gem5  v20.1.0.0
decoder.hh
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40 
41 #ifndef __ARCH_ARM_DECODER_HH__
42 #define __ARCH_ARM_DECODER_HH__
43 
44 #include <cassert>
45 
46 #include "arch/arm/miscregs.hh"
47 #include "arch/arm/types.hh"
49 #include "arch/generic/decoder.hh"
50 #include "base/types.hh"
51 #include "cpu/static_inst.hh"
52 #include "enums/DecoderFlavor.hh"
53 
54 namespace ArmISA
55 {
56 
57 class ISA;
58 class Decoder : public InstDecoder
59 {
60  protected:
61  //The extended machine instruction being generated
64  bool bigThumb;
65  bool instDone;
66  bool outOfBytes;
67  int offset;
68  bool foundIt;
69  ITSTATE itBits;
70 
71  int fpscrLen;
73 
78  int sveLen;
79 
80  Enums::DecoderFlavor decoderFlavor;
81 
84 
89  void process();
90 
95  void consumeBytes(int numBytes);
96 
97  public: // Decoder API
98  Decoder(ISA* isa = nullptr);
99 
101  void reset();
102 
110  bool needMoreBytes() const { return outOfBytes; }
111 
120  bool instReady() const { return instDone; }
121 
148  void moreBytes(const PCState &pc, Addr fetchPC, MachInst inst);
149 
162 
173  {
174  return defaultCache.decode(this, mach_inst, addr);
175  }
176 
190 
196  void takeOverFrom(Decoder *old) {}
197 
198 
199  public: // ARM-specific decoder state manipulation
200  void setContext(FPSCR fpscr)
201  {
202  fpscrLen = fpscr.len;
203  fpscrStride = fpscr.stride;
204  }
205 
206  void setSveLen(uint8_t len)
207  {
208  sveLen = len;
209  }
210 };
211 
212 } // namespace ArmISA
213 
214 #endif // __ARCH_ARM_DECODER_HH__
ArmISA::Decoder::emi
ExtMachInst emi
Definition: decoder.hh:62
ArmISA::Decoder::takeOverFrom
void takeOverFrom(Decoder *old)
Take over the state from an old decoder when switching CPUs.
Definition: decoder.hh:196
ArmISA::Decoder::process
void process()
Pre-decode an instruction from the current state of the decoder.
Definition: decoder.cc:77
ArmISA::Decoder::data
MachInst data
Definition: decoder.hh:63
GenericISA::BasicDecodeCache::decode
StaticInstPtr decode(TheISA::Decoder *const decoder, TheISA::ExtMachInst mach_inst, Addr addr)
Decode a machine instruction.
Definition: decode_cache.cc:40
ArmISA::Decoder::fpscrLen
int fpscrLen
Definition: decoder.hh:71
ArmISA::Decoder::Decoder
Decoder(ISA *isa=nullptr)
Definition: decoder.cc:55
ArmISA::MachInst
uint32_t MachInst
Definition: types.hh:52
decode_cache.hh
ArmISA::Decoder::decoderFlavor
Enums::DecoderFlavor decoderFlavor
Definition: decoder.hh:80
ArmISA::Decoder::outOfBytes
bool outOfBytes
Definition: decoder.hh:66
GenericISA::BasicDecodeCache
Definition: decode_cache.hh:45
ArmISA::ISA
Definition: isa.hh:65
ArmISA
Definition: ccregs.hh:41
types.hh
ArmISA::Decoder::offset
int offset
Definition: decoder.hh:67
ArmISA::Decoder::decode
StaticInstPtr decode(ExtMachInst mach_inst, Addr addr)
Decode a pre-decoded machine instruction.
Definition: decoder.hh:172
ArmISA::Decoder::decode
StaticInstPtr decode(ArmISA::PCState &pc)
Decode an instruction or fetch it from the code cache.
Definition: decoder.cc:172
decoder.hh
MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:240
ArmISA::Decoder::needMoreBytes
bool needMoreBytes() const
Can the decoder accept more data?
Definition: decoder.hh:110
ArmISA::Decoder::instDone
bool instDone
Definition: decoder.hh:65
ArmISA::Decoder::sveLen
int sveLen
SVE vector length, encoded in the same format as the ZCR_EL<x>.LEN bitfields.
Definition: decoder.hh:78
static_inst.hh
ArmISA::Decoder::itBits
ITSTATE itBits
Definition: decoder.hh:69
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
ArmISA::Decoder::reset
void reset()
Reset the decoders internal state.
Definition: decoder.cc:66
ArmISA::Decoder::decodeInst
StaticInstPtr decodeInst(ExtMachInst mach_inst)
Decode a machine instruction without calling the cache.
ArmISA::Decoder
Definition: decoder.hh:58
ArmISA::Decoder::setSveLen
void setSveLen(uint8_t len)
Definition: decoder.hh:206
miscregs.hh
ArmISA::Decoder::defaultCache
static GenericISA::BasicDecodeCache defaultCache
A cache of decoded instruction objects.
Definition: decoder.hh:83
ArmISA::Decoder::instReady
bool instReady() const
Is an instruction ready to be decoded?
Definition: decoder.hh:120
MipsISA::PCState
GenericISA::DelaySlotPCState< MachInst > PCState
Definition: types.hh:41
types.hh
ArmISA::Decoder::setContext
void setContext(FPSCR fpscr)
Definition: decoder.hh:200
ArmISA::len
Bitfield< 18, 16 > len
Definition: miscregs_types.hh:439
addr
ip6_addr_t addr
Definition: inet.hh:423
InstDecoder
Definition: decoder.hh:34
RefCountingPtr< StaticInst >
ArmISA::Decoder::fpscrStride
int fpscrStride
Definition: decoder.hh:72
ArmISA::Decoder::foundIt
bool foundIt
Definition: decoder.hh:68
ArmISA::Decoder::moreBytes
void moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
Feed data to the decoder.
Definition: decoder.cc:153
ArmISA::Decoder::bigThumb
bool bigThumb
Definition: decoder.hh:64
ArmISA::Decoder::consumeBytes
void consumeBytes(int numBytes)
Consume bytes by moving the offset into the data word and sanity check the results.
Definition: decoder.cc:144
MipsISA::ExtMachInst
uint64_t ExtMachInst
Definition: types.hh:39

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