gem5  v20.1.0.0
interrupts.cc
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37 
38 #include "arch/arm/interrupts.hh"
39 
40 #include "arch/arm/system.hh"
41 
43 ArmInterruptsParams::create()
44 {
45  return new ArmISA::Interrupts(this);
46 }
47 
48 bool
50 {
51  // Table G1-17~19 of ARM V8 ARM
53  bool highest_el_is_64 = ArmSystem::highestELIs64(tc);
54 
55  CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
56  SCR scr;
57  HCR hcr;
58  hcr = tc->readMiscReg(MISCREG_HCR);
60  bool cpsr_mask_bit, scr_routing_bit, scr_fwaw_bit, hcr_mask_override_bit;
61 
62  if (!highest_el_is_64)
63  scr = tc->readMiscReg(MISCREG_SCR);
64  else
66 
67  bool is_secure = isSecure(tc);
68 
69  switch(int_type) {
70  case INT_FIQ:
71  cpsr_mask_bit = cpsr.f;
72  scr_routing_bit = scr.fiq;
73  scr_fwaw_bit = scr.fw;
74  hcr_mask_override_bit = hcr.fmo;
75  break;
76  case INT_IRQ:
77  cpsr_mask_bit = cpsr.i;
78  scr_routing_bit = scr.irq;
79  scr_fwaw_bit = 1;
80  hcr_mask_override_bit = hcr.imo;
81  break;
82  case INT_ABT:
83  cpsr_mask_bit = cpsr.a;
84  scr_routing_bit = scr.ea;
85  scr_fwaw_bit = scr.aw;
86  hcr_mask_override_bit = hcr.amo;
87  break;
88  default:
89  panic("Unhandled interrupt type!");
90  }
91 
92  if (hcr.tge)
93  hcr_mask_override_bit = 1;
94 
95  if (!highest_el_is_64) {
96  // AArch32
97  if (!scr_routing_bit) {
98  // SCR IRQ == 0
99  if (!hcr_mask_override_bit)
100  mask = INT_MASK_M;
101  else {
102  if (!is_secure && (el == EL0 || el == EL1))
103  mask = INT_MASK_T;
104  else
105  mask = INT_MASK_M;
106  }
107  } else {
108  // SCR IRQ == 1
109  if ((!is_secure) &&
110  (hcr_mask_override_bit ||
111  (!scr_fwaw_bit && !hcr_mask_override_bit)))
112  mask = INT_MASK_T;
113  else
114  mask = INT_MASK_M;
115  }
116  } else {
117  // AArch64
118  if (!scr_routing_bit) {
119  // SCR IRQ == 0
120  if (!scr.rw) {
121  // SCR RW == 0
122  if (!hcr_mask_override_bit) {
123  if (el == EL3)
124  mask = INT_MASK_P;
125  else
126  mask = INT_MASK_M;
127  } else {
128  if (el == EL3)
129  mask = INT_MASK_T;
130  else if (is_secure || el == EL2)
131  mask = INT_MASK_M;
132  else
133  mask = INT_MASK_T;
134  }
135  } else {
136  // SCR RW == 1
137  if (!hcr_mask_override_bit) {
138  if (el == EL3 || el == EL2)
139  mask = INT_MASK_P;
140  else
141  mask = INT_MASK_M;
142  } else {
143  if (el == EL3)
144  mask = INT_MASK_P;
145  else if (is_secure || el == EL2)
146  mask = INT_MASK_M;
147  else
148  mask = INT_MASK_T;
149  }
150  }
151  } else {
152  // SCR IRQ == 1
153  if (el == EL3)
154  mask = INT_MASK_M;
155  else
156  mask = INT_MASK_T;
157  }
158  }
159 
160  return ((mask == INT_MASK_T) ||
161  ((mask == INT_MASK_M) && !cpsr_mask_bit)) &&
162  (mask != INT_MASK_P);
163 }
164 
ArmISA::Interrupts::INT_MASK_P
@ INT_MASK_P
Definition: interrupts.hh:132
ArmISA::EL2
@ EL2
Definition: types.hh:624
ArmSystem::highestELIs64
bool highestELIs64() const
Returns true if the register width of the highest implemented exception level is 64 bits (ARMv8)
Definition: system.hh:204
ArmISA::INT_FIQ
@ INT_FIQ
Definition: interrupts.hh:62
ArmISA::EL0
@ EL0
Definition: types.hh:622
sc_dt::int_type
int64 int_type
Definition: sc_nbdefs.hh:240
ArmISA::currEL
static ExceptionLevel currEL(const ThreadContext *tc)
Definition: utility.hh:143
ArmISA::EL3
@ EL3
Definition: types.hh:625
ArmISA::Interrupts::INT_MASK_M
@ INT_MASK_M
Definition: interrupts.hh:130
ArmISA::Interrupts
Definition: interrupts.hh:69
system.hh
ArmISA::Interrupts::INT_MASK_T
@ INT_MASK_T
Definition: interrupts.hh:131
ArmISA::Interrupts::takeInt
bool takeInt(InterruptTypes int_type) const
Definition: interrupts.cc:49
interrupts.hh
ArmISA::MISCREG_HCR
@ MISCREG_HCR
Definition: miscregs.hh:242
ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:621
ArmISA::INT_ABT
@ INT_ABT
Definition: interrupts.hh:60
ArmISA::el
Bitfield< 3, 2 > el
Definition: miscregs_types.hh:69
ArmISA::InterruptTypes
InterruptTypes
Definition: interrupts.hh:57
ArmISA::EL1
@ EL1
Definition: types.hh:623
ArmISA::Interrupts::InterruptMask
InterruptMask
Definition: interrupts.hh:129
ArmISA::MISCREG_SCR_EL3
@ MISCREG_SCR_EL3
Definition: miscregs.hh:585
ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition: miscregs.hh:57
ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
BaseInterrupts::tc
ThreadContext * tc
Definition: interrupts.hh:40
ArmISA::MISCREG_SCR
@ MISCREG_SCR
Definition: miscregs.hh:237
ArmISA::INT_IRQ
@ INT_IRQ
Definition: interrupts.hh:61
ArmISA::mask
Bitfield< 28, 24 > mask
Definition: miscregs_types.hh:711
ArmISA::isSecure
bool isSecure(ThreadContext *tc)
Definition: utility.cc:174
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:171

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