gem5  v20.1.0.0
utility.cc
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1 /*
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37 
38 #include "arch/arm/utility.hh"
39 
40 #include <memory>
41 
42 #include "arch/arm/faults.hh"
43 #include "arch/arm/interrupts.hh"
44 #include "arch/arm/isa_traits.hh"
45 #include "arch/arm/system.hh"
46 #include "arch/arm/tlb.hh"
47 #include "cpu/base.hh"
48 #include "cpu/checker/cpu.hh"
49 #include "cpu/thread_context.hh"
50 #include "mem/port_proxy.hh"
51 #include "sim/full_system.hh"
52 
53 namespace ArmISA
54 {
55 
56 uint64_t
57 getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
58 {
59  if (!FullSystem) {
60  panic("getArgument() only implemented for full system mode.\n");
61  M5_DUMMY_RETURN
62  }
63 
64  if (fp)
65  panic("getArgument(): Floating point arguments not implemented\n");
66 
67  if (inAArch64(tc)) {
68  if (size == (uint16_t)(-1))
69  size = sizeof(uint64_t);
70 
71  if (number < 8 /*NumArgumentRegs64*/) {
72  return tc->readIntReg(number);
73  } else {
74  panic("getArgument(): No support reading stack args for AArch64\n");
75  }
76  } else {
77  if (size == (uint16_t)(-1))
78  size = sizeof(uint32_t);
79 
80  if (number < NumArgumentRegs) {
81  // If the argument is 64 bits, it must be in an even regiser
82  // number. Increment the number here if it isn't even.
83  if (size == sizeof(uint64_t)) {
84  if ((number % 2) != 0)
85  number++;
86  // Read the two halves of the data. Number is inc here to
87  // get the second half of the 64 bit reg.
88  uint64_t tmp;
89  tmp = tc->readIntReg(number++);
90  tmp |= tc->readIntReg(number) << 32;
91  return tmp;
92  } else {
93  return tc->readIntReg(number);
94  }
95  } else {
97  PortProxy &vp = tc->getVirtProxy();
98  uint64_t arg;
99  if (size == sizeof(uint64_t)) {
100  // If the argument is even it must be aligned
101  if ((number % 2) != 0)
102  number++;
103  arg = vp.read<uint64_t>(sp +
104  (number-NumArgumentRegs) * sizeof(uint32_t));
105  // since two 32 bit args == 1 64 bit arg, increment number
106  number++;
107  } else {
108  arg = vp.read<uint32_t>(sp +
109  (number-NumArgumentRegs) * sizeof(uint32_t));
110  }
111  return arg;
112  }
113  }
114  panic("getArgument() should always return\n");
115 }
116 
117 static void
119 {
120  auto src_mode = RenameMode<ArmISA::ISA>::mode(src->pcState());
121 
122  // The way vector registers are copied (VecReg vs VecElem) is relevant
123  // in the O3 model only.
124  if (src_mode == Enums::Full) {
125  for (auto idx = 0; idx < NumVecRegs; idx++)
126  dest->setVecRegFlat(idx, src->readVecRegFlat(idx));
127  } else {
128  for (auto idx = 0; idx < NumVecRegs; idx++)
129  for (auto elem_idx = 0; elem_idx < NumVecElemPerVecReg; elem_idx++)
130  dest->setVecElemFlat(
131  idx, elem_idx, src->readVecElemFlat(idx, elem_idx));
132  }
133 }
134 
135 void
137 {
138  for (int i = 0; i < NumIntRegs; i++)
139  dest->setIntRegFlat(i, src->readIntRegFlat(i));
140 
141  for (int i = 0; i < NumFloatRegs; i++)
142  dest->setFloatRegFlat(i, src->readFloatRegFlat(i));
143 
144  for (int i = 0; i < NumCCRegs; i++)
145  dest->setCCReg(i, src->readCCReg(i));
146 
147  for (int i = 0; i < NumMiscRegs; i++)
149 
150  copyVecRegs(src, dest);
151 
152  // setMiscReg "with effect" will set the misc register mapping correctly.
153  // e.g. updateRegMap(val)
155 
156  // Copy over the PC State
157  dest->pcState(src->pcState());
158 
159  // Invalidate the tlb misc register cache
160  dynamic_cast<TLB *>(dest->getITBPtr())->invalidateMiscReg();
161  dynamic_cast<TLB *>(dest->getDTBPtr())->invalidateMiscReg();
162 }
163 
164 void
166 {
167  if (tc->readMiscReg(MISCREG_SEV_MAILBOX) == 0) {
168  // Post Interrupt and wake cpu if needed
169  tc->getCpuPtr()->postInterrupt(tc->threadId(), INT_SEV, 0);
170  }
171 }
172 
173 bool
175 {
176  CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
177  if (ArmSystem::haveEL(tc, EL3) && !cpsr.width && currEL(tc) == EL3)
178  return true;
179  if (ArmSystem::haveEL(tc, EL3) && cpsr.width && cpsr.mode == MODE_MON)
180  return true;
181  else
182  return isSecureBelowEL3(tc);
183 }
184 
185 bool
187 {
188  SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
189  return ArmSystem::haveEL(tc, EL3) && scr.ns == 0;
190 }
191 
194 {
195  bool route_to_el2;
196  if (ArmSystem::haveEL(tc, EL2) && (!secure || HaveSecureEL2Ext(tc))) {
197  if (ELIs32(tc, EL2)) {
198  const HCR hcr = tc->readMiscReg(MISCREG_HCR);
199  const HDCR hdcr = tc->readMiscRegNoEffect(MISCREG_HDCR);
200  route_to_el2 = (hdcr.tde == 1 || hcr.tge == 1);
201  } else {
202  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
203  const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
204  route_to_el2 = (mdcr.tde == 1 || hcr.tge == 1);
205  }
206  }else{
207  route_to_el2 = false;
208  }
209  ExceptionLevel target;
210  if (route_to_el2) {
211  target = EL2;
212  } else if (ArmSystem::haveEL(tc, EL3) && !ArmSystem::highestELIs64(tc)
213  && secure) {
214  target = EL3;
215  } else {
216  target = EL1;
217  }
218  return target;
219 }
220 
221 bool
223 {
224  CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
225  return opModeIs64((OperatingMode) (uint8_t) cpsr.mode);
226 }
227 
228 bool
230 {
231  TTBCR ttbcr = tc->readMiscReg(MISCREG_TTBCR);
232  return ArmSystem::haveLPAE(tc) && ttbcr.eae;
233 }
234 
235 RegVal
237 {
238  const ExceptionLevel current_el = currEL(tc);
239 
240  const bool is_secure = isSecureBelowEL3(tc);
241 
242  switch (current_el) {
243  case EL0:
244  // Note: in MsrMrs instruction we read the register value before
245  // checking access permissions. This means that EL0 entry must
246  // be part of the table even if MPIDR is not accessible in user
247  // mode.
248  warn_once("Trying to read MPIDR at EL0\n");
250  case EL1:
251  if (ArmSystem::haveEL(tc, EL2) && !is_secure)
252  return tc->readMiscReg(MISCREG_VMPIDR_EL2);
253  else
254  return getMPIDR(arm_sys, tc);
255  case EL2:
256  case EL3:
257  return getMPIDR(arm_sys, tc);
258  default:
259  panic("Invalid EL for reading MPIDR register\n");
260  }
261 }
262 
263 RegVal
265 {
266  // Multiprocessor Affinity Register MPIDR from Cortex(tm)-A15 Technical
267  // Reference Manual
268  //
269  // bit 31 - Multi-processor extensions available
270  // bit 30 - Uni-processor system
271  // bit 24 - Multi-threaded cores
272  // bit 11-8 - Cluster ID
273  // bit 1-0 - CPU ID
274  //
275  // We deliberately extend both the Cluster ID and CPU ID fields to allow
276  // for simulation of larger systems
277  assert((0 <= tc->cpuId()) && (tc->cpuId() < 256));
278  assert(tc->socketId() < 65536);
279 
280  RegVal mpidr = 0x80000000;
281 
282  if (!arm_sys->multiProc)
283  replaceBits(mpidr, 30, 1);
284 
285  if (arm_sys->multiThread)
286  replaceBits(mpidr, 24, 1);
287 
288  // Get Affinity numbers
289  mpidr |= getAffinity(arm_sys, tc);
290  return mpidr;
291 }
292 
293 static RegVal
295 {
296  return arm_sys->multiThread ? tc->socketId() << 16 : 0;
297 }
298 
299 static RegVal
301 {
302  return arm_sys->multiThread ? tc->cpuId() << 8 : tc->socketId() << 8;
303 }
304 
305 static RegVal
307 {
308  return arm_sys->multiThread ? tc->threadId() : tc->cpuId();
309 }
310 
311 RegVal
313 {
314  return getAff2(arm_sys, tc) | getAff1(arm_sys, tc) | getAff0(arm_sys, tc);
315 }
316 
317 bool
319 {
320  AA64ISAR1 id_aa64isar1 = tc->readMiscReg(MISCREG_ID_AA64ISAR1_EL1);
321  return id_aa64isar1.api | id_aa64isar1.apa |
322  id_aa64isar1.gpi | id_aa64isar1.gpa;
323 }
324 
325 bool
327 {
328  AA64MMFR1 id_aa64mmfr1 = tc->readMiscReg(MISCREG_ID_AA64MMFR1_EL1);
329  return id_aa64mmfr1.vh;
330 }
331 
334 {
335 
336  SCR scr = tc->readMiscReg(MISCREG_SCR);
337  if (el != EL0)
338  return el;
339  else if (ArmSystem::haveEL(tc, EL3) && ELIs32(tc, EL3) && scr.ns == 0)
340  return EL3;
341  else if (HaveVirtHostExt(tc) && ELIsInHost(tc, el))
342  return EL2;
343  else
344  return EL1;
345 }
346 
347 bool
349 {
350  AA64PFR0 id_aa64pfr0 = tc->readMiscReg(MISCREG_ID_AA64PFR0_EL1);
351  return id_aa64pfr0.sel2;
352 }
353 
354 bool
356 {
357  SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
358  if (ArmSystem::haveEL(tc, EL2) && HaveSecureEL2Ext(tc) &&
359  !ELIs32(tc, EL2)) {
360  if (ArmSystem::haveEL(tc, EL3))
361  return !ELIs32(tc, EL3) && scr.eel2;
362  else
363  return isSecure(tc);
364  }
365  return false;
366 }
367 
368 bool
370 {
371  SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
372  return ArmSystem::haveEL(tc, EL2) &&
373  (!ArmSystem::haveEL(tc, EL3) || scr.ns || IsSecureEL2Enabled(tc));
374 }
375 
376 bool
378 {
379  return !ELIs32(tc, el);
380 }
381 
382 bool
384 {
385  bool known, aarch32;
386  std::tie(known, aarch32) = ELUsingAArch32K(tc, el);
387  panic_if(!known, "EL state is UNKNOWN");
388  return aarch32;
389 }
390 
391 bool
393 {
394  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
395  return (ArmSystem::haveEL(tc, EL2) &&
396  (IsSecureEL2Enabled(tc) || !isSecureBelowEL3(tc)) &&
397  HaveVirtHostExt(tc) && !ELIs32(tc, EL2) && hcr.e2h == 1 &&
398  (el == EL2 || (el == EL0 && hcr.tge == 1)));
399 }
400 
403 {
404  bool secure = isSecureBelowEL3(tc);
405  return ELStateUsingAArch32K(tc, el, secure);
406 }
407 
408 bool
410 {
411  if (!ArmSystem::haveEL(tc, el))
412  return false;
413  else if (!ArmSystem::highestELIs64(tc))
414  return true;
415  else if (ArmSystem::highestEL(tc) == el)
416  return false;
417  else if (el == EL0)
418  return true;
419  return true;
420 }
421 
424 {
425  // Return true if the specified EL is in aarch32 state.
426  const bool have_el3 = ArmSystem::haveSecurity(tc);
427  const bool have_el2 = ArmSystem::haveVirtualization(tc);
428 
429  panic_if(el == EL2 && !have_el2, "Asking for EL2 when it doesn't exist");
430  panic_if(el == EL3 && !have_el3, "Asking for EL3 when it doesn't exist");
431 
432  bool known, aarch32;
433  known = aarch32 = false;
434  if (!haveAArch32EL(tc, el)) {
435  // Target EL is the highest one in a system where
436  // the highest is using AArch64.
437  known = true; aarch32 = false;
438  } else if (secure && el == EL2) {
439  known = true; aarch32 = false;
440  } else if (!ArmSystem::highestELIs64(tc)) {
441  // All ELs are using AArch32:
442  known = true; aarch32 = true;
443  } else if (ArmSystem::highestEL(tc) == el) {
444  known = true; aarch32 = false;
445  } else {
446  SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
447  bool aarch32_below_el3 = have_el3 && scr.rw == 0 &&
448  (!secure || !HaveSecureEL2Ext(tc) || !scr.eel2);
449 
450  HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
451  bool sec_el2 = HaveSecureEL2Ext(tc) && scr.eel2;
452  bool aarch32_at_el1 = (aarch32_below_el3 ||
453  (have_el2 && (sec_el2 || !secure) &&
454  hcr.rw == 0 && !(hcr.e2h && hcr.tge &&
455  HaveVirtHostExt(tc))));
456 
457  // Only know if EL0 using AArch32 from PSTATE
458  if (el == EL0 && !aarch32_at_el1) {
459  // EL0 controlled by PSTATE
460  CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
461  known = (currEL(tc) == EL0);
462  aarch32 = (cpsr.width == 1);
463  } else {
464  known = true;
465  aarch32 = (aarch32_below_el3 && el != EL3)
466  || (aarch32_at_el1 && (el == EL0 || el == EL1) );
467  }
468  }
469 
470  return std::make_pair(known, aarch32);
471 }
472 
474 {
475 
476  bool known, aarch32;
477  std::tie(known, aarch32) = ELStateUsingAArch32K(tc, el, secure);
478  panic_if(!known, "EL state is UNKNOWN");
479  return aarch32;
480 }
481 
482 bool
484 {
485  switch (currEL(tc)) {
486  case EL3:
487  return ((SCTLR) tc->readMiscRegNoEffect(MISCREG_SCTLR_EL3)).ee;
488  case EL2:
489  return ((SCTLR) tc->readMiscRegNoEffect(MISCREG_SCTLR_EL2)).ee;
490  case EL1:
491  return ((SCTLR) tc->readMiscRegNoEffect(MISCREG_SCTLR_EL1)).ee;
492  case EL0:
493  return ((SCTLR) tc->readMiscRegNoEffect(MISCREG_SCTLR_EL1)).e0e;
494  default:
495  panic("Invalid exception level");
496  break;
497  }
498 }
499 
500 bool
502 {
504 }
505 
506 bool
508 {
510 }
511 
512 int
513 computeAddrTop(ThreadContext *tc, bool selbit, bool isInstr,
514  TCR tcr, ExceptionLevel el)
515 {
516  bool tbi = false;
517  bool tbid = false;
518  ExceptionLevel regime = s1TranslationRegime(tc, el);
519  if (ELIs32(tc, regime)) {
520  return 31;
521  } else {
522  switch (regime) {
523  case EL1:
524  {
525  //TCR tcr = tc->readMiscReg(MISCREG_TCR_EL1);
526  tbi = selbit? tcr.tbi1 : tcr.tbi0;
527  tbid = selbit? tcr.tbid1 : tcr.tbid0;
528  break;
529  }
530  case EL2:
531  {
532  TCR tcr = tc->readMiscReg(MISCREG_TCR_EL2);
533  if (HaveVirtHostExt(tc) && ELIsInHost(tc, el)) {
534  tbi = selbit? tcr.tbi1 : tcr.tbi0;
535  tbid = selbit? tcr.tbid1 : tcr.tbid0;
536  } else {
537  tbi = tcr.tbi;
538  tbid = tcr.tbid;
539  }
540  break;
541  }
542  case EL3:
543  {
544  TCR tcr = tc->readMiscReg(MISCREG_TCR_EL3);
545  tbi = tcr.tbi;
546  tbid = tcr.tbid;
547  break;
548  }
549  default:
550  break;
551  }
552 
553  }
554  int res = (tbi && (!tbid || !isInstr))? 55: 63;
555  return res;
556 }
557 Addr
559  TCR tcr, bool isInstr)
560 {
561  bool selbit = bits(addr, 55);
562  int topbit = computeAddrTop(tc, selbit, isInstr, tcr, el);
563 
564  if (topbit == 63) {
565  return addr;
566  } else if (selbit && (el == EL1 || el == EL0 || ELIsInHost(tc, el))) {
567  uint64_t mask = ((uint64_t)0x1 << topbit) -1;
568  addr = addr | ~mask;
569  } else {
570  addr = bits(addr, topbit, 0);
571  }
572  return addr; // Nothing to do if this is not a tagged address
573 }
574 
575 Addr
577  bool isInstr)
578 {
579 
580  TCR tcr = tc->readMiscReg(MISCREG_TCR_EL1);
581  return purifyTaggedAddr(addr, tc, el, tcr, isInstr);
582 }
583 
584 Addr
586 {
587  return addr & ~(PageBytes - 1);
588 }
589 
590 Addr
592 {
593  return (addr + PageBytes - 1) & ~(PageBytes - 1);
594 }
595 
596 Fault
597 mcrMrc15Trap(const MiscRegIndex miscReg, ExtMachInst machInst,
598  ThreadContext *tc, uint32_t imm)
599 {
601  if (mcrMrc15TrapToHyp(miscReg, tc, imm, &ec))
602  return std::make_shared<HypervisorTrap>(machInst, imm, ec);
603  return AArch64AArch32SystemAccessTrap(miscReg, machInst, tc, imm, ec);
604 }
605 
606 bool
607 mcrMrc15TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc, uint32_t iss,
609 {
610  bool isRead;
611  uint32_t crm;
612  IntRegIndex rt;
613  uint32_t crn;
614  uint32_t opc1;
615  uint32_t opc2;
616  bool trapToHype = false;
617 
618  const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
619  const HCR hcr = tc->readMiscReg(MISCREG_HCR);
620  const SCR scr = tc->readMiscReg(MISCREG_SCR);
621  const HDCR hdcr = tc->readMiscReg(MISCREG_HDCR);
622  const HSTR hstr = tc->readMiscReg(MISCREG_HSTR);
623  const HCPTR hcptr = tc->readMiscReg(MISCREG_HCPTR);
624 
625  if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) {
626  mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2);
627  trapToHype = ((uint32_t) hstr) & (1 << crn);
628  trapToHype |= hdcr.tpm && (crn == 9) && (crm >= 12);
629  trapToHype |= hcr.tidcp && (
630  ((crn == 9) && ((crm <= 2) || ((crm >= 5) && (crm <= 8)))) ||
631  ((crn == 10) && ((crm <= 1) || (crm == 4) || (crm == 8))) ||
632  ((crn == 11) && ((crm <= 8) || (crm == 15))) );
633 
634  if (!trapToHype) {
635  switch (unflattenMiscReg(miscReg)) {
636  case MISCREG_CPACR:
637  trapToHype = hcptr.tcpac;
638  break;
639  case MISCREG_REVIDR:
640  case MISCREG_TCMTR:
641  case MISCREG_TLBTR:
642  case MISCREG_AIDR:
643  trapToHype = hcr.tid1;
644  break;
645  case MISCREG_CTR:
646  case MISCREG_CCSIDR:
647  case MISCREG_CLIDR:
648  case MISCREG_CSSELR:
649  trapToHype = hcr.tid2;
650  break;
651  case MISCREG_ID_PFR0:
652  case MISCREG_ID_PFR1:
653  case MISCREG_ID_DFR0:
654  case MISCREG_ID_AFR0:
655  case MISCREG_ID_MMFR0:
656  case MISCREG_ID_MMFR1:
657  case MISCREG_ID_MMFR2:
658  case MISCREG_ID_MMFR3:
659  case MISCREG_ID_ISAR0:
660  case MISCREG_ID_ISAR1:
661  case MISCREG_ID_ISAR2:
662  case MISCREG_ID_ISAR3:
663  case MISCREG_ID_ISAR4:
664  case MISCREG_ID_ISAR5:
665  trapToHype = hcr.tid3;
666  break;
667  case MISCREG_DCISW:
668  case MISCREG_DCCSW:
669  case MISCREG_DCCISW:
670  trapToHype = hcr.tsw;
671  break;
672  case MISCREG_DCIMVAC:
673  case MISCREG_DCCIMVAC:
674  case MISCREG_DCCMVAC:
675  trapToHype = hcr.tpc;
676  break;
677  case MISCREG_ICIMVAU:
678  case MISCREG_ICIALLU:
679  case MISCREG_ICIALLUIS:
680  case MISCREG_DCCMVAU:
681  trapToHype = hcr.tpu;
682  break;
683  case MISCREG_TLBIALLIS:
684  case MISCREG_TLBIMVAIS:
685  case MISCREG_TLBIASIDIS:
686  case MISCREG_TLBIMVAAIS:
687  case MISCREG_TLBIMVALIS:
688  case MISCREG_TLBIMVAALIS:
689  case MISCREG_DTLBIALL:
690  case MISCREG_ITLBIALL:
691  case MISCREG_DTLBIMVA:
692  case MISCREG_ITLBIMVA:
693  case MISCREG_DTLBIASID:
694  case MISCREG_ITLBIASID:
695  case MISCREG_TLBIMVAA:
696  case MISCREG_TLBIALL:
697  case MISCREG_TLBIMVA:
698  case MISCREG_TLBIMVAL:
699  case MISCREG_TLBIMVAAL:
700  case MISCREG_TLBIASID:
701  trapToHype = hcr.ttlb;
702  break;
703  case MISCREG_ACTLR:
704  trapToHype = hcr.tac;
705  break;
706  case MISCREG_SCTLR:
707  case MISCREG_TTBR0:
708  case MISCREG_TTBR1:
709  case MISCREG_TTBCR:
710  case MISCREG_DACR:
711  case MISCREG_DFSR:
712  case MISCREG_IFSR:
713  case MISCREG_DFAR:
714  case MISCREG_IFAR:
715  case MISCREG_ADFSR:
716  case MISCREG_AIFSR:
717  case MISCREG_PRRR:
718  case MISCREG_NMRR:
719  case MISCREG_MAIR0:
720  case MISCREG_MAIR1:
721  case MISCREG_CONTEXTIDR:
722  trapToHype = hcr.tvm & !isRead;
723  break;
724  case MISCREG_PMCR:
725  trapToHype = hdcr.tpmcr;
726  break;
727  // GICv3 regs
728  case MISCREG_ICC_SGI0R:
729  {
730  auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
731  if (isa->haveGICv3CpuIfc())
732  trapToHype = hcr.fmo;
733  }
734  break;
735  case MISCREG_ICC_SGI1R:
736  case MISCREG_ICC_ASGI1R:
737  {
738  auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
739  if (isa->haveGICv3CpuIfc())
740  trapToHype = hcr.imo;
741  }
742  break;
744  // CNTFRQ may be trapped only on reads
745  // CNTPCT and CNTVCT are read-only
746  if (MISCREG_CNTFRQ <= miscReg && miscReg <= MISCREG_CNTVCT &&
747  !isRead)
748  break;
749  trapToHype = isGenericTimerHypTrap(miscReg, tc, ec);
750  break;
751  // No default action needed
752  default:
753  break;
754  }
755  }
756  }
757  return trapToHype;
758 }
759 
760 
761 bool
762 mcrMrc14TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr,
763  HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss)
764 {
765  bool isRead;
766  uint32_t crm;
767  IntRegIndex rt;
768  uint32_t crn;
769  uint32_t opc1;
770  uint32_t opc2;
771  bool trapToHype = false;
772 
773  if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) {
774  mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2);
775  inform("trap check M:%x N:%x 1:%x 2:%x hdcr %x, hcptr %x, hstr %x\n",
776  crm, crn, opc1, opc2, hdcr, hcptr, hstr);
777  trapToHype = hdcr.tda && (opc1 == 0);
778  trapToHype |= hcptr.tta && (opc1 == 1);
779  if (!trapToHype) {
780  switch (unflattenMiscReg(miscReg)) {
781  case MISCREG_DBGOSLSR:
782  case MISCREG_DBGOSLAR:
783  case MISCREG_DBGOSDLR:
784  case MISCREG_DBGPRCR:
785  trapToHype = hdcr.tdosa;
786  break;
787  case MISCREG_DBGDRAR:
788  case MISCREG_DBGDSAR:
789  trapToHype = hdcr.tdra;
790  break;
791  case MISCREG_JIDR:
792  trapToHype = hcr.tid0;
793  break;
794  case MISCREG_JOSCR:
795  case MISCREG_JMCR:
796  trapToHype = hstr.tjdbx;
797  break;
798  case MISCREG_TEECR:
799  case MISCREG_TEEHBR:
800  trapToHype = hstr.ttee;
801  break;
802  // No default action needed
803  default:
804  break;
805  }
806  }
807  }
808  return trapToHype;
809 }
810 
811 Fault
812 mcrrMrrc15Trap(const MiscRegIndex miscReg, ExtMachInst machInst,
813  ThreadContext *tc, uint32_t imm)
814 {
816  if (mcrrMrrc15TrapToHyp(miscReg, tc, imm, &ec))
817  return std::make_shared<HypervisorTrap>(machInst, imm, ec);
818  return AArch64AArch32SystemAccessTrap(miscReg, machInst, tc, imm, ec);
819 }
820 
821 bool
823  uint32_t iss, ExceptionClass *ec)
824 {
825  uint32_t crm;
826  IntRegIndex rt;
827  uint32_t crn;
828  uint32_t opc1;
829  uint32_t opc2;
830  bool isRead;
831  bool trapToHype = false;
832 
833  const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
834  const HCR hcr = tc->readMiscReg(MISCREG_HCR);
835  const SCR scr = tc->readMiscReg(MISCREG_SCR);
836  const HSTR hstr = tc->readMiscReg(MISCREG_HSTR);
837 
838  if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) {
839  // This is technically the wrong function, but we can re-use it for
840  // the moment because we only need one field, which overlaps with the
841  // mcrmrc layout
842  mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2);
843  trapToHype = ((uint32_t) hstr) & (1 << crm);
844 
845  if (!trapToHype) {
846  switch (unflattenMiscReg(miscReg)) {
847  case MISCREG_SCTLR:
848  case MISCREG_TTBR0:
849  case MISCREG_TTBR1:
850  case MISCREG_TTBCR:
851  case MISCREG_DACR:
852  case MISCREG_DFSR:
853  case MISCREG_IFSR:
854  case MISCREG_DFAR:
855  case MISCREG_IFAR:
856  case MISCREG_ADFSR:
857  case MISCREG_AIFSR:
858  case MISCREG_PRRR:
859  case MISCREG_NMRR:
860  case MISCREG_MAIR0:
861  case MISCREG_MAIR1:
862  case MISCREG_CONTEXTIDR:
863  trapToHype = hcr.tvm & !isRead;
864  break;
866  // CNTFRQ may be trapped only on reads
867  // CNTPCT and CNTVCT are read-only
868  if (MISCREG_CNTFRQ <= miscReg && miscReg <= MISCREG_CNTVCT &&
869  !isRead)
870  break;
871  trapToHype = isGenericTimerHypTrap(miscReg, tc, ec);
872  break;
873  // No default action needed
874  default:
875  break;
876  }
877  }
878  }
879  return trapToHype;
880 }
881 
882 Fault
884  ExtMachInst machInst, ThreadContext *tc,
885  uint32_t imm, ExceptionClass ec)
886 {
887  if (currEL(tc) <= EL1 && !ELIs32(tc, EL1) &&
889  return std::make_shared<SupervisorTrap>(machInst, imm, ec);
890  if (currEL(tc) <= EL2 && EL2Enabled(tc) && !ELIs32(tc, EL2) &&
892  return std::make_shared<HypervisorTrap>(machInst, imm, ec);
893  return NoFault;
894 }
895 
896 bool
898  ThreadContext *tc)
899 {
900  switch (miscReg) {
902  return currEL(tc) == EL0 &&
904  default:
905  break;
906  }
907  return false;
908 }
909 
910 bool
913 {
914  if (currEL(tc) <= EL2 && EL2Enabled(tc) && ELIs32(tc, EL2)) {
915  switch (miscReg) {
917  if (currEL(tc) == EL0 &&
918  isGenericTimerCommonEL0HypTrap(miscReg, tc, ec))
919  return true;
920  switch (miscReg) {
921  case MISCREG_CNTPCT:
923  return currEL(tc) <= EL1 &&
924  isGenericTimerPhysHypTrap(miscReg, tc, ec);
925  default:
926  break;
927  }
928  break;
929  default:
930  break;
931  }
932  }
933  return false;
934 }
935 
936 bool
939 {
940  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
941  bool trap_cond = condGenericTimerSystemAccessTrapEL1(miscReg, tc);
942  if (ELIs32(tc, EL1) && trap_cond && hcr.tge) {
943  // As per the architecture, this hyp trap should have uncategorized
944  // exception class
945  if (ec)
946  *ec = EC_UNKNOWN;
947  return true;
948  }
949  return false;
950 }
951 
952 bool
955 {
956  return condGenericTimerPhysHypTrap(miscReg, tc);
957 }
958 
959 bool
961 {
962  const CNTHCTL cnthctl = tc->readMiscReg(MISCREG_CNTHCTL_EL2);
963  switch (miscReg) {
964  case MISCREG_CNTPCT:
965  return !cnthctl.el1pcten;
967  return !cnthctl.el1pcen;
968  default:
969  break;
970  }
971  return false;
972 }
973 
974 bool
976  ThreadContext *tc)
977 {
978  switch (miscReg) {
981  {
982  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
983  bool trap_cond = condGenericTimerSystemAccessTrapEL1(miscReg, tc);
984  return !(EL2Enabled(tc) && hcr.e2h && hcr.tge) && trap_cond &&
985  !(EL2Enabled(tc) && !ELIs32(tc, EL2) && hcr.tge);
986  }
987  default:
988  break;
989  }
990  return false;
991 }
992 
993 bool
995  ThreadContext *tc)
996 {
997  const CNTKCTL cntkctl = tc->readMiscReg(MISCREG_CNTKCTL_EL1);
998  switch (miscReg) {
999  case MISCREG_CNTFRQ:
1000  case MISCREG_CNTFRQ_EL0:
1001  return !cntkctl.el0pcten && !cntkctl.el0vcten;
1002  case MISCREG_CNTPCT:
1003  case MISCREG_CNTPCT_EL0:
1004  return !cntkctl.el0pcten;
1005  case MISCREG_CNTVCT:
1006  case MISCREG_CNTVCT_EL0:
1007  return !cntkctl.el0vcten;
1010  return !cntkctl.el0pten;
1013  return !cntkctl.el0vten;
1014  default:
1015  break;
1016  }
1017  return false;
1018 }
1019 
1020 bool
1022  ThreadContext *tc)
1023 {
1024  switch (miscReg) {
1026  return currEL(tc) <= EL1 &&
1027  isGenericTimerSystemAccessTrapEL2(miscReg, tc);
1028  default:
1029  break;
1030  }
1031  return false;
1032 }
1033 
1034 bool
1036  ThreadContext *tc)
1037 {
1038  switch (miscReg) {
1041  if (currEL(tc) == EL0 &&
1043  return true;
1044  switch (miscReg) {
1045  case MISCREG_CNTPCT:
1046  case MISCREG_CNTPCT_EL0:
1049  return (currEL(tc) == EL0 &&
1051  (currEL(tc) == EL1 &&
1053  case MISCREG_CNTVCT:
1054  case MISCREG_CNTVCT_EL0:
1057  return isGenericTimerVirtSystemAccessTrapEL2(miscReg, tc);
1058  default:
1059  break;
1060  }
1061  break;
1062  default:
1063  break;
1064  }
1065  return false;
1066 }
1067 
1068 bool
1070  ThreadContext *tc)
1071 {
1072  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1073  bool trap_cond_el1 = condGenericTimerSystemAccessTrapEL1(miscReg, tc);
1074  bool trap_cond_el2 = condGenericTimerCommonEL0SystemAccessTrapEL2(miscReg,
1075  tc);
1076  return (!ELIs32(tc, EL1) && !hcr.e2h && trap_cond_el1 && hcr.tge) ||
1077  (ELIs32(tc, EL1) && trap_cond_el1 && hcr.tge) ||
1078  (hcr.e2h && hcr.tge && trap_cond_el2);
1079 }
1080 
1081 bool
1083  ThreadContext *tc)
1084 {
1085  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1086  bool trap_cond_0 = condGenericTimerPhysEL1SystemAccessTrapEL2(miscReg, tc);
1087  bool trap_cond_1 = condGenericTimerCommonEL1SystemAccessTrapEL2(miscReg,
1088  tc);
1089  switch (miscReg) {
1090  case MISCREG_CNTPCT:
1091  case MISCREG_CNTPCT_EL0:
1092  return !hcr.e2h && trap_cond_1;
1095  return (!hcr.e2h && trap_cond_0) ||
1096  (hcr.e2h && !hcr.tge && trap_cond_1);
1097  default:
1098  break;
1099  }
1100 
1101  return false;
1102 }
1103 
1104 bool
1106  ThreadContext *tc)
1107 {
1108  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1109  bool trap_cond_0 = condGenericTimerPhysEL1SystemAccessTrapEL2(miscReg, tc);
1110  bool trap_cond_1 = condGenericTimerCommonEL1SystemAccessTrapEL2(miscReg,
1111  tc);
1112  switch (miscReg) {
1113  case MISCREG_CNTPCT:
1114  case MISCREG_CNTPCT_EL0:
1115  return trap_cond_1;
1118  return (!hcr.e2h && trap_cond_0) ||
1119  (hcr.e2h && trap_cond_1);
1120  default:
1121  break;
1122  }
1123  return false;
1124 }
1125 
1126 bool
1128  ThreadContext *tc)
1129 {
1130  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1131  bool trap_cond = condGenericTimerCommonEL1SystemAccessTrapEL2(miscReg, tc);
1132  return !ELIs32(tc, EL1) && !(hcr.e2h && hcr.tge) && trap_cond;
1133 }
1134 
1135 bool
1137  ThreadContext *tc)
1138 {
1139  const CNTHCTL_E2H cnthctl = tc->readMiscReg(MISCREG_CNTHCTL_EL2);
1140  switch (miscReg) {
1141  case MISCREG_CNTFRQ:
1142  case MISCREG_CNTFRQ_EL0:
1143  return !cnthctl.el0pcten && !cnthctl.el0vcten;
1144  case MISCREG_CNTPCT:
1145  case MISCREG_CNTPCT_EL0:
1146  return !cnthctl.el0pcten;
1147  case MISCREG_CNTVCT:
1148  case MISCREG_CNTVCT_EL0:
1149  return !cnthctl.el0vcten;
1152  return !cnthctl.el0pten;
1155  return !cnthctl.el0vten;
1156  default:
1157  break;
1158  }
1159  return false;
1160 }
1161 
1162 bool
1164  ThreadContext *tc)
1165 {
1166  const AA64MMFR0 mmfr0 = tc->readMiscRegNoEffect(MISCREG_ID_AA64MMFR0_EL1);
1167  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1168  const RegVal cnthctl_val = tc->readMiscReg(MISCREG_CNTHCTL_EL2);
1169  const CNTHCTL cnthctl = cnthctl_val;
1170  const CNTHCTL_E2H cnthctl_e2h = cnthctl_val;
1171  switch (miscReg) {
1172  case MISCREG_CNTPCT:
1173  case MISCREG_CNTPCT_EL0:
1174  return hcr.e2h ? !cnthctl_e2h.el1pcten : !cnthctl.el1pcten;
1175  case MISCREG_CNTVCT:
1176  case MISCREG_CNTVCT_EL0:
1177  if (!mmfr0.ecv)
1178  return false;
1179  else
1180  return hcr.e2h ? cnthctl_e2h.el1tvct : cnthctl.el1tvct;
1183  return hcr.e2h ? !cnthctl_e2h.el1pten : false;
1186  if (!mmfr0.ecv)
1187  return false;
1188  else
1189  return hcr.e2h ? cnthctl_e2h.el1tvt : cnthctl.el1tvt;
1190  default:
1191  break;
1192  }
1193  return false;
1194 }
1195 
1196 bool
1198  ThreadContext *tc)
1199 {
1200  const CNTHCTL cnthctl = tc->readMiscReg(MISCREG_CNTHCTL_EL2);
1201  return !cnthctl.el1pcen;
1202 }
1203 
1204 bool
1206  ThreadContext *tc)
1207 {
1208  switch (miscReg) {
1210  {
1211  const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
1212  return currEL(tc) == EL1 && !scr.ns && !scr.st;
1213  }
1214  default:
1215  break;
1216  }
1217  return false;
1218 }
1219 
1220 bool
1221 decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int &regIdx,
1222  CPSR cpsr, SCR scr, NSACR nsacr, bool checkSecurity)
1223 {
1225  bool ok = true;
1226 
1227  // R mostly indicates if its a int register or a misc reg, we override
1228  // below if the few corner cases
1229  isIntReg = !r;
1230  // Loosely based on ARM ARM issue C section B9.3.10
1231  if (r) {
1232  switch (sysM)
1233  {
1234  case 0xE:
1235  regIdx = MISCREG_SPSR_FIQ;
1236  mode = MODE_FIQ;
1237  break;
1238  case 0x10:
1239  regIdx = MISCREG_SPSR_IRQ;
1240  mode = MODE_IRQ;
1241  break;
1242  case 0x12:
1243  regIdx = MISCREG_SPSR_SVC;
1244  mode = MODE_SVC;
1245  break;
1246  case 0x14:
1247  regIdx = MISCREG_SPSR_ABT;
1248  mode = MODE_ABORT;
1249  break;
1250  case 0x16:
1251  regIdx = MISCREG_SPSR_UND;
1252  mode = MODE_UNDEFINED;
1253  break;
1254  case 0x1C:
1255  regIdx = MISCREG_SPSR_MON;
1256  mode = MODE_MON;
1257  break;
1258  case 0x1E:
1259  regIdx = MISCREG_SPSR_HYP;
1260  mode = MODE_HYP;
1261  break;
1262  default:
1263  ok = false;
1264  break;
1265  }
1266  } else {
1267  int sysM4To3 = bits(sysM, 4, 3);
1268 
1269  if (sysM4To3 == 0) {
1270  mode = MODE_USER;
1271  regIdx = intRegInMode(mode, bits(sysM, 2, 0) + 8);
1272  } else if (sysM4To3 == 1) {
1273  mode = MODE_FIQ;
1274  regIdx = intRegInMode(mode, bits(sysM, 2, 0) + 8);
1275  } else if (sysM4To3 == 3) {
1276  if (bits(sysM, 1) == 0) {
1277  mode = MODE_MON;
1278  regIdx = intRegInMode(mode, 14 - bits(sysM, 0));
1279  } else {
1280  mode = MODE_HYP;
1281  if (bits(sysM, 0) == 1) {
1282  regIdx = intRegInMode(mode, 13); // R13 in HYP
1283  } else {
1284  isIntReg = false;
1285  regIdx = MISCREG_ELR_HYP;
1286  }
1287  }
1288  } else { // Other Banked registers
1289  int sysM2 = bits(sysM, 2);
1290  int sysM1 = bits(sysM, 1);
1291 
1292  mode = (OperatingMode) ( ((sysM2 || sysM1) << 0) |
1293  (1 << 1) |
1294  ((sysM2 && !sysM1) << 2) |
1295  ((sysM2 && sysM1) << 3) |
1296  (1 << 4) );
1297  regIdx = intRegInMode(mode, 14 - bits(sysM, 0));
1298  // Don't flatten the register here. This is going to go through
1299  // setIntReg() which will do the flattening
1300  ok &= mode != cpsr.mode;
1301  }
1302  }
1303 
1304  // Check that the requested register is accessable from the current mode
1305  if (ok && checkSecurity && mode != cpsr.mode) {
1306  switch (cpsr.mode)
1307  {
1308  case MODE_USER:
1309  ok = false;
1310  break;
1311  case MODE_FIQ:
1312  ok &= mode != MODE_HYP;
1313  ok &= (mode != MODE_MON) || !scr.ns;
1314  break;
1315  case MODE_HYP:
1316  ok &= mode != MODE_MON;
1317  ok &= (mode != MODE_FIQ) || !nsacr.rfr;
1318  break;
1319  case MODE_IRQ:
1320  case MODE_SVC:
1321  case MODE_ABORT:
1322  case MODE_UNDEFINED:
1323  case MODE_SYSTEM:
1324  ok &= mode != MODE_HYP;
1325  ok &= (mode != MODE_MON) || !scr.ns;
1326  ok &= (mode != MODE_FIQ) || !nsacr.rfr;
1327  break;
1328  // can access everything, no further checks required
1329  case MODE_MON:
1330  break;
1331  default:
1332  panic("unknown Mode 0x%x\n", cpsr.mode);
1333  break;
1334  }
1335  }
1336  return (ok);
1337 }
1338 
1339 bool
1341 {
1342  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1343  // NV Extension not implemented yet
1344  bool have_nv_ext = false;
1345  bool unpriv_el1 = currEL(tc) == EL1 &&
1347  have_nv_ext && hcr.nv == 1 && hcr.nv1 == 1);
1348  bool unpriv_el2 = ArmSystem::haveEL(tc, EL2) && HaveVirtHostExt(tc) &&
1349  currEL(tc) == EL2 && hcr.e2h == 1 && hcr.tge == 1;
1350 
1351  // User Access override, or UAO not implemented yet.
1352  bool user_access_override = false;
1353  return (unpriv_el1 || unpriv_el2) && !user_access_override;
1354 }
1355 
1356 bool
1358 {
1359  ExceptionLevel regime = s1TranslationRegime(tc, currEL(tc));
1360 
1361  switch (currEL(tc)) {
1362  case EL3:
1363  return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL3)).sa;
1364  case EL2:
1365  return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL2)).sa;
1366  case EL1:
1367  return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).sa;
1368  case EL0:
1369  {
1370  SCTLR sc = (regime == EL2) ? tc->readMiscReg(MISCREG_SCTLR_EL2):
1372  return sc.sa0;
1373  }
1374  default:
1375  panic("Invalid exception level");
1376  break;
1377  }
1378 }
1379 
1380 int
1381 decodePhysAddrRange64(uint8_t pa_enc)
1382 {
1383  switch (pa_enc) {
1384  case 0x0:
1385  return 32;
1386  case 0x1:
1387  return 36;
1388  case 0x2:
1389  return 40;
1390  case 0x3:
1391  return 42;
1392  case 0x4:
1393  return 44;
1394  case 0x5:
1395  case 0x6:
1396  case 0x7:
1397  return 48;
1398  default:
1399  panic("Invalid phys. address range encoding");
1400  }
1401 }
1402 
1403 uint8_t
1405 {
1406  switch (pa_size) {
1407  case 32:
1408  return 0x0;
1409  case 36:
1410  return 0x1;
1411  case 40:
1412  return 0x2;
1413  case 42:
1414  return 0x3;
1415  case 44:
1416  return 0x4;
1417  case 48:
1418  return 0x5;
1419  default:
1420  panic("Invalid phys. address range");
1421  }
1422 }
1423 
1424 } // namespace ArmISA
ArmISA::sendEvent
void sendEvent(ThreadContext *tc)
Send an event (SEV) to a specific PE if there isn't already a pending event.
Definition: utility.cc:165
ArmISA::MISCREG_TLBIALLIS
@ MISCREG_TLBIALLIS
Definition: miscregs.hh:315
ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
ArmISA::isGenericTimerSystemAccessTrapEL3
bool isGenericTimerSystemAccessTrapEL3(const MiscRegIndex miscReg, ThreadContext *tc)
Definition: utility.cc:1205
ArmISA::MISCREG_DBGOSLAR
@ MISCREG_DBGOSLAR
Definition: miscregs.hh:183
ThreadContext::readIntRegFlat
virtual RegVal readIntRegFlat(RegIndex idx) const =0
Flat register interfaces.
ArmISA::ELIsInHost
bool ELIsInHost(ThreadContext *tc, ExceptionLevel el)
Returns true if the current exception level el is executing a Host OS or an application of a Host OS ...
Definition: utility.cc:392
ArmISA::copyRegs
void copyRegs(ThreadContext *src, ThreadContext *dest)
Definition: utility.cc:136
ArmISA::EL2Enabled
bool EL2Enabled(ThreadContext *tc)
Definition: utility.cc:369
ArmISA::fp
Bitfield< 19, 16 > fp
Definition: miscregs_types.hh:173
ArmISA::encodePhysAddrRange64
uint8_t encodePhysAddrRange64(int pa_size)
Returns the encoding corresponding to the specified n.
Definition: utility.cc:1404
ArmISA::debugTargetFrom
ExceptionLevel debugTargetFrom(ThreadContext *tc, bool secure)
Definition: utility.cc:193
ArmISA::MODE_HYP
@ MODE_HYP
Definition: types.hh:642
ArmISA::MISCREG_TLBIMVAAIS
@ MISCREG_TLBIMVAAIS
Definition: miscregs.hh:318
ThreadContext::readVecElemFlat
virtual const VecElem & readVecElemFlat(RegIndex idx, const ElemIndex &elemIdx) const =0
ArmISA::getAffinity
RegVal getAffinity(ArmSystem *arm_sys, ThreadContext *tc)
Retrieves MPIDR_EL1.
Definition: utility.cc:312
ArmISA::computeAddrTop
int computeAddrTop(ThreadContext *tc, bool selbit, bool isInstr, TCR tcr, ExceptionLevel el)
Definition: utility.cc:513
ArmISA::MISCREG_ID_AA64ISAR1_EL1
@ MISCREG_ID_AA64ISAR1_EL1
Definition: miscregs.hh:560
replaceBits
void replaceBits(T &val, int first, int last, B bit_val)
A convenience function to replace bits first to last of val with bit_val in place.
Definition: bitfield.hh:179
ArmISA::EL2
@ EL2
Definition: types.hh:624
ArmISA::MISCREG_CNTV_CTL
@ MISCREG_CNTV_CTL
Definition: miscregs.hh:419
ArmISA::MODE_UNDEFINED
@ MODE_UNDEFINED
Definition: types.hh:643
ArmISA::MISCREG_HCPTR
@ MISCREG_HCPTR
Definition: miscregs.hh:245
ArmISA::MISCREG_TTBR0
@ MISCREG_TTBR0
Definition: miscregs.hh:248
ArmISA::HaveVirtHostExt
bool HaveVirtHostExt(ThreadContext *tc)
Definition: utility.cc:326
ThreadContext::readVecRegFlat
virtual const VecRegContainer & readVecRegFlat(RegIndex idx) const =0
ArmISA::MISCREG_SPSR_HYP
@ MISCREG_SPSR_HYP
Definition: miscregs.hh:64
ArmISA::MISCREG_CNTPCT
@ MISCREG_CNTPCT
Definition: miscregs.hh:408
ArmISA::isGenericTimerVirtSystemAccessTrapEL2
bool isGenericTimerVirtSystemAccessTrapEL2(const MiscRegIndex miscReg, ThreadContext *tc)
Definition: utility.cc:1127
RenameMode::mode
static Enums::VecRegRenameMode mode(const TheISA::PCState &)
Definition: traits.hh:58
ArmISA::MISCREG_SPSR_UND
@ MISCREG_SPSR_UND
Definition: miscregs.hh:65
ArmISA::getArgument
uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
Definition: utility.cc:57
ArmISA::MISCREG_AIDR
@ MISCREG_AIDR
Definition: miscregs.hh:223
ArmSystem::highestELIs64
bool highestELIs64() const
Returns true if the register width of the highest implemented exception level is 64 bits (ARMv8)
Definition: system.hh:204
ArmISA::isGenericTimerPhysEL1SystemAccessTrapEL2
bool isGenericTimerPhysEL1SystemAccessTrapEL2(const MiscRegIndex miscReg, ThreadContext *tc)
Definition: utility.cc:1105
ArmISA::MISCREG_DCCISW
@ MISCREG_DCCISW
Definition: miscregs.hh:312
warn_once
#define warn_once(...)
Definition: logging.hh:243
ArmISA::i
Bitfield< 7 > i
Definition: miscregs_types.hh:63
ArmISA::MISCREG_VMPIDR_EL2
@ MISCREG_VMPIDR_EL2
Definition: miscregs.hh:570
ArmISA::MISCREG_CNTFRQ_EL0
@ MISCREG_CNTFRQ_EL0
Definition: miscregs.hh:745
ArmISA::MISCREG_TEECR
@ MISCREG_TEECR
Definition: miscregs.hh:194
ArmISA::EL0
@ EL0
Definition: types.hh:622
ArmISA::MISCREG_TLBIMVAL
@ MISCREG_TLBIMVAL
Definition: miscregs.hh:331
ArmISA::MISCREG_DCISW
@ MISCREG_DCISW
Definition: miscregs.hh:297
ArmISA::isGenericTimerCommonEL0SystemAccessTrapEL2
bool isGenericTimerCommonEL0SystemAccessTrapEL2(const MiscRegIndex miscReg, ThreadContext *tc)
Definition: utility.cc:1069
ArmISA::MISCREG_ITLBIMVA
@ MISCREG_ITLBIMVA
Definition: miscregs.hh:322
ArmISA::MISCREG_ID_MMFR0
@ MISCREG_ID_MMFR0
Definition: miscregs.hh:211
ArmISA::MISCREG_JMCR
@ MISCREG_JMCR
Definition: miscregs.hh:198
ArmISA::MISCREG_CNTP_TVAL_EL0
@ MISCREG_CNTP_TVAL_EL0
Definition: miscregs.hh:750
ArmISA::MISCREG_ICIALLUIS
@ MISCREG_ICIALLUIS
Definition: miscregs.hh:286
ArmISA::badMode32
bool badMode32(ThreadContext *tc, OperatingMode mode)
badMode is checking if the execution mode provided as an argument is valid and implemented for AArch3...
Definition: utility.cc:501
ArmISA::MISCREG_JIDR
@ MISCREG_JIDR
Definition: miscregs.hh:195
ArmISA::OperatingMode
OperatingMode
Definition: types.hh:628
ArmISA::currEL
static ExceptionLevel currEL(const ThreadContext *tc)
Definition: utility.hh:143
ArmISA::MISCREG_ICIALLU
@ MISCREG_ICIALLU
Definition: miscregs.hh:291
ArmISA::MISCREG_TLBIMVA
@ MISCREG_TLBIMVA
Definition: miscregs.hh:328
ArmISA::MISCREG_ID_MMFR2
@ MISCREG_ID_MMFR2
Definition: miscregs.hh:213
ArmISA::MISCREG_CNTPS_TVAL_EL1
@ MISCREG_CNTPS_TVAL_EL1
Definition: miscregs.hh:764
ArmISA::MISCREG_TLBIMVAIS
@ MISCREG_TLBIMVAIS
Definition: miscregs.hh:316
ArmISA::MISCREG_CLIDR
@ MISCREG_CLIDR
Definition: miscregs.hh:222
ArmISA::MISCREG_REVIDR
@ MISCREG_REVIDR
Definition: miscregs.hh:206
ArmISA::condGenericTimerCommonEL1SystemAccessTrapEL2
bool condGenericTimerCommonEL1SystemAccessTrapEL2(const MiscRegIndex miscReg, ThreadContext *tc)
Definition: utility.cc:1163
ArmISA::MISCREG_CNTV_TVAL
@ MISCREG_CNTV_TVAL
Definition: miscregs.hh:421
ArmISA::MISCREG_CPACR
@ MISCREG_CPACR
Definition: miscregs.hh:235
ArmISA::IntRegIndex
IntRegIndex
Definition: intregs.hh:51
ArmISA::MODE_SYSTEM
@ MODE_SYSTEM
Definition: types.hh:644
ArmISA::MISCREG_ICC_SGI1R
@ MISCREG_ICC_SGI1R
Definition: miscregs.hh:993
ArmISA::isAArch64AArch32SystemAccessTrapEL1
bool isAArch64AArch32SystemAccessTrapEL1(const MiscRegIndex miscReg, ThreadContext *tc)
Definition: utility.cc:897
ArmISA::isGenericTimerHypTrap
bool isGenericTimerHypTrap(const MiscRegIndex miscReg, ThreadContext *tc, ExceptionClass *ec)
Definition: utility.cc:911
ArmISA::MISCREG_CNTV_TVAL_EL0
@ MISCREG_CNTV_TVAL_EL0
Definition: miscregs.hh:753
ArmISA::inSecureState
static bool inSecureState(SCR scr, CPSR cpsr)
Definition: utility.hh:246
ArmISA::EC_TRAPPED_CP15_MCRR_MRRC
@ EC_TRAPPED_CP15_MCRR_MRRC
Definition: types.hh:653
ArmISA::getAff1
static RegVal getAff1(ArmSystem *arm_sys, ThreadContext *tc)
Definition: utility.cc:300
ArmISA::decodePhysAddrRange64
int decodePhysAddrRange64(uint8_t pa_enc)
Returns the n.
Definition: utility.cc:1381
ArmISA::INT_SEV
@ INT_SEV
Definition: interrupts.hh:63
ArmISA::tbi
Bitfield< 20 > tbi
Definition: miscregs_types.hh:509
BaseCPU::postInterrupt
void postInterrupt(ThreadID tid, int int_num, int index)
Definition: base.cc:189
tlb.hh
ArmISA::MISCREG_DCCIMVAC
@ MISCREG_DCCIMVAC
Definition: miscregs.hh:311
ArmISA::MISCREG_DCCSW
@ MISCREG_DCCSW
Definition: miscregs.hh:307
ArmISA::EL3
@ EL3
Definition: types.hh:625
ArmISA::MISCREG_ELR_HYP
@ MISCREG_ELR_HYP
Definition: miscregs.hh:66
FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:132
ArmISA::MISCREG_TLBIMVAA
@ MISCREG_TLBIMVAA
Definition: miscregs.hh:330
ArmISA::MISCREG_ID_ISAR3
@ MISCREG_ID_ISAR3
Definition: miscregs.hh:218
ArmISA::MISCREG_TCR_EL2
@ MISCREG_TCR_EL2
Definition: miscregs.hh:596
ArmISA::condGenericTimerPhysHypTrap
bool condGenericTimerPhysHypTrap(const MiscRegIndex miscReg, ThreadContext *tc)
Definition: utility.cc:960
ArmISA::mcrrMrrc15TrapToHyp
bool mcrrMrrc15TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc, uint32_t iss, ExceptionClass *ec)
Definition: utility.cc:822
ArmISA::MISCREG_ID_MMFR1
@ MISCREG_ID_MMFR1
Definition: miscregs.hh:212
ArmISA::ISA
Definition: isa.hh:65
ArmISA::HaveSecureEL2Ext
bool HaveSecureEL2Ext(ThreadContext *tc)
Definition: utility.cc:348
ArmISA::MISCREG_ICC_SGI0R
@ MISCREG_ICC_SGI0R
Definition: miscregs.hh:992
ArmISA::mcrMrc15TrapToHyp
bool mcrMrc15TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc, uint32_t iss, ExceptionClass *ec)
Definition: utility.cc:607
ArmISA::MISCREG_CCSIDR
@ MISCREG_CCSIDR
Definition: miscregs.hh:221
ArmISA::getMPIDR
RegVal getMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
This helper function is returning the value of MPIDR_EL1.
Definition: utility.cc:264
system.hh
ArmISA::MISCREG_CNTV_CTL_EL0
@ MISCREG_CNTV_CTL_EL0
Definition: miscregs.hh:751
ArmISA::condGenericTimerPhysEL1SystemAccessTrapEL2
bool condGenericTimerPhysEL1SystemAccessTrapEL2(const MiscRegIndex miscReg, ThreadContext *tc)
Definition: utility.cc:1197
ArmISA::AArch64AArch32SystemAccessTrap
Fault AArch64AArch32SystemAccessTrap(const MiscRegIndex miscReg, ExtMachInst machInst, ThreadContext *tc, uint32_t imm, ExceptionClass ec)
Definition: utility.cc:883
ArmISA::MISCREG_ICIMVAU
@ MISCREG_ICIMVAU
Definition: miscregs.hh:292
ArmISA::unflattenMiscReg
int unflattenMiscReg(int reg)
Definition: miscregs.cc:1363
ArmISA::decodeMrsMsrBankedReg
bool decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int &regIdx, CPSR cpsr, SCR scr, NSACR nsacr, bool checkSecurity)
Definition: utility.cc:1221
ArmISA::MISCREG_SEV_MAILBOX
@ MISCREG_SEV_MAILBOX
Definition: miscregs.hh:88
ArmISA
Definition: ccregs.hh:41
ArmISA::MISCREG_TCR_EL3
@ MISCREG_TCR_EL3
Definition: miscregs.hh:602
ThreadContext::setFloatRegFlat
virtual void setFloatRegFlat(RegIndex idx, RegVal val)=0
ArmSystem::haveVirtualization
bool haveVirtualization() const
Returns true if this system implements the virtualization Extensions.
Definition: system.hh:170
ArmISA::MISCREG_TLBIMVAALIS
@ MISCREG_TLBIMVAALIS
Definition: miscregs.hh:320
ArmISA::MISCREG_ICC_ASGI1R
@ MISCREG_ICC_ASGI1R
Definition: miscregs.hh:967
ArmISA::MISCREG_CNTP_TVAL_S
@ MISCREG_CNTP_TVAL_S
Definition: miscregs.hh:418
ArmISA::MISCREG_CNTVCT
@ MISCREG_CNTVCT
Definition: miscregs.hh:409
ArmISA::MISCREG_CNTFRQ
@ MISCREG_CNTFRQ
Definition: miscregs.hh:407
ArmISA::ec
ec
Definition: miscregs_types.hh:663
ArmISA::MISCREG_AIFSR
@ MISCREG_AIFSR
Definition: miscregs.hh:271
ArmISA::MISCREG_ID_AA64MMFR0_EL1
@ MISCREG_ID_AA64MMFR0_EL1
Definition: miscregs.hh:561
ArmISA::MISCREG_CNTKCTL_EL1
@ MISCREG_CNTKCTL_EL1
Definition: miscregs.hh:760
ThreadContext::threadId
virtual int threadId() const =0
ArmISA::mcrrMrrc15Trap
Fault mcrrMrrc15Trap(const MiscRegIndex miscReg, ExtMachInst machInst, ThreadContext *tc, uint32_t imm)
Definition: utility.cc:812
ArmISA::rt
Bitfield< 15, 12 > rt
Definition: types.hh:124
ArmISA::MISCREG_TLBIALL
@ MISCREG_TLBIALL
Definition: miscregs.hh:327
ArmISA::ELIs64
bool ELIs64(ThreadContext *tc, ExceptionLevel el)
Definition: utility.cc:377
ThreadContext::getIsaPtr
virtual BaseISA * getIsaPtr()=0
ArmISA::mcrMrc15Trap
Fault mcrMrc15Trap(const MiscRegIndex miscReg, ExtMachInst machInst, ThreadContext *tc, uint32_t imm)
Definition: utility.cc:597
ArmISA::IsSecureEL2Enabled
bool IsSecureEL2Enabled(ThreadContext *tc)
Definition: utility.cc:355
ArmISA::MISCREG_ADFSR
@ MISCREG_ADFSR
Definition: miscregs.hh:268
ArmISA::ELStateUsingAArch32
bool ELStateUsingAArch32(ThreadContext *tc, ExceptionLevel el, bool secure)
Definition: utility.cc:473
ArmISA::MISCREG_DBGDRAR
@ MISCREG_DBGDRAR
Definition: miscregs.hh:166
ArmISA::truncPage
Addr truncPage(Addr addr)
Definition: utility.cc:585
ArmISA::MISCREG_ID_MMFR3
@ MISCREG_ID_MMFR3
Definition: miscregs.hh:214
ArmISA::ELIs32
bool ELIs32(ThreadContext *tc, ExceptionLevel el)
Definition: utility.cc:383
ArmISA::MISCREG_CONTEXTIDR
@ MISCREG_CONTEXTIDR
Definition: miscregs.hh:393
ArmISA::MISCREG_ID_PFR0
@ MISCREG_ID_PFR0
Definition: miscregs.hh:207
ArmISA::MISCREG_CTR
@ MISCREG_CTR
Definition: miscregs.hh:202
ArmISA::MISCREG_ID_AA64PFR0_EL1
@ MISCREG_ID_AA64PFR0_EL1
Definition: miscregs.hh:553
interrupts.hh
ArmISA::MISCREG_DTLBIMVA
@ MISCREG_DTLBIMVA
Definition: miscregs.hh:325
ArmISA::isBigEndian64
bool isBigEndian64(const ThreadContext *tc)
Definition: utility.cc:483
ArmSystem::haveSecurity
bool haveSecurity() const
Returns true if this system implements the Security Extensions.
Definition: system.hh:161
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:88
ArmSystem::haveLPAE
bool haveLPAE() const
Returns true if this system implements the Large Physical Address Extension.
Definition: system.hh:165
System::multiThread
const bool multiThread
Definition: system.hh:311
ArmISA::MISCREG_HCR
@ MISCREG_HCR
Definition: miscregs.hh:242
ThreadContext::setIntRegFlat
virtual void setIntRegFlat(RegIndex idx, RegVal val)=0
ArmISA::isAArch64AArch32SystemAccessTrapEL2
bool isAArch64AArch32SystemAccessTrapEL2(const MiscRegIndex miscReg, ThreadContext *tc)
Definition: utility.cc:1021
ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:621
ArmISA::imm
Bitfield< 7, 0 > imm
Definition: types.hh:141
ArmISA::MISCREG_TLBTR
@ MISCREG_TLBTR
Definition: miscregs.hh:204
Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:240
ArmISA::MISCREG_ID_AA64MMFR1_EL1
@ MISCREG_ID_AA64MMFR1_EL1
Definition: miscregs.hh:562
MipsISA::r
r
Definition: pra_constants.hh:95
cpu.hh
port_proxy.hh
ArmISA::ELStateUsingAArch32K
std::pair< bool, bool > ELStateUsingAArch32K(ThreadContext *tc, ExceptionLevel el, bool secure)
Definition: utility.cc:423
ArmISA::MISCREG_ID_ISAR1
@ MISCREG_ID_ISAR1
Definition: miscregs.hh:216
ArmISA::NumVecElemPerVecReg
constexpr unsigned NumVecElemPerVecReg
Definition: registers.hh:66
ArmISA::MISCREG_SPSR_IRQ
@ MISCREG_SPSR_IRQ
Definition: miscregs.hh:60
ArmISA::MISCREG_TCR_EL1
@ MISCREG_TCR_EL1
Definition: miscregs.hh:593
ArmISA::mode
Bitfield< 4, 0 > mode
Definition: miscregs_types.hh:70
ArmISA::MISCREG_ID_ISAR4
@ MISCREG_ID_ISAR4
Definition: miscregs.hh:219
ArmISA::NumArgumentRegs
const int NumArgumentRegs
Definition: registers.hh:107
ArmISA::el
Bitfield< 3, 2 > el
Definition: miscregs_types.hh:69
ArmISA::MISCREG_SPSR_ABT
@ MISCREG_SPSR_ABT
Definition: miscregs.hh:63
ArmISA::MISCREG_TTBCR
@ MISCREG_TTBCR
Definition: miscregs.hh:254
ArmISA::MISCREG_DFSR
@ MISCREG_DFSR
Definition: miscregs.hh:262
ArmISA::SPAlignmentCheckEnabled
bool SPAlignmentCheckEnabled(ThreadContext *tc)
Definition: utility.cc:1357
ThreadContext::cpuId
virtual int cpuId() const =0
ArmISA::isGenericTimerPhysHypTrap
bool isGenericTimerPhysHypTrap(const MiscRegIndex miscReg, ThreadContext *tc, ExceptionClass *ec)
Definition: utility.cc:953
ArmISA::getAff2
static RegVal getAff2(ArmSystem *arm_sys, ThreadContext *tc)
Definition: utility.cc:294
M5_FALLTHROUGH
#define M5_FALLTHROUGH
Definition: compiler.hh:84
ArmISA::opModeToEL
static ExceptionLevel opModeToEL(OperatingMode mode)
Definition: types.hh:736
ArmISA::MISCREG_TLBIMVAAL
@ MISCREG_TLBIMVAAL
Definition: miscregs.hh:332
ArmISA::MISCREG_ACTLR
@ MISCREG_ACTLR
Definition: miscregs.hh:232
ArmISA::opc2
Bitfield< 7, 5 > opc2
Definition: types.hh:115
ArmISA::MODE_SVC
@ MODE_SVC
Definition: types.hh:639
ArmISA::MISCREG_CNTPS_CTL_EL1
@ MISCREG_CNTPS_CTL_EL1
Definition: miscregs.hh:762
ArmISA::MISCREG_DACR
@ MISCREG_DACR
Definition: miscregs.hh:259
ArmISA::s1TranslationRegime
ExceptionLevel s1TranslationRegime(ThreadContext *tc, ExceptionLevel el)
Definition: utility.cc:333
ArmISA::NumFloatRegs
const int NumFloatRegs
Definition: registers.hh:83
ArmISA::MISCREG_DBGOSDLR
@ MISCREG_DBGOSDLR
Definition: miscregs.hh:185
ArmISA::longDescFormatInUse
bool longDescFormatInUse(ThreadContext *tc)
Definition: utility.cc:229
ThreadContext::readFloatRegFlat
virtual RegVal readFloatRegFlat(RegIndex idx) const =0
std::pair
STL pair class.
Definition: stl.hh:58
ArmISA::MODE_FIQ
@ MODE_FIQ
Definition: types.hh:637
faults.hh
ArmISA::MISCREG_ITLBIALL
@ MISCREG_ITLBIALL
Definition: miscregs.hh:321
ArmISA::MISCREG_TLBIASIDIS
@ MISCREG_TLBIASIDIS
Definition: miscregs.hh:317
ArmISA::MISCREG_HCR_EL2
@ MISCREG_HCR_EL2
Definition: miscregs.hh:578
ArmISA::ELUsingAArch32K
std::pair< bool, bool > ELUsingAArch32K(ThreadContext *tc, ExceptionLevel el)
This function checks whether selected EL provided as an argument is using the AArch32 ISA.
Definition: utility.cc:402
NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:245
ArmISA::sp
Bitfield< 0 > sp
Definition: miscregs_types.hh:71
ArmISA::MISCREG_IFSR
@ MISCREG_IFSR
Definition: miscregs.hh:265
ArmISA::MISCREG_DTLBIASID
@ MISCREG_DTLBIASID
Definition: miscregs.hh:326
ArmISA::EL1
@ EL1
Definition: types.hh:623
ArmISA::NumIntRegs
const int NumIntRegs
Definition: registers.hh:82
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
ArmISA::purifyTaggedAddr
Addr purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el, TCR tcr, bool isInstr)
Removes the tag from tagged addresses if that mode is enabled.
Definition: utility.cc:558
ArmISA::MISCREG_CNTPCT_EL0
@ MISCREG_CNTPCT_EL0
Definition: miscregs.hh:746
ArmISA::EC_TRAPPED_CP15_MCR_MRC
@ EC_TRAPPED_CP15_MCR_MRC
Definition: types.hh:652
ArmISA::MISCREG_IFAR
@ MISCREG_IFAR
Definition: miscregs.hh:280
ArmISA::readMPIDR
RegVal readMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
This helper function is either returing the value of MPIDR_EL1 (by calling getMPIDR),...
Definition: utility.cc:236
ArmISA::MISCREG_TLBIASID
@ MISCREG_TLBIASID
Definition: miscregs.hh:329
ArmISA::MISCREG_TCMTR
@ MISCREG_TCMTR
Definition: miscregs.hh:203
ArmISA::HavePACExt
bool HavePACExt(ThreadContext *tc)
Definition: utility.cc:318
utility.hh
ThreadContext::getITBPtr
virtual BaseTLB * getITBPtr()=0
full_system.hh
ArmISA::MISCREG_NMRR
@ MISCREG_NMRR
Definition: miscregs.hh:369
ThreadContext::pcState
virtual TheISA::PCState pcState() const =0
ArmISA::MISCREG_TTBR1
@ MISCREG_TTBR1
Definition: miscregs.hh:251
ArmISA::isGenericTimerSystemAccessTrapEL1
bool isGenericTimerSystemAccessTrapEL1(const MiscRegIndex miscReg, ThreadContext *tc)
Definition: utility.cc:975
ArmISA::MISCREG_CNTHCTL_EL2
@ MISCREG_CNTHCTL_EL2
Definition: miscregs.hh:765
ArmISA::TLB
Definition: tlb.hh:100
ArmISA::copyVecRegs
static void copyVecRegs(ThreadContext *src, ThreadContext *dest)
Definition: utility.cc:118
ThreadContext::readCCReg
virtual RegVal readCCReg(RegIndex reg_idx) const =0
ThreadContext::getVirtProxy
virtual PortProxy & getVirtProxy()=0
ArmISA::MISCREG_PRRR
@ MISCREG_PRRR
Definition: miscregs.hh:363
ArmSystem
Definition: system.hh:59
ArmISA::MISCREG_SCR_EL3
@ MISCREG_SCR_EL3
Definition: miscregs.hh:585
ArmISA::unknownMode32
static bool unknownMode32(OperatingMode mode)
Definition: types.hh:791
ArmISA::MISCREG_ID_DFR0
@ MISCREG_ID_DFR0
Definition: miscregs.hh:209
ArmISA::MISCREG_SPSR_MON
@ MISCREG_SPSR_MON
Definition: miscregs.hh:62
ArmISA::MODE_IRQ
@ MODE_IRQ
Definition: types.hh:638
ArmISA::MODE_ABORT
@ MODE_ABORT
Definition: types.hh:641
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:197
ArmISA::MISCREG_MAIR1
@ MISCREG_MAIR1
Definition: miscregs.hh:372
ArmISA::PageBytes
const Addr PageBytes
Definition: isa_traits.hh:52
ArmISA::MISCREG_DBGOSLSR
@ MISCREG_DBGOSLSR
Definition: miscregs.hh:184
ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition: miscregs.hh:57
inform
#define inform(...)
Definition: logging.hh:240
ArmISA::NumCCRegs
const int NumCCRegs
Definition: registers.hh:84
PortProxy
This object is a proxy for a port or other object which implements the functional response protocol,...
Definition: port_proxy.hh:80
ThreadContext::setCCReg
virtual void setCCReg(RegIndex reg_idx, RegVal val)=0
ArmISA::mcrMrcIssExtract
static void mcrMrcIssExtract(uint32_t iss, bool &isRead, uint32_t &crm, IntRegIndex &rt, uint32_t &crn, uint32_t &opc1, uint32_t &opc2)
Definition: utility.hh:290
PortProxy::read
T read(Addr address) const
Read sizeof(T) bytes from address and return as object T.
Definition: port_proxy.hh:282
ArmISA::isSecureBelowEL3
bool isSecureBelowEL3(ThreadContext *tc)
Definition: utility.cc:186
base.hh
ArmISA::StackPointerReg
const int StackPointerReg
Definition: registers.hh:114
ArmISA::MISCREG_MDCR_EL2
@ MISCREG_MDCR_EL2
Definition: miscregs.hh:579
ArmISA::MISCREG_ID_AFR0
@ MISCREG_ID_AFR0
Definition: miscregs.hh:210
ArmISA::MISCREG_TLBIMVALIS
@ MISCREG_TLBIMVALIS
Definition: miscregs.hh:319
ArmSystem::highestEL
ArmISA::ExceptionLevel highestEL() const
Returns the highest implemented exception level.
Definition: system.hh:208
ArmISA::isUnpriviledgeAccess
bool isUnpriviledgeAccess(ThreadContext *tc)
Definition: utility.cc:1340
ArmISA::MISCREG_DFAR
@ MISCREG_DFAR
Definition: miscregs.hh:277
ArmISA::MISCREG_DBGPRCR
@ MISCREG_DBGPRCR
Definition: miscregs.hh:186
ArmISA::MISCREG_ID_ISAR2
@ MISCREG_ID_ISAR2
Definition: miscregs.hh:217
ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
ArmISA::MISCREG_SPSR_SVC
@ MISCREG_SPSR_SVC
Definition: miscregs.hh:61
ArmISA::MiscRegIndex
MiscRegIndex
Definition: miscregs.hh:56
ThreadContext::setMiscReg
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
addr
ip6_addr_t addr
Definition: inet.hh:423
ArmISA::MISCREG_HSTR
@ MISCREG_HSTR
Definition: miscregs.hh:246
ArmISA::isGenericTimerCommonEL0HypTrap
bool isGenericTimerCommonEL0HypTrap(const MiscRegIndex miscReg, ThreadContext *tc, ExceptionClass *ec)
Definition: utility.cc:937
ArmISA::ExceptionClass
ExceptionClass
Definition: types.hh:648
ArmSystem::haveEL
static bool haveEL(ThreadContext *tc, ArmISA::ExceptionLevel el)
Return true if the system implements a specific exception level.
Definition: system.cc:135
ArmISA::MISCREG_ID_ISAR0
@ MISCREG_ID_ISAR0
Definition: miscregs.hh:215
ArmISA::unknownMode
static bool unknownMode(OperatingMode mode)
Definition: types.hh:765
ArmISA::EC_UNKNOWN
@ EC_UNKNOWN
Definition: types.hh:650
ArmISA::MISCREG_DTLBIALL
@ MISCREG_DTLBIALL
Definition: miscregs.hh:324
ArmISA::MISCREG_ITLBIASID
@ MISCREG_ITLBIASID
Definition: miscregs.hh:323
isa_traits.hh
ArmISA::MISCREG_ID_PFR1
@ MISCREG_ID_PFR1
Definition: miscregs.hh:208
ArmISA::condGenericTimerCommonEL0SystemAccessTrapEL2
bool condGenericTimerCommonEL0SystemAccessTrapEL2(const MiscRegIndex miscReg, ThreadContext *tc)
Definition: utility.cc:1136
ArmISA::MISCREG_DCIMVAC
@ MISCREG_DCIMVAC
Definition: miscregs.hh:296
ArmSystem::multiProc
bool multiProc
true if this a multiprocessor system
Definition: system.hh:158
ArmISA::intRegInMode
static int intRegInMode(OperatingMode mode, int reg)
Definition: intregs.hh:462
ArmISA::MISCREG_MAIR0
@ MISCREG_MAIR0
Definition: miscregs.hh:366
ArmISA::MODE_MON
@ MODE_MON
Definition: types.hh:640
ArmISA::MISCREG_CNTVCT_EL0
@ MISCREG_CNTVCT_EL0
Definition: miscregs.hh:747
ArmISA::MISCREG_DCCMVAU
@ MISCREG_DCCMVAU
Definition: miscregs.hh:310
ArmISA::MISCREG_DBGDSAR
@ MISCREG_DBGDSAR
Definition: miscregs.hh:187
ArmISA::NumVecRegs
const int NumVecRegs
Definition: registers.hh:97
ArmISA::MISCREG_SCTLR
@ MISCREG_SCTLR
Definition: miscregs.hh:229
ThreadContext::setVecElemFlat
virtual void setVecElemFlat(RegIndex idx, const ElemIndex &elemIdx, const VecElem &val)=0
ArmISA::tbid
Bitfield< 29 > tbid
Definition: miscregs_types.hh:532
ThreadContext::setMiscRegNoEffect
virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val)=0
ArmISA::MISCREG_DCCMVAC
@ MISCREG_DCCMVAC
Definition: miscregs.hh:306
ArmISA::haveAArch32EL
bool haveAArch32EL(ThreadContext *tc, ExceptionLevel el)
Definition: utility.cc:409
ThreadContext::socketId
virtual uint32_t socketId() const =0
ArmISA::MISCREG_CNTP_CTL_EL0
@ MISCREG_CNTP_CTL_EL0
Definition: miscregs.hh:748
ArmISA::getAff0
static RegVal getAff0(ArmSystem *arm_sys, ThreadContext *tc)
Definition: utility.cc:306
ArmISA::MODE_USER
@ MODE_USER
Definition: types.hh:636
ArmISA::inAArch64
bool inAArch64(ThreadContext *tc)
Definition: utility.cc:222
ArmISA::isGenericTimerPhysEL0SystemAccessTrapEL2
bool isGenericTimerPhysEL0SystemAccessTrapEL2(const MiscRegIndex miscReg, ThreadContext *tc)
Definition: utility.cc:1082
ThreadContext::setVecRegFlat
virtual void setVecRegFlat(RegIndex idx, const VecRegContainer &val)=0
ThreadContext::readIntReg
virtual RegVal readIntReg(RegIndex reg_idx) const =0
ArmISA::MISCREG_SCTLR_EL3
@ MISCREG_SCTLR_EL3
Definition: miscregs.hh:583
ArmISA::mcrMrc14TrapToHyp
bool mcrMrc14TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr, HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss)
Definition: utility.cc:762
ArmISA::MISCREG_JOSCR
@ MISCREG_JOSCR
Definition: miscregs.hh:197
ArmISA::condGenericTimerSystemAccessTrapEL1
bool condGenericTimerSystemAccessTrapEL1(const MiscRegIndex miscReg, ThreadContext *tc)
Definition: utility.cc:994
ArmISA::NumMiscRegs
const int NumMiscRegs
Definition: registers.hh:85
ThreadContext::getCpuPtr
virtual BaseCPU * getCpuPtr()=0
ArmISA::MISCREG_SCR
@ MISCREG_SCR
Definition: miscregs.hh:237
ArmISA::MISCREG_HDCR
@ MISCREG_HDCR
Definition: miscregs.hh:244
ArmISA::MISCREG_CNTP_CTL
@ MISCREG_CNTP_CTL
Definition: miscregs.hh:410
ArmISA::MISCREG_CNTVOFF
@ MISCREG_CNTVOFF
Definition: miscregs.hh:427
ArmISA::MISCREG_TEEHBR
@ MISCREG_TEEHBR
Definition: miscregs.hh:196
ArmISA::MISCREG_SCTLR_EL2
@ MISCREG_SCTLR_EL2
Definition: miscregs.hh:576
ArmISA::isGenericTimerSystemAccessTrapEL2
bool isGenericTimerSystemAccessTrapEL2(const MiscRegIndex miscReg, ThreadContext *tc)
Definition: utility.cc:1035
ArmISA::roundPage
Addr roundPage(Addr addr)
Definition: utility.cc:591
ArmISA::badMode
bool badMode(ThreadContext *tc, OperatingMode mode)
badMode is checking if the execution mode provided as an argument is valid and implemented.
Definition: utility.cc:507
ArmISA::MISCREG_SPSR_FIQ
@ MISCREG_SPSR_FIQ
Definition: miscregs.hh:59
thread_context.hh
ArmISA::MISCREG_CSSELR
@ MISCREG_CSSELR
Definition: miscregs.hh:224
RegVal
uint64_t RegVal
Definition: types.hh:168
ArmISA::MISCREG_PMCR
@ MISCREG_PMCR
Definition: miscregs.hh:345
ArmISA::MISCREG_ID_ISAR5
@ MISCREG_ID_ISAR5
Definition: miscregs.hh:220
ThreadContext::getDTBPtr
virtual BaseTLB * getDTBPtr()=0
ArmISA::mask
Bitfield< 28, 24 > mask
Definition: miscregs_types.hh:711
ArmISA::MISCREG_SCTLR_EL1
@ MISCREG_SCTLR_EL1
Definition: miscregs.hh:571
ArmISA::isSecure
bool isSecure(ThreadContext *tc)
Definition: utility.cc:174
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:171
bits
T bits(T val, int first, int last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:75
MipsISA::ExtMachInst
uint64_t ExtMachInst
Definition: types.hh:39

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