Go to the documentation of this file.
42 NopStaticInst() :
StaticInst(
"gem5 nop", nopMachInst, No_OpClass)
76 if (cachedDisassembly)
77 delete cachedDisassembly;
85 tgt = branchTarget(
pc);
89 if (isIndirectCtrl()) {
90 tgt = branchTarget(tc);
100 panic(
"StaticInst::fetchMicroop() called on instruction "
101 "that is not microcoded.");
107 panic(
"StaticInst::branchTarget() called on instruction "
108 "that is not a PC-relative branch.");
115 panic(
"StaticInst::branchTarget() called on instruction "
116 "that is not an indirect branch.");
123 if (!cachedDisassembly)
124 cachedDisassembly =
new string(generateDisassembly(
pc, symtab));
126 return *cachedDisassembly;
131 const std::string &separator)
const
133 bool printed_a_flag =
false;
135 for (
unsigned int flag = IsNop; flag < Num_Flags; flag++) {
140 outs << FlagsStrings[flag];
141 printed_a_flag =
true;
virtual void advancePC(TheISA::PCState &pcState) const =0
Base, ISA-independent static instruction class.
bool hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc, TheISA::PCState &tgt) const
Return true if the instruction is a control transfer, and if so, return the target address as well.
ThreadContext is the external interface to all thread state for anything outside of the CPU.
virtual TheISA::PCState branchTarget(const TheISA::PCState &pc) const
Return the target address for a PC-relative branch.
void printFlags(std::ostream &outs, const std::string &separator) const
Print a separator separated list of this instruction's set flag names on the given stream.
std::shared_ptr< FaultBase > Fault
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
const char * mnemonic
Base mnemonic (e.g., "add").
constexpr decltype(nullptr) NoFault
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
static StaticInstPtr nullStaticInstPtr
Pointer to a statically allocated "null" instruction object.
virtual StaticInstPtr fetchMicroop(MicroPC upc) const
Return the microop that goes with a particular micropc.
Overload hash function for BasicBlockRange type.
GenericISA::DelaySlotPCState< MachInst > PCState
virtual const std::string & disassemble(Addr pc, const Loader::SymbolTable *symtab=nullptr) const
Return string representation of disassembled instruction.
virtual Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const =0
static StaticInstPtr nopStaticInstPtr
Pointer to a statically allocated generic "nop" instruction object.
virtual std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const =0
Internal function to generate disassembly string.
#define panic(...)
This implements a cprintf based panic() function.
Generated on Wed Sep 30 2020 14:02:00 for gem5 by doxygen 1.8.17