gem5  v20.1.0.0
utility.hh
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1 /*
2  * Copyright (c) 2013 ARM Limited
3  * Copyright (c) 2014-2015 Sven Karlsson
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43 
44 #ifndef __ARCH_RISCV_UTILITY_HH__
45 #define __ARCH_RISCV_UTILITY_HH__
46 
47 #include <cmath>
48 #include <cstdint>
49 #include <sstream>
50 #include <string>
51 
52 #include "arch/riscv/registers.hh"
53 #include "base/types.hh"
54 #include "cpu/reg_class.hh"
55 #include "cpu/static_inst.hh"
56 #include "cpu/thread_context.hh"
57 
58 namespace RiscvISA
59 {
60 
61 template<typename T> inline bool
63 {
64  return false;
65 }
66 
67 template<> inline bool
69 {
70  return std::isnan(val)
71  && (reinterpret_cast<uint32_t&>(val)&0x00400000);
72 }
73 
74 template<> inline bool
76 {
77  return std::isnan(val)
78  && (reinterpret_cast<uint64_t&>(val)&0x0008000000000000ULL);
79 }
80 
81 template<typename T> inline bool
83 {
84  return false;
85 }
86 
87 template<> inline bool
89 {
90  return std::isnan(val)
91  && (reinterpret_cast<uint32_t&>(val)&0x00200000);
92 }
93 
94 template<> inline bool
96 {
97  return std::isnan(val)
98  && (reinterpret_cast<uint64_t&>(val)&0x0004000000000000ULL);
99 }
100 
101 inline PCState
102 buildRetPC(const PCState &curPC, const PCState &callPC)
103 {
104  PCState retPC = callPC;
105  retPC.advance();
106  retPC.pc(curPC.npc());
107  return retPC;
108 }
109 
110 inline uint64_t
111 getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
112 {
113  panic_if(fp, "getArgument(): Floating point arguments not implemented");
114  panic_if(size != 8, "getArgument(): Can only handle 64-bit arguments.");
115  panic_if(number >= ArgumentRegs.size(),
116  "getArgument(): Don't know how to handle stack arguments");
117 
118  // The first 8 integer arguments are passed in registers, the rest
119  // are passed on the stack.
120  return tc->readIntReg(ArgumentRegs[number]);
121 }
122 
123 inline void
125 {
126  // First loop through the integer registers.
127  for (int i = 0; i < NumIntRegs; ++i)
128  dest->setIntReg(i, src->readIntReg(i));
129 
130  // Second loop through the float registers.
131  for (int i = 0; i < NumFloatRegs; ++i)
132  dest->setFloatReg(i, src->readFloatReg(i));
133 
134  // Lastly copy PC/NPC
135  dest->pcState(src->pcState());
136 }
137 
138 inline std::string
140 {
141  if (reg.isIntReg()) {
142  if (reg.index() >= NumIntArchRegs) {
143  /*
144  * This should only happen if a instruction is being speculatively
145  * executed along a not-taken branch, and if that instruction's
146  * width was incorrectly predecoded (i.e., it was predecoded as a
147  * full instruction rather than a compressed one or vice versa).
148  * It also should only happen if a debug flag is on that prints
149  * disassembly information, so rather than panic the incorrect
150  * value is printed for debugging help.
151  */
152  std::stringstream str;
153  str << "?? (x" << reg.index() << ')';
154  return str.str();
155  }
156  return IntRegNames[reg.index()];
157  } else {
158  if (reg.index() >= NumFloatRegs) {
159  std::stringstream str;
160  str << "?? (f" << reg.index() << ')';
161  return str.str();
162  }
163  return FloatRegNames[reg.index()];
164  }
165 }
166 
167 inline void
169 {
170  inst->advancePC(pc);
171 }
172 
173 static inline bool
175 {
176  return true;
177 }
178 
179 inline uint64_t
181 {
182  return 0;
183 }
184 
185 } // namespace RiscvISA
186 
187 #endif // __ARCH_RISCV_UTILITY_HH__
RiscvISA::ArgumentRegs
const std::vector< int > ArgumentRegs
Definition: registers.hh:100
RiscvISA::PCState
Definition: types.hh:53
GenericISA::SimplePCState::advance
void advance()
Definition: types.hh:188
StaticInst::advancePC
virtual void advancePC(TheISA::PCState &pcState) const =0
RiscvISA::fp
Bitfield< 0 > fp
Definition: pra_constants.hh:244
RiscvISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:240
RiscvISA::inUserMode
static bool inUserMode(ThreadContext *tc)
Definition: utility.hh:174
RiscvISA::NumIntRegs
const int NumIntRegs
Definition: registers.hh:81
ThreadContext::setIntReg
virtual void setIntReg(RegIndex reg_idx, RegVal val)=0
RiscvISA::issignalingnan< float >
bool issignalingnan< float >(float val)
Definition: utility.hh:88
RiscvISA::isquietnan< float >
bool isquietnan< float >(float val)
Definition: utility.hh:68
RiscvISA::FloatRegNames
const std::vector< std::string > FloatRegNames
Definition: registers.hh:117
RiscvISA::copyRegs
void copyRegs(ThreadContext *src, ThreadContext *dest)
Definition: utility.hh:124
X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:87
RiscvISA
Definition: fs_workload.cc:36
RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:75
GenericISA::SimplePCState::npc
Addr npc() const
Definition: types.hh:161
ThreadContext::readFloatReg
virtual RegVal readFloatReg(RegIndex reg_idx) const =0
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:88
RiscvISA::getExecutingAsid
uint64_t getExecutingAsid(ThreadContext *tc)
Definition: utility.hh:180
RiscvISA::IntRegNames
const std::vector< std::string > IntRegNames
Definition: registers.hh:107
static_inst.hh
X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
RiscvISA::NumIntArchRegs
const int NumIntArchRegs
Definition: registers.hh:79
RiscvISA::getArgument
uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
Definition: utility.hh:111
RiscvISA::issignalingnan
bool issignalingnan(T val)
Definition: utility.hh:82
RiscvISA::issignalingnan< double >
bool issignalingnan< double >(double val)
Definition: utility.hh:95
registers.hh
ThreadContext::pcState
virtual TheISA::PCState pcState() const =0
RiscvISA::i
Bitfield< 2 > i
Definition: pra_constants.hh:276
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:197
RiscvISA::isquietnan
bool isquietnan(T val)
Definition: utility.hh:62
ThreadContext::setFloatReg
virtual void setFloatReg(RegIndex reg_idx, RegVal val)=0
MipsISA::PCState
GenericISA::DelaySlotPCState< MachInst > PCState
Definition: types.hh:41
types.hh
RiscvISA::isquietnan< double >
bool isquietnan< double >(double val)
Definition: utility.hh:75
reg_class.hh
GenericISA::SimplePCState::pc
Addr pc() const
Definition: types.hh:158
RiscvISA::registerName
std::string registerName(RegId reg)
Definition: utility.hh:139
RiscvISA::buildRetPC
PCState buildRetPC(const PCState &curPC, const PCState &callPC)
Definition: utility.hh:102
RiscvISA::NumFloatRegs
const int NumFloatRegs
Definition: registers.hh:82
RefCountingPtr< StaticInst >
ThreadContext::readIntReg
virtual RegVal readIntReg(RegIndex reg_idx) const =0
RiscvISA::advancePC
void advancePC(PCState &pc, const StaticInstPtr &inst)
Definition: utility.hh:168
thread_context.hh

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