gem5  v20.1.0.0
hsa_packet_processor.hh
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2015-2018 Advanced Micro Devices, Inc.
3  * All rights reserved.
4  *
5  * For use for simulation and test purposes only
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions are met:
9  *
10  * 1. Redistributions of source code must retain the above copyright notice,
11  * this list of conditions and the following disclaimer.
12  *
13  * 2. Redistributions in binary form must reproduce the above copyright notice,
14  * this list of conditions and the following disclaimer in the documentation
15  * and/or other materials provided with the distribution.
16  *
17  * 3. Neither the name of the copyright holder nor the names of its
18  * contributors may be used to endorse or promote products derived from this
19  * software without specific prior written permission.
20  *
21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31  * POSSIBILITY OF SUCH DAMAGE.
32  *
33  * Authors: Eric van Tassell
34  */
35 
36 #ifndef __DEV_HSA_HSA_PACKET_PROCESSOR__
37 #define __DEV_HSA_HSA_PACKET_PROCESSOR__
38 
39 #include <cstdint>
40 
41 #include <queue>
42 
43 #include "dev/dma_device.hh"
44 #include "dev/hsa/hsa.h"
45 #include "dev/hsa/hsa_queue.hh"
46 #include "params/HSAPacketProcessor.hh"
47 
48 #define AQL_PACKET_SIZE 64
49 #define PAGE_SIZE 4096
50 #define NUM_DMA_BUFS 16
51 #define DMA_BUF_SIZE (AQL_PACKET_SIZE * NUM_DMA_BUFS)
52 // HSA runtime supports only 5 signals per barrier packet
53 #define NumSignalsPerBarrier 5
54 
55 // Ideally, each queue should store this status and
56 // the processPkt() should make decisions based on that
57 // status variable.
58 typedef enum {
59  UNBLOCKED = 0, // Unblocked queue, can submit packets.
60  BLOCKED_BBIT, // Queue blocked by barrier bit.
61  // Can submit packet packets after
62  // previous packet completes.
63  BLOCKED_BPKT, // Queue blocked by barrier packet.
64  // Can submit packet packets after
65  // barrier packet completes.
66 } Q_STATE;
67 
68 class HSADevice;
69 class HWScheduler;
70 
71 // Our internal representation of an HSA queue
73  public:
74  uint64_t basePointer;
75  uint64_t doorbellPointer;
76  uint64_t writeIndex;
77  uint64_t readIndex;
78  uint32_t numElts;
79  uint64_t hostReadIndexPtr;
82 
83  HSAQueueDescriptor(uint64_t base_ptr, uint64_t db_ptr,
84  uint64_t hri_ptr, uint32_t size)
85  : basePointer(base_ptr), doorbellPointer(db_ptr),
86  writeIndex(0), readIndex(0),
87  numElts(size), hostReadIndexPtr(hri_ptr),
89  dmaInProgress(false)
90  { }
91  uint64_t spaceRemaining() { return numElts - (writeIndex - readIndex); }
92  uint64_t spaceUsed() { return writeIndex - readIndex; }
93  uint32_t objSize() { return AQL_PACKET_SIZE; }
94  uint32_t numObjs() { return numElts; }
95  bool isFull() { return spaceRemaining() == 0; }
96  bool isEmpty() { return spaceRemaining() == numElts; }
97 
98  uint64_t ptr(uint64_t ix)
99  {
100  return basePointer +
101  ((ix % numElts) * objSize());
102  }
103 };
104 
118 {
119  private:
121  std::string _name;
124  uint64_t _wrIdx; // Points to next write location
125  uint64_t _rdIdx; // Read pointer of AQL buffer
126  uint64_t _dispIdx; // Dispatch pointer of AQL buffer
127 
128  public:
129  std::string name() {return _name;}
130  AQLRingBuffer(uint32_t size, const std::string name);
131  int allocEntry(uint32_t nBufReq);
132  bool freeEntry(void *pkt);
133 
143  void
144  saveHostDispAddr(Addr host_pkt_addr, int num_pkts, int ix)
145  {
146  for (int i = 0; i < num_pkts; ++i) {
147  _hostDispAddresses[ix % numObjs()] = host_pkt_addr + i * objSize();
148  ++ix;
149  }
150  }
151 
152  Addr
153  hostDispAddr() const
154  {
155  return _hostDispAddresses[dispIdx() % numObjs()];
156  }
157 
158  bool
159  dispPending() const
160  {
161  int packet_type = (_aqlBuf[_dispIdx % _aqlBuf.size()].header
163  ((1 << HSA_PACKET_HEADER_WIDTH_TYPE) - 1);
164  return (_dispIdx < _wrIdx) && packet_type != HSA_PACKET_TYPE_INVALID;
165  }
166 
175  bool
177  {
178  for (int i = _rdIdx + 1; i < _dispIdx; i++) {
179  if (!_aqlComplete[i % _aqlBuf.size()]) {
180  return false;
181  }
182  }
183  return !_aqlComplete[_rdIdx % _aqlBuf.size()] && _rdIdx != _dispIdx;
184  }
185 
186  uint32_t nFree() const { return _aqlBuf.size() - (_wrIdx - _rdIdx); }
187  void *ptr(uint32_t ix) { return _aqlBuf.data() + (ix % _aqlBuf.size()); }
188  uint32_t numObjs() const { return _aqlBuf.size(); };
189  uint32_t objSize() const { return AQL_PACKET_SIZE; }
190  uint64_t dispIdx() const { return _dispIdx; }
191  uint64_t wrIdx() const { return _wrIdx; }
192  uint64_t rdIdx() const { return _rdIdx; }
193  uint64_t* rdIdxPtr() { return &_rdIdx; }
194  void incRdIdx(uint64_t value) { _rdIdx += value; }
195  void incWrIdx(uint64_t value) { _wrIdx += value; }
196  void incDispIdx(uint64_t value) { _dispIdx += value; }
197  uint64_t compltnPending() { return (_dispIdx - _rdIdx); }
198 };
199 
200 typedef struct QueueContext {
203  // used for HSA packets that enforce synchronization with barrier bit
206  AQLRingBuffer* aql_buf)
207  : qDesc(q_desc), aqlBuf(aql_buf), barrierBit(false)
208  {}
209  QueueContext() : qDesc(NULL), aqlBuf(NULL), barrierBit(false) {}
210 } QCntxt;
211 
213 {
214  friend class HWScheduler;
215  protected:
216  typedef void (DmaDevice::*DmaFnPtr)(Addr, int, Event*, uint8_t*, Tick);
219 
220  // Structure to store the read values of dependency signals
221  // from shared memory. Also used for tracking the status of
222  // those reads while they are in progress
224  {
225  public:
227  : pendingReads(0), allRead(false), discardRead(false)
228  {
230  }
231  void handleReadDMA();
233  bool allRead;
234  // If this queue is unmapped when there are pending reads, then
235  // the pending reads has to be discarded.
237  // values stores the value of already read dependency signal
239  void
241  {
242  std::fill(values.begin(), values.end(), 1);
243  }
244  };
245 
246  class QueueProcessEvent : public Event
247  {
248  private:
250  uint32_t rqIdx;
251  public:
252  QueueProcessEvent(HSAPacketProcessor *_hsaPP, uint32_t _rqIdx)
253  : Event(Default_Pri), hsaPP(_hsaPP), rqIdx(_rqIdx)
254  {}
255  virtual void process();
256  virtual const char *description() const;
257  };
258 
259  // Registered queue list entry; each entry has one queueDescriptor and
260  // associated AQL buffer
261  class RQLEntry
262  {
263  public:
264  RQLEntry(HSAPacketProcessor *hsaPP, uint32_t rqIdx)
265  : aqlProcessEvent(hsaPP, rqIdx) {}
267  bool dispPending() { return qCntxt.aqlBuf->dispPending() > 0; }
268  uint64_t compltnPending() { return qCntxt.aqlBuf->compltnPending(); }
271  void setBarrierBit(bool set_val) { qCntxt.barrierBit = set_val; }
272  bool getBarrierBit() const { return qCntxt.barrierBit; }
273  bool isLastOutstandingPkt() const
274  {
276  }
277  };
278  // Keeps track of queueDescriptors of registered queues
280 
281  void translateOrDie(Addr vaddr, Addr &paddr);
282  void dmaVirt(DmaFnPtr, Addr host_addr, unsigned size, Event *event,
283  void *data, Tick delay = 0);
284 
285  void dmaReadVirt(Addr host_addr, unsigned size, Event *event,
286  void *data, Tick delay = 0);
287 
288  void dmaWriteVirt(Addr host_addr, unsigned size, Event *event,
289  void *data, Tick delay = 0);
290  Q_STATE processPkt(void* pkt, uint32_t rl_idx, Addr host_pkt_addr);
291  void displayQueueDescriptor(int pid, uint32_t rl_idx);
292 
293  public:
295  getQueueDesc(uint32_t queId)
296  {
297  return regdQList.at(queId)->qCntxt.qDesc;
298  }
299  class RQLEntry*
300  getRegdListEntry(uint32_t queId)
301  {
302  return regdQList.at(queId);
303  }
304 
310 
311  typedef HSAPacketProcessorParams Params;
312  HSAPacketProcessor(const Params *p);
314  void setDeviceQueueDesc(uint64_t hostReadIndexPointer,
315  uint64_t basePointer,
316  uint64_t queue_id,
317  uint32_t size);
318  void unsetDeviceQueueDesc(uint64_t queue_id);
319  void setDevice(HSADevice * dev);
320  void updateReadIndex(int, uint32_t);
321  void getCommandsFromHost(int pid, uint32_t rl_idx);
322 
323  // PIO interface
324  virtual Tick read(Packet*);
325  virtual Tick write(Packet*);
326  virtual AddrRangeList getAddrRanges() const;
327  void finishPkt(void *pkt, uint32_t rl_idx);
328  void finishPkt(void *pkt) { finishPkt(pkt, 0); }
329  void schedAQLProcessing(uint32_t rl_idx);
330  void schedAQLProcessing(uint32_t rl_idx, Tick delay);
331 
333  {
334  protected:
336  public:
339  {}
340  virtual void process() { signalState->handleReadDMA(); }
341  virtual const char *description() const;
342  };
343 
350  {
351  public:
353 
354  void process() override { }
355  const char *description() const override;
356 
357  };
358 
362  struct dma_series_ctx {
363  // deal with the fact dma ops can complete out of issue order
364  uint32_t pkts_ttl;
365  uint32_t pkts_2_go;
366  uint32_t start_ix;
367  uint32_t rl_idx;
368 
369  dma_series_ctx(uint32_t _pkts_ttl,
370  uint32_t _pkts_2_go,
371  uint32_t _start_ix,
372  uint32_t _rl_idx)
373  : pkts_ttl(_pkts_2_go), pkts_2_go(_pkts_2_go),
374  start_ix(_start_ix), rl_idx(_rl_idx)
375  {};
377  };
378 
379  class CmdQueueCmdDmaEvent : public Event
380  {
381  protected:
383  int pid;
384  bool isRead;
385  uint32_t ix_start;
386  uint num_pkts;
388  void *dest_4debug;
389 
390  public:
392  uint32_t dma_buf_ix, uint num_bufs,
394  virtual void process();
395  virtual const char *description() const;
396  };
397 };
398 
399 #endif // __DEV_HSA_HSA_PACKET_PROCESSOR__
HSAPacketProcessor::DepSignalsReadDmaEvent
Definition: hsa_packet_processor.hh:332
HSAPacketProcessor::QueueProcessEvent::hsaPP
HSAPacketProcessor * hsaPP
Definition: hsa_packet_processor.hh:249
HSAPacketProcessor::numHWQueues
int numHWQueues
Definition: hsa_packet_processor.hh:305
EventBase::AutoDelete
static const FlagsType AutoDelete
Definition: eventq.hh:102
HSAPacketProcessor::UpdateReadDispIdDmaEvent::UpdateReadDispIdDmaEvent
UpdateReadDispIdDmaEvent()
Definition: hsa_packet_processor.cc:209
HSAPacketProcessor::~HSAPacketProcessor
~HSAPacketProcessor()
Definition: hsa_packet_processor.cc:85
data
const char data[]
Definition: circlebuf.test.cc:42
AQLRingBuffer::freeEntry
bool freeEntry(void *pkt)
Definition: hsa_packet_processor.cc:616
HSAPacketProcessor::CmdQueueCmdDmaEvent::dest_4debug
void * dest_4debug
Definition: hsa_packet_processor.hh:388
HSAPacketProcessor::CmdQueueCmdDmaEvent::ix_start
uint32_t ix_start
Definition: hsa_packet_processor.hh:385
ArmISA::i
Bitfield< 7 > i
Definition: miscregs_types.hh:63
HSAPacketProcessor::UpdateReadDispIdDmaEvent::description
const char * description() const override
Return a C string describing the event.
HSAPacketProcessor::getQueueDesc
HSAQueueDescriptor * getQueueDesc(uint32_t queId)
Definition: hsa_packet_processor.hh:295
HSAPacketProcessor::QueueProcessEvent::QueueProcessEvent
QueueProcessEvent(HSAPacketProcessor *_hsaPP, uint32_t _rqIdx)
Definition: hsa_packet_processor.hh:252
HSAPacketProcessor::DepSignalsReadDmaEvent::description
virtual const char * description() const
Return a C string describing the event.
BLOCKED_BBIT
@ BLOCKED_BBIT
Definition: hsa_packet_processor.hh:60
HSAPacketProcessor::DepSignalsReadDmaEvent::process
virtual void process()
Definition: hsa_packet_processor.hh:340
HSAPacketProcessor::UpdateReadDispIdDmaEvent::process
void process() override
Definition: hsa_packet_processor.hh:354
AQLRingBuffer::saveHostDispAddr
void saveHostDispAddr(Addr host_pkt_addr, int num_pkts, int ix)
the kernel may try to read from the dispatch packet, so we need to keep the host address that corresp...
Definition: hsa_packet_processor.hh:144
HSAQueueDescriptor::basePointer
uint64_t basePointer
Definition: hsa_packet_processor.hh:74
HSAPacketProcessor::dma_series_ctx::pkts_ttl
uint32_t pkts_ttl
Definition: hsa_packet_processor.hh:364
HSAPacketProcessor::dma_series_ctx::start_ix
uint32_t start_ix
Definition: hsa_packet_processor.hh:366
HSAPacketProcessor::pktProcessDelay
const Tick pktProcessDelay
Definition: hsa_packet_processor.hh:309
AQLRingBuffer::isLastOutstandingPkt
bool isLastOutstandingPkt() const
Packets aren't guaranteed to be completed in-order, and we need to know when the last packet is finis...
Definition: hsa_packet_processor.hh:176
HSAPacketProcessor::RQLEntry::isLastOutstandingPkt
bool isLastOutstandingPkt() const
Definition: hsa_packet_processor.hh:273
QueueContext::QueueContext
QueueContext(HSAQueueDescriptor *q_desc, AQLRingBuffer *aql_buf)
Definition: hsa_packet_processor.hh:205
Tick
uint64_t Tick
Tick count type.
Definition: types.hh:63
AQLRingBuffer::_aqlBuf
std::vector< hsa_kernel_dispatch_packet_t > _aqlBuf
Definition: hsa_packet_processor.hh:120
HSAQueueDescriptor::isEmpty
bool isEmpty()
Definition: hsa_packet_processor.hh:96
HSAPacketProcessor::pioDelay
Tick pioDelay
Definition: hsa_packet_processor.hh:308
AQLRingBuffer::dispPending
bool dispPending() const
Definition: hsa_packet_processor.hh:159
NumSignalsPerBarrier
#define NumSignalsPerBarrier
Definition: hsa_packet_processor.hh:53
QCntxt
struct QueueContext QCntxt
HSAPacketProcessor::finishPkt
void finishPkt(void *pkt, uint32_t rl_idx)
Definition: hsa_packet_processor.cc:667
HSAPacketProcessor::dmaWriteVirt
void dmaWriteVirt(Addr host_addr, unsigned size, Event *event, void *data, Tick delay=0)
Definition: hsa_packet_processor.cc:202
std::vector
STL vector class.
Definition: stl.hh:37
AQL_PACKET_SIZE
#define AQL_PACKET_SIZE
Definition: hsa_packet_processor.hh:48
HSAQueueDescriptor::dmaInProgress
bool dmaInProgress
Definition: hsa_packet_processor.hh:81
HSAPacketProcessor::CmdQueueCmdDmaEvent::hsaPP
HSAPacketProcessor * hsaPP
Definition: hsa_packet_processor.hh:382
HSAPacketProcessor::dma_series_ctx::dma_series_ctx
dma_series_ctx(uint32_t _pkts_ttl, uint32_t _pkts_2_go, uint32_t _start_ix, uint32_t _rl_idx)
Definition: hsa_packet_processor.hh:369
AQLRingBuffer::incWrIdx
void incWrIdx(uint64_t value)
Definition: hsa_packet_processor.hh:195
QueueContext::QueueContext
QueueContext()
Definition: hsa_packet_processor.hh:209
Q_STATE
Q_STATE
Definition: hsa_packet_processor.hh:58
BLOCKED_BPKT
@ BLOCKED_BPKT
Definition: hsa_packet_processor.hh:63
HSAQueueDescriptor
Definition: hsa_packet_processor.hh:72
hsa_queue.hh
HSAPacketProcessor::pioSize
Addr pioSize
Definition: hsa_packet_processor.hh:307
hsa.h
AQLRingBuffer::dispIdx
uint64_t dispIdx() const
Definition: hsa_packet_processor.hh:190
HSAPacketProcessor::pioAddr
Addr pioAddr
Definition: hsa_packet_processor.hh:306
HSAPacketProcessor::setDeviceQueueDesc
void setDeviceQueueDesc(uint64_t hostReadIndexPointer, uint64_t basePointer, uint64_t queue_id, uint32_t size)
Definition: hsa_packet_processor.cc:99
AQLRingBuffer::_rdIdx
uint64_t _rdIdx
Definition: hsa_packet_processor.hh:125
AQLRingBuffer::nFree
uint32_t nFree() const
Definition: hsa_packet_processor.hh:186
HSA_PACKET_HEADER_WIDTH_TYPE
@ HSA_PACKET_HEADER_WIDTH_TYPE
Definition: hsa.h:2827
AQLRingBuffer::name
std::string name()
Definition: hsa_packet_processor.hh:129
AQLRingBuffer
Internal ring buffer which is used to prefetch/store copies of the in-memory HSA ring buffer.
Definition: hsa_packet_processor.hh:117
HSAPacketProcessor::setDevice
void setDevice(HSADevice *dev)
Definition: hsa_packet_processor.cc:636
HSAPacketProcessor::dma_series_ctx::~dma_series_ctx
~dma_series_ctx()
Definition: hsa_packet_processor.hh:376
HSAPacketProcessor::QueueProcessEvent::description
virtual const char * description() const
Return a C string describing the event.
HWScheduler
Definition: hw_scheduler.hh:45
HSAPacketProcessor::getCommandsFromHost
void getCommandsFromHost(int pid, uint32_t rl_idx)
Definition: hsa_packet_processor.cc:510
HSAPacketProcessor::getAddrRanges
virtual AddrRangeList getAddrRanges() const
Every PIO device is obliged to provide an implementation that returns the address ranges the device r...
Definition: hsa_packet_processor.cc:112
AQLRingBuffer::hostDispAddr
Addr hostDispAddr() const
Definition: hsa_packet_processor.hh:153
QueueContext::barrierBit
bool barrierBit
Definition: hsa_packet_processor.hh:204
HSAQueueDescriptor::hostReadIndexPtr
uint64_t hostReadIndexPtr
Definition: hsa_packet_processor.hh:79
HSAPacketProcessor::SignalState::SignalState
SignalState()
Definition: hsa_packet_processor.hh:226
UNBLOCKED
@ UNBLOCKED
Definition: hsa_packet_processor.hh:59
dma_device.hh
HSAPacketProcessor::CmdQueueCmdDmaEvent::pid
int pid
Definition: hsa_packet_processor.hh:383
QueueContext::aqlBuf
AQLRingBuffer * aqlBuf
Definition: hsa_packet_processor.hh:202
ArmISA::ss
Bitfield< 21 > ss
Definition: miscregs_types.hh:56
HSAQueueDescriptor::ptr
uint64_t ptr(uint64_t ix)
Definition: hsa_packet_processor.hh:98
AQLRingBuffer::wrIdx
uint64_t wrIdx() const
Definition: hsa_packet_processor.hh:191
HSAPacketProcessor
Definition: hsa_packet_processor.hh:212
AQLRingBuffer::objSize
uint32_t objSize() const
Definition: hsa_packet_processor.hh:189
AQLRingBuffer::incRdIdx
void incRdIdx(uint64_t value)
Definition: hsa_packet_processor.hh:194
Event
Definition: eventq.hh:246
HSAPacketProcessor::CmdQueueCmdDmaEvent::CmdQueueCmdDmaEvent
CmdQueueCmdDmaEvent(HSAPacketProcessor *hsaPP, int pid, bool isRead, uint32_t dma_buf_ix, uint num_bufs, dma_series_ctx *series_ctx, void *dest_4debug)
Definition: hsa_packet_processor.cc:241
AQLRingBuffer::_wrIdx
uint64_t _wrIdx
Definition: hsa_packet_processor.hh:124
HSAPacketProcessor::processPkt
Q_STATE processPkt(void *pkt, uint32_t rl_idx, Addr host_pkt_addr)
Definition: hsa_packet_processor.cc:305
AQLRingBuffer::AQLRingBuffer
AQLRingBuffer(uint32_t size, const std::string name)
Definition: hsa_packet_processor.cc:602
MipsISA::vaddr
vaddr
Definition: pra_constants.hh:275
HSAPacketProcessor::SignalState::resetSigVals
void resetSigVals()
Definition: hsa_packet_processor.hh:240
HSAPacketProcessor::dmaReadVirt
void dmaReadVirt(Addr host_addr, unsigned size, Event *event, void *data, Tick delay=0)
Definition: hsa_packet_processor.cc:193
MipsISA::event
Bitfield< 10, 5 > event
Definition: pra_constants.hh:297
AQLRingBuffer::rdIdx
uint64_t rdIdx() const
Definition: hsa_packet_processor.hh:192
HSAQueueDescriptor::spaceRemaining
uint64_t spaceRemaining()
Definition: hsa_packet_processor.hh:91
HSAPacketProcessor::regdQList
std::vector< class RQLEntry * > regdQList
Definition: hsa_packet_processor.hh:279
HSAPacketProcessor::Params
HSAPacketProcessorParams Params
Definition: hsa_packet_processor.hh:311
HSAPacketProcessor::unsetDeviceQueueDesc
void unsetDeviceQueueDesc(uint64_t queue_id)
Definition: hsa_packet_processor.cc:93
HSAPacketProcessor::RQLEntry
Definition: hsa_packet_processor.hh:261
HSAPacketProcessor::DepSignalsReadDmaEvent::DepSignalsReadDmaEvent
DepSignalsReadDmaEvent(SignalState *ss)
Definition: hsa_packet_processor.hh:337
HSAPacketProcessor::HSAPacketProcessor
HSAPacketProcessor(const Params *p)
Definition: hsa_packet_processor.cc:73
HSAPacketProcessor::SignalState::discardRead
bool discardRead
Definition: hsa_packet_processor.hh:236
HSAQueueDescriptor::objSize
uint32_t objSize()
Definition: hsa_packet_processor.hh:93
HSAPacketProcessor::dmaVirt
void dmaVirt(DmaFnPtr, Addr host_addr, unsigned size, Event *event, void *data, Tick delay=0)
Definition: hsa_packet_processor.cc:166
HSAPacketProcessor::SignalState::handleReadDMA
void handleReadDMA()
Definition: hsa_packet_processor.cc:497
HSA_PACKET_HEADER_TYPE
@ HSA_PACKET_HEADER_TYPE
Packet type.
Definition: hsa.h:2786
AQLRingBuffer::incDispIdx
void incDispIdx(uint64_t value)
Definition: hsa_packet_processor.hh:196
HSAQueueDescriptor::numObjs
uint32_t numObjs()
Definition: hsa_packet_processor.hh:94
HSAQueueDescriptor::doorbellPointer
uint64_t doorbellPointer
Definition: hsa_packet_processor.hh:75
HSAPacketProcessor::updateReadIndex
void updateReadIndex(int, uint32_t)
Definition: hsa_packet_processor.cc:217
AQLRingBuffer::allocEntry
int allocEntry(uint32_t nBufReq)
Definition: hsa_packet_processor.cc:642
HSAPacketProcessor::SignalState::allRead
bool allRead
Definition: hsa_packet_processor.hh:233
HSAPacketProcessor::SignalState
Definition: hsa_packet_processor.hh:223
AQLRingBuffer::_name
std::string _name
Definition: hsa_packet_processor.hh:121
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
AQLRingBuffer::_dispIdx
uint64_t _dispIdx
Definition: hsa_packet_processor.hh:126
HSAPacketProcessor::translateOrDie
void translateOrDie(Addr vaddr, Addr &paddr)
Definition: hsa_packet_processor.cc:154
HSAPacketProcessor::hwSchdlr
HWScheduler * hwSchdlr
Definition: hsa_packet_processor.hh:218
AQLRingBuffer::rdIdxPtr
uint64_t * rdIdxPtr()
Definition: hsa_packet_processor.hh:193
HSAPacketProcessor::RQLEntry::RQLEntry
RQLEntry(HSAPacketProcessor *hsaPP, uint32_t rqIdx)
Definition: hsa_packet_processor.hh:264
QueueContext::qDesc
HSAQueueDescriptor * qDesc
Definition: hsa_packet_processor.hh:201
HSAPacketProcessor::write
virtual Tick write(Packet *)
Definition: hsa_packet_processor.cc:124
HSAPacketProcessor::dma_series_ctx::rl_idx
uint32_t rl_idx
Definition: hsa_packet_processor.hh:367
HSA_PACKET_TYPE_INVALID
@ HSA_PACKET_TYPE_INVALID
The packet has been processed in the past, but has not been reassigned to the packet processor.
Definition: hsa.h:2728
QueueContext
Definition: hsa_packet_processor.hh:200
AQLRingBuffer::_aqlComplete
std::vector< bool > _aqlComplete
Definition: hsa_packet_processor.hh:123
HSAQueueDescriptor::stalledOnDmaBufAvailability
bool stalledOnDmaBufAvailability
Definition: hsa_packet_processor.hh:80
HSAPacketProcessor::RQLEntry::getBarrierBit
bool getBarrierBit() const
Definition: hsa_packet_processor.hh:272
HSAPacketProcessor::RQLEntry::aqlProcessEvent
QueueProcessEvent aqlProcessEvent
Definition: hsa_packet_processor.hh:270
MipsISA::fill
fill
Definition: pra_constants.hh:54
HSAPacketProcessor::read
virtual Tick read(Packet *)
Definition: hsa_packet_processor.cc:146
HSAPacketProcessor::DepSignalsReadDmaEvent::signalState
SignalState * signalState
Definition: hsa_packet_processor.hh:335
HSAPacketProcessor::getRegdListEntry
class RQLEntry * getRegdListEntry(uint32_t queId)
Definition: hsa_packet_processor.hh:300
HSAPacketProcessor::CmdQueueCmdDmaEvent::process
virtual void process()
Definition: hsa_packet_processor.cc:256
AQLRingBuffer::numObjs
uint32_t numObjs() const
Definition: hsa_packet_processor.hh:188
HSAPacketProcessor::schedAQLProcessing
void schedAQLProcessing(uint32_t rl_idx)
Definition: hsa_packet_processor.cc:299
DmaDevice
Definition: dma_device.hh:165
HSAPacketProcessor::RQLEntry::compltnPending
uint64_t compltnPending()
Definition: hsa_packet_processor.hh:268
HSAQueueDescriptor::HSAQueueDescriptor
HSAQueueDescriptor(uint64_t base_ptr, uint64_t db_ptr, uint64_t hri_ptr, uint32_t size)
Definition: hsa_packet_processor.hh:83
HSAPacketProcessor::finishPkt
void finishPkt(void *pkt)
Definition: hsa_packet_processor.hh:328
HSAQueueDescriptor::isFull
bool isFull()
Definition: hsa_packet_processor.hh:95
HSAPacketProcessor::hsa_device
HSADevice * hsa_device
Definition: hsa_packet_processor.hh:217
HSAPacketProcessor::CmdQueueCmdDmaEvent::num_pkts
uint num_pkts
Definition: hsa_packet_processor.hh:386
Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:257
HSAPacketProcessor::DmaFnPtr
void(DmaDevice::* DmaFnPtr)(Addr, int, Event *, uint8_t *, Tick)
Definition: hsa_packet_processor.hh:216
EventBase::Default_Pri
static const Priority Default_Pri
Default is zero for historical reasons.
Definition: eventq.hh:174
HSAPacketProcessor::CmdQueueCmdDmaEvent::description
virtual const char * description() const
Return a C string describing the event.
HSAPacketProcessor::displayQueueDescriptor
void displayQueueDescriptor(int pid, uint32_t rl_idx)
Definition: hsa_packet_processor.cc:591
HSAPacketProcessor::QueueProcessEvent::rqIdx
uint32_t rqIdx
Definition: hsa_packet_processor.hh:250
AQLRingBuffer::ptr
void * ptr(uint32_t ix)
Definition: hsa_packet_processor.hh:187
HSAQueueDescriptor::writeIndex
uint64_t writeIndex
Definition: hsa_packet_processor.hh:76
HSAPacketProcessor::RQLEntry::dispPending
bool dispPending()
Definition: hsa_packet_processor.hh:267
AQLRingBuffer::_hostDispAddresses
std::vector< Addr > _hostDispAddresses
Definition: hsa_packet_processor.hh:122
MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:323
std::list< AddrRange >
HSAPacketProcessor::SignalState::values
std::vector< hsa_signal_value_t > values
Definition: hsa_packet_processor.hh:238
HSAPacketProcessor::SignalState::pendingReads
int pendingReads
Definition: hsa_packet_processor.hh:232
HSAPacketProcessor::CmdQueueCmdDmaEvent
Definition: hsa_packet_processor.hh:379
HSAPacketProcessor::QueueProcessEvent::process
virtual void process()
Definition: hsa_packet_processor.cc:445
HSAQueueDescriptor::spaceUsed
uint64_t spaceUsed()
Definition: hsa_packet_processor.hh:92
HSAPacketProcessor::CmdQueueCmdDmaEvent::isRead
bool isRead
Definition: hsa_packet_processor.hh:384
HSAQueueDescriptor::numElts
uint32_t numElts
Definition: hsa_packet_processor.hh:78
HSADevice
Definition: hsa_device.hh:46
HSAPacketProcessor::CmdQueueCmdDmaEvent::series_ctx
dma_series_ctx * series_ctx
Definition: hsa_packet_processor.hh:387
HSAQueueDescriptor::readIndex
uint64_t readIndex
Definition: hsa_packet_processor.hh:77
AQLRingBuffer::compltnPending
uint64_t compltnPending()
Definition: hsa_packet_processor.hh:197
HSAPacketProcessor::QueueProcessEvent
Definition: hsa_packet_processor.hh:246
HSAPacketProcessor::RQLEntry::qCntxt
QCntxt qCntxt
Definition: hsa_packet_processor.hh:266
HSAPacketProcessor::UpdateReadDispIdDmaEvent
this event is used to update the read_disp_id field (the read pointer) of the MQD,...
Definition: hsa_packet_processor.hh:349
DmaDevice::Params
DmaDeviceParams Params
Definition: dma_device.hh:171
HSAPacketProcessor::RQLEntry::setBarrierBit
void setBarrierBit(bool set_val)
Definition: hsa_packet_processor.hh:271
HSAPacketProcessor::dma_series_ctx::pkts_2_go
uint32_t pkts_2_go
Definition: hsa_packet_processor.hh:365
HSAPacketProcessor::RQLEntry::depSignalRdState
SignalState depSignalRdState
Definition: hsa_packet_processor.hh:269
HSAPacketProcessor::dma_series_ctx
Calls getCurrentEntry once the queueEntry has been dmaRead.
Definition: hsa_packet_processor.hh:362

Generated on Wed Sep 30 2020 14:02:11 for gem5 by doxygen 1.8.17