gem5  v20.1.0.0
ltage.cc
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3  *
4  * Copyright (c) 2006 INRIA (Institut National de Recherche en
5  * Informatique et en Automatique / French National Research Institute
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33 
34 /* @file
35  * Implementation of a L-TAGE branch predictor
36  */
37 
38 #include "cpu/pred/ltage.hh"
39 
40 #include "base/intmath.hh"
41 #include "base/logging.hh"
42 #include "base/random.hh"
43 #include "base/trace.hh"
44 #include "debug/Fetch.hh"
45 #include "debug/LTage.hh"
46 
47 LTAGE::LTAGE(const LTAGEParams *params)
48  : TAGE(params), loopPredictor(params->loop_predictor)
49 {
50 }
51 
52 void
54 {
55  TAGE::init();
56 }
57 
58 //prediction
59 bool
60 LTAGE::predict(ThreadID tid, Addr branch_pc, bool cond_branch, void* &b)
61 {
63  b = (void*)(bi);
64 
65  bool pred_taken = tage->tagePredict(tid, branch_pc, cond_branch,
66  bi->tageBranchInfo);
67 
68  pred_taken = loopPredictor->loopPredict(tid, branch_pc, cond_branch,
69  bi->lpBranchInfo, pred_taken,
70  instShiftAmt);
71  if (cond_branch) {
72  if (bi->lpBranchInfo->loopPredUsed) {
73  bi->tageBranchInfo->provider = LOOP;
74  }
75  DPRINTF(LTage, "Predict for %lx: taken?:%d, loopTaken?:%d, "
76  "loopValid?:%d, loopUseCounter:%d, tagePred:%d, altPred:%d\n",
77  branch_pc, pred_taken, bi->lpBranchInfo->loopPred,
78  bi->lpBranchInfo->loopPredValid,
80  bi->tageBranchInfo->tagePred, bi->tageBranchInfo->altTaken);
81  }
82 
83  // record final prediction
84  bi->lpBranchInfo->predTaken = pred_taken;
85 
86  return pred_taken;
87 }
88 
89 // PREDICTOR UPDATE
90 void
91 LTAGE::update(ThreadID tid, Addr branch_pc, bool taken, void* bp_history,
92  bool squashed, const StaticInstPtr & inst, Addr corrTarget)
93 {
94  assert(bp_history);
95 
96  LTageBranchInfo* bi = static_cast<LTageBranchInfo*>(bp_history);
97 
98  if (squashed) {
100  // This restores the global history, then update it
101  // and recomputes the folded histories.
102  tage->squash(tid, taken, bi->tageBranchInfo, corrTarget);
103 
104  if (bi->tageBranchInfo->condBranch) {
105  loopPredictor->squashLoop(bi->lpBranchInfo);
106  }
107  }
108  return;
109  }
110 
111  int nrand = random_mt.random<int>() & 3;
112  if (bi->tageBranchInfo->condBranch) {
113  DPRINTF(LTage, "Updating tables for branch:%lx; taken?:%d\n",
114  branch_pc, taken);
115  tage->updateStats(taken, bi->tageBranchInfo);
116 
117  loopPredictor->updateStats(taken, bi->lpBranchInfo);
118 
119  loopPredictor->condBranchUpdate(tid, branch_pc, taken,
120  bi->tageBranchInfo->tagePred, bi->lpBranchInfo, instShiftAmt);
121 
122  tage->condBranchUpdate(tid, branch_pc, taken, bi->tageBranchInfo,
123  nrand, corrTarget, bi->lpBranchInfo->predTaken);
124  }
125 
126  tage->updateHistories(tid, branch_pc, taken, bi->tageBranchInfo, false,
127  inst, corrTarget);
128 
129  delete bi;
130 }
131 
132 void
133 LTAGE::squash(ThreadID tid, void *bp_history)
134 {
135  LTageBranchInfo* bi = (LTageBranchInfo*)(bp_history);
136 
137  if (bi->tageBranchInfo->condBranch) {
138  loopPredictor->squash(tid, bi->lpBranchInfo);
139  }
140 
141  TAGE::squash(tid, bp_history);
142 }
143 
144 void
146 {
147  TAGE::regStats();
148 }
149 
150 LTAGE*
151 LTAGEParams::create()
152 {
153  return new LTAGE(this);
154 }
Stats::Group::regStats
virtual void regStats()
Callback to set stat parameters.
Definition: group.cc:64
ltage.hh
LTAGE::regStats
virtual void regStats() override
Callback to set stat parameters.
Definition: ltage.cc:145
TAGE
Definition: tage.hh:58
LoopPredictor::updateStats
void updateStats(bool taken, BranchInfo *bi)
Update the stats.
Definition: loop_predictor.cc:315
TAGE::squash
virtual void squash(ThreadID tid, void *bp_history) override
Definition: tage.cc:84
ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:227
random.hh
LTAGE
Definition: ltage.hh:60
LoopPredictor::squash
void squash(ThreadID tid, BranchInfo *bi)
Definition: loop_predictor.cc:293
LTAGE::LTageBranchInfo
Definition: ltage.hh:85
LTAGE::LOOP
@ LOOP
Definition: ltage.hh:80
BPredUnit::instShiftAmt
const unsigned instShiftAmt
Number of bits to shift instructions by for predictor addresses.
Definition: bpred_unit.hh:312
random_mt
Random random_mt
Definition: random.cc:96
PowerISA::bi
Bitfield< 20, 16 > bi
Definition: types.hh:63
TAGEBase::condBranchUpdate
virtual void condBranchUpdate(ThreadID tid, Addr branch_pc, bool taken, BranchInfo *bi, int nrand, Addr corrTarget, bool pred, bool preAdjustAlloc=false)
Update TAGE for conditional branches.
Definition: tage_base.cc:508
LTAGE::update
void update(ThreadID tid, Addr branch_addr, bool taken, void *bp_history, bool squashed, const StaticInstPtr &inst, Addr corrTarget) override
Updates the BP with taken/not taken information.
Definition: ltage.cc:91
TAGE::tage
TAGEBase * tage
Definition: tage.hh:61
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:234
LoopPredictor::squashLoop
void squashLoop(BranchInfo *bi)
Definition: loop_predictor.cc:304
TAGEBase::updateHistories
virtual void updateHistories(ThreadID tid, Addr branch_pc, bool taken, BranchInfo *b, bool speculative, const StaticInstPtr &inst=StaticInst::nullStaticInstPtr, Addr target=MaxAddr)
(Speculatively) updates global histories (path and direction).
Definition: tage_base.cc:582
TAGEBase::updateStats
virtual void updateStats(bool taken, BranchInfo *bi)
Update the stats.
Definition: tage_base.cc:656
LTAGE::squash
void squash(ThreadID tid, void *bp_history) override
Definition: ltage.cc:133
LoopPredictor::loopPredict
bool loopPredict(ThreadID tid, Addr branch_pc, bool cond_branch, BranchInfo *bi, bool prev_pred_taken, unsigned instShiftAmt)
Get the loop prediction.
Definition: loop_predictor.cc:271
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
TAGEBase::squash
virtual void squash(ThreadID tid, bool taken, BranchInfo *bi, Addr target)
Restores speculatively updated path and direction histories.
Definition: tage_base.cc:623
TAGEBase::isSpeculativeUpdateEnabled
bool isSpeculativeUpdateEnabled() const
Definition: tage_base.cc:772
LTAGE::loopPredictor
LoopPredictor * loopPredictor
The loop predictor object.
Definition: ltage.hh:76
ArmISA::b
Bitfield< 7 > b
Definition: miscregs_types.hh:376
LTAGE::LTAGE
LTAGE(const LTAGEParams *params)
Definition: ltage.cc:47
LoopPredictor::condBranchUpdate
void condBranchUpdate(ThreadID tid, Addr branch_pc, bool taken, bool tage_pred, BranchInfo *bi, unsigned instShiftAmt)
Update LTAGE for conditional branches.
Definition: loop_predictor.cc:325
SimObject::init
virtual void init()
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: sim_object.cc:73
logging.hh
TAGEBase::tagePredict
bool tagePredict(ThreadID tid, Addr branch_pc, bool cond_branch, BranchInfo *bi)
TAGE prediction called from TAGE::predict.
Definition: tage_base.cc:354
Random::random
std::enable_if< std::is_integral< T >::value, T >::type random()
Use the SFINAE idiom to choose an implementation based on whether the type is integral or floating po...
Definition: random.hh:86
RefCountingPtr< StaticInst >
trace.hh
LoopPredictor::getLoopUseCounter
int8_t getLoopUseCounter() const
Gets the value of the loop use counter.
Definition: loop_predictor.hh:245
intmath.hh
LTAGE::predict
bool predict(ThreadID tid, Addr branch_pc, bool cond_branch, void *&b) override
Get a branch prediction from LTAGE.
Definition: ltage.cc:60
LTAGE::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: ltage.cc:53

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