PowerISA Namespace Reference

Classes
class	AlignmentFault
class	BranchCond
	Base class for conditional branches. More...
class	BranchNonPCRel
	Base class for unconditional, non PC-relative branches. More...
class	BranchNonPCRelCond
	Base class for conditional, non PC-relative branches. More...
class	BranchPCRel
	Base class for unconditional, PC-relative branches. More...
class	BranchPCRelCond
	Base class for conditional, PC-relative branches. More...
class	BranchRegCond
	Base class for conditional, register-based branches. More...
class	CondLogicOp
	Class for condition register logical operations. More...
class	CondMoveOp
	Class for condition register move operations. More...
class	Decoder
class	FloatOp
	Base class for floating point operations. More...
class	Interrupts
class	IntImmOp
	Class for integer immediate (signed and unsigned) operations. More...
class	IntOp
	We provide a base class for integer operations and then inherit for several other classes. More...
class	IntRotateOp
	Class for integer rotate operations. More...
class	IntShiftOp
	Class for integer operations with a shift. More...
class	ISA
class	MachineCheckFault
class	MemDispOp
	Class for memory operations with displacement. More...
class	MemOp
	Base class for memory operations. More...
class	MiscOp
	Class for misc operations. More...
class	PCDependentDisassembly
	Base class for instructions whose disassembly is not purely a function of the machine instruction (i.e., it depends on the PC). More...
class	PowerFault
class	PowerStaticInst
struct	PTE
class	RemoteGDB
class	StackTrace
class	TLB
struct	TlbEntry
class	UnimplementedOpcodeFault

Typedefs
using	VecElem = ::DummyVecElem
using	VecReg = ::DummyVecReg
using	ConstVecReg = ::DummyConstVecReg
using	VecRegContainer = ::DummyVecRegContainer
using	VecPredReg = ::DummyVecPredReg
using	ConstVecPredReg = ::DummyConstVecPredReg
using	VecPredRegContainer = ::DummyVecPredRegContainer
typedef uint32_t	MachInst

Enumerations
enum	MiscRegIndex { NUM_MISCREGS = 0 }
enum	MiscIntRegNums {   INTREG_CR = NumIntArchRegs, INTREG_XER, INTREG_LR, INTREG_CTR,   INTREG_FPSCR, INTREG_RSV, INTREG_RSV_LEN, INTREG_RSV_ADDR }

Functions
	BitUnion32 (Cr) SubBitUnion(cr0
	EndSubBitUnion (cr0) Bitfield< 27
	EndBitUnion (Cr) BitUnion32(Xer) Bitfield< 31 > so
	EndBitUnion (Xer) BitUnion32(Fpscr) Bitfield< 31 > fx
	SubBitUnion (fprf, 16, 12) Bitfield< 16 > c
	SubBitUnion (fpcc, 15, 12) Bitfield< 15 > fl
	EndSubBitUnion (fpcc) EndSubBitUnion(fprf) Bitfield< 10 > vxsqrt
	BitUnion32 (ExtMachInst) Bitfield< 25
void	copyRegs (ThreadContext *src, ThreadContext *dest)
uint64_t	getArgument (ThreadContext *tc, int &number, uint16_t size, bool fp)
PCState	buildRetPC (const PCState &curPC, const PCState &callPC)
static void	copyMiscRegs (ThreadContext *src, ThreadContext *dest)
void	advancePC (PCState &pc, const StaticInstPtr &inst)
static bool	inUserMode (ThreadContext *tc)
uint64_t	getExecutingAsid (ThreadContext *tc)

Variables
const ByteOrder	GuestByteOrder = ByteOrder::big
const Addr	PageShift = 12
const Addr	PageBytes = ULL(1) << PageShift
const char *const	miscRegName [NUM_MISCREGS]
Bitfield< 31 >	lt
Bitfield< 30 >	gt
Bitfield< 29 >	eq
Bitfield< 28 >	so
	cr1
Bitfield< 30 >	ov
Bitfield< 29 >	ca
Bitfield< 30 >	fex
Bitfield< 29 >	vx
Bitfield< 28 >	ox
Bitfield< 27 >	ux
Bitfield< 26 >	zx
Bitfield< 25 >	xx
Bitfield< 24 >	vxsnan
Bitfield< 23 >	vxisi
Bitfield< 22 >	vxidi
Bitfield< 21 >	vxzdz
Bitfield< 20 >	vximz
Bitfield< 19 >	vxvc
Bitfield< 18 >	fr
Bitfield< 17 >	fi
Bitfield< 14 >	fg
Bitfield< 13 >	fe
Bitfield< 12 >	fu
Bitfield< 9 >	vxcvi
Bitfield< 8 >	ve
Bitfield< 7 >	oe
Bitfield< 6 >	ue
Bitfield< 5 >	ze
Bitfield< 4 >	xe
Bitfield< 3 >	ni
Bitfield< 2, 1 >	rn
const int	MaxMiscDestRegs = PowerISAInst::MaxMiscDestRegs + 1
constexpr unsigned	NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg
constexpr size_t	VecRegSizeBytes = ::DummyVecRegSizeBytes
constexpr size_t	VecPredRegSizeBits = ::DummyVecPredRegSizeBits
constexpr bool	VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr
const int	NumIntArchRegs = 32
const int	NumIntSpecialRegs = 9
const int	NumFloatArchRegs = 32
const int	NumFloatSpecialRegs = 0
const int	NumInternalProcRegs = 0
const int	NumIntRegs = NumIntArchRegs + NumIntSpecialRegs
const int	NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs
const int	NumVecRegs = 1
const int	NumVecPredRegs = 1
const int	NumCCRegs = 0
const int	NumMiscRegs = NUM_MISCREGS
const int	ReturnValueReg = 3
const int	ArgumentReg0 = 3
const int	ArgumentReg1 = 4
const int	ArgumentReg2 = 5
const int	ArgumentReg3 = 6
const int	ArgumentReg4 = 7
const int	FramePointerReg = 31
const int	StackPointerReg = 1
const int	ZeroReg = NumIntRegs - 1
const int	SyscallNumReg = 0
const int	SyscallPseudoReturnReg = 3
const int	SyscallSuccessReg = 3
	rs
Bitfield< 20, 16 >	ra
Bitfield< 15, 11 >	sh
Bitfield< 10, 6 >	mb
Bitfield< 5, 1 >	me
Bitfield< 15, 0 >	si
Bitfield< 15, 0 >	d
Bitfield< 20, 11 >	spr
Bitfield< 25, 2 >	li
Bitfield< 1 >	aa
Bitfield< 25, 23 >	bf
Bitfield< 15, 2 >	bd
Bitfield< 25, 21 >	bo
Bitfield< 20, 16 >	bi
Bitfield< 20, 18 >	bfa
Bitfield< 0 >	rc31
Bitfield< 25, 21 >	bt
Bitfield< 20, 16 >	ba
Bitfield< 15, 11 >	bb
Bitfield< 19, 12 >	fxm

Typedef Documentation

ConstVecPredReg

using PowerISA::ConstVecPredReg = typedef ::DummyConstVecPredReg

Definition at line 57 of file registers.hh.

ConstVecReg

using PowerISA::ConstVecReg = typedef ::DummyConstVecReg

Definition at line 50 of file registers.hh.

MachInst

typedef uint32_t PowerISA::MachInst

Definition at line 39 of file types.hh.

VecElem

using PowerISA::VecElem = typedef ::DummyVecElem

Definition at line 48 of file registers.hh.

VecPredReg

using PowerISA::VecPredReg = typedef ::DummyVecPredReg

Definition at line 56 of file registers.hh.

VecPredRegContainer

using PowerISA::VecPredRegContainer = typedef ::DummyVecPredRegContainer

Definition at line 58 of file registers.hh.

VecReg

using PowerISA::VecReg = typedef ::DummyVecReg

Definition at line 49 of file registers.hh.

VecRegContainer

using PowerISA::VecRegContainer = typedef ::DummyVecRegContainer

Definition at line 51 of file registers.hh.

Enumeration Type Documentation

MiscIntRegNums

enum PowerISA::MiscIntRegNums

Enumerator
INTREG_CR
INTREG_XER
INTREG_LR
INTREG_CTR
INTREG_FPSCR
INTREG_RSV
INTREG_RSV_LEN
INTREG_RSV_ADDR

Definition at line 98 of file registers.hh.

MiscRegIndex

enum PowerISA::MiscRegIndex

Enumerator
NUM_MISCREGS

Definition at line 37 of file miscregs.hh.

Function Documentation

advancePC()

void PowerISA::advancePC ( PCState &  pc, const StaticInstPtr &  inst  )

inline

Definition at line 56 of file utility.hh.

References MipsISA::pc.

BitUnion32() [1/2]

PowerISA::BitUnion32

(

Cr

)

BitUnion32() [2/2]

PowerISA::BitUnion32

(

ExtMachInst

)

buildRetPC()

PCState PowerISA::buildRetPC ( const PCState &  curPC, const PCState &  callPC  )

inline

Definition at line 41 of file utility.hh.

copyMiscRegs()

static void PowerISA::copyMiscRegs ( ThreadContext *  src, ThreadContext *  dest  )

inlinestatic

Definition at line 51 of file utility.hh.

Referenced by copyRegs().

copyRegs()

void PowerISA::copyRegs	(	ThreadContext *	src,
		ThreadContext *	dest
	)

Definition at line 38 of file utility.cc.

References copyMiscRegs(), ArmISA::i, NumCCRegs, NumFloatRegs, NumIntRegs, ThreadContext::pcState(), ThreadContext::readFloatReg(), ThreadContext::readIntReg(), ThreadContext::setFloatReg(), and ThreadContext::setIntReg().

EndBitUnion() [1/2]

PowerISA::EndBitUnion

(

Cr

)

EndBitUnion() [2/2]

PowerISA::EndBitUnion

(

Xer

)

EndSubBitUnion() [1/2]

PowerISA::EndSubBitUnion

(

cr0

)

EndSubBitUnion() [2/2]

PowerISA::EndSubBitUnion

(

fpcc

)

getArgument()

uint64_t PowerISA::getArgument	(	ThreadContext *	tc,
		int &	number,
		uint16_t	size,
		bool	fp
	)

Definition at line 59 of file utility.cc.

References panic.

getExecutingAsid()

uint64_t PowerISA::getExecutingAsid ( ThreadContext *  tc )

inline

Definition at line 70 of file utility.hh.

inUserMode()

static bool PowerISA::inUserMode ( ThreadContext *  tc )

inlinestatic

Definition at line 64 of file utility.hh.

SubBitUnion() [1/2]

PowerISA::SubBitUnion	(	fpcc	,
		15	,
		12
	)

SubBitUnion() [2/2]

PowerISA::SubBitUnion	(	fprf	,
		16	,
		12
	)

Variable Documentation

aa

Bitfield<1> PowerISA::aa

Definition at line 59 of file types.hh.

Referenced by sc_dt::sc_uint_bitref::concat_set(), sc_dt::sc_int_bitref::concat_set(), sc_dt::sc_uint_subref::concat_set(), sc_dt::sc_int_subref::concat_set(), sc_dt::sc_uint_subref::operator=(), sc_dt::sc_int_subref::operator=(), sc_dt::sc_uint_base::operator=(), sc_dt::sc_int_base::operator=(), sc_dt::sc_unsigned_subref::operator=(), sc_dt::sc_unsigned::operator=(), sc_dt::sc_signed_subref::operator=(), sc_dt::sc_signed::operator=(), sc_core::sc_inout< sc_dt::sc_biguint< W > >::operator=(), sc_core::sc_inout< sc_dt::sc_bigint< W > >::operator=(), sc_core::sc_out< sc_dt::sc_biguint< W > >::operator=(), sc_core::sc_out< sc_dt::sc_bigint< W > >::operator=(), sc_dt::sc_uint_base::to_string(), sc_dt::sc_int_base::to_string(), sc_dt::sc_unsigned::to_string(), and sc_dt::sc_signed::to_string().

ArgumentReg0

const int PowerISA::ArgumentReg0 = 3

Definition at line 83 of file registers.hh.

ArgumentReg1

const int PowerISA::ArgumentReg1 = 4

Definition at line 84 of file registers.hh.

ArgumentReg2

const int PowerISA::ArgumentReg2 = 5

Definition at line 85 of file registers.hh.

ArgumentReg3

const int PowerISA::ArgumentReg3 = 6

Definition at line 86 of file registers.hh.

ArgumentReg4

const int PowerISA::ArgumentReg4 = 7

Definition at line 87 of file registers.hh.

ba

Bitfield<20, 16> PowerISA::ba

Definition at line 72 of file types.hh.

bb

Bitfield<15, 11> PowerISA::bb

Definition at line 73 of file types.hh.

Referenced by std::hash< BasicBlockRange >::operator()().

bd

Bitfield<15, 2> PowerISA::bd

Definition at line 61 of file types.hh.

bf

Bitfield<25, 23> PowerISA::bf

Definition at line 60 of file types.hh.

Referenced by PowerISA::PowerStaticInst::insertCRField().

bfa

Bitfield<20, 18> PowerISA::bfa

Definition at line 64 of file types.hh.

bi

Bitfield<20, 16> PowerISA::bi

Definition at line 63 of file types.hh.

Referenced by sc_dt::sc_bitref< X >::b_not(), TAGEBase::baseUpdate(), TAGE::btbUpdate(), TAGEBase::btbUpdate(), TAGE_SC_L_TAGE::calcDep(), TAGE_SC_L_TAGE::calculateIndicesAndTags(), TAGEBase::calculateIndicesAndTags(), MultiperspectivePerceptron::computeOutput(), MultiperspectivePerceptronTAGE::computePartialSum(), MPP_StatisticalCorrector::condBranchUpdate(), LoopPredictor::condBranchUpdate(), StatisticalCorrector::condBranchUpdate(), TAGEBase::condBranchUpdate(), TAGE_SC_L_TAGE::extraAltCalc(), sc_dt::sc_lv_base::get_word(), MPP_StatisticalCorrector_8KB::getBiasLSUM(), MPP_StatisticalCorrector_64KB::getBiasLSUM(), TAGE_SC_L_TAGE::getBimodePred(), TAGEBase::getBimodePred(), TAGEBase::getGHR(), MPP_StatisticalCorrector::getIndBias(), StatisticalCorrector::getIndBias(), TAGE_SC_L_8KB_StatisticalCorrector::getIndBiasBank(), TAGE_SC_L_64KB_StatisticalCorrector::getIndBiasBank(), MPP_StatisticalCorrector::getIndBiasSK(), StatisticalCorrector::getIndBiasSK(), MultiperspectivePerceptronTAGE::getIndex(), MultiperspectivePerceptron::getIndex(), LoopPredictor::getLoop(), MPP_TAGE::getUseAltIdx(), TAGE_SC_L_TAGE::getUseAltIdx(), MPP_StatisticalCorrector_8KB::gPredictions(), MPP_StatisticalCorrector_64KB::gPredictions(), TAGE_SC_L_64KB_StatisticalCorrector::gPredictions(), StatisticalCorrector::gUpdate(), MPP_StatisticalCorrector_8KB::gUpdates(), MPP_StatisticalCorrector_64KB::gUpdates(), TAGE_SC_L_8KB_StatisticalCorrector::gUpdates(), TAGE_SC_L_64KB_StatisticalCorrector::gUpdates(), TAGE_SC_L_TAGE_8KB::handleAllocAndUReset(), TAGE_SC_L_TAGE_64KB::handleAllocAndUReset(), MPP_TAGE::handleAllocAndUReset(), TAGEBase::handleAllocAndUReset(), TAGE_SC_L_TAGE_8KB::handleTAGEUpdate(), TAGE_SC_L_TAGE_64KB::handleTAGEUpdate(), MPP_TAGE::handleTAGEUpdate(), TAGEBase::handleTAGEUpdate(), MPP_TAGE::isHighConfidence(), TAGE::lookup(), MultiperspectivePerceptronTAGE::lookup(), MultiperspectivePerceptron::lookup(), LoopPredictor::loopPredict(), LoopPredictor::loopUpdate(), sc_dt::scfx_rep::o_extend(), sc_dt::scfx_rep::o_set_high(), sc_dt::scfx_rep::o_zero_left(), sc_dt::scfx_rep::o_zero_right(), TAGE::predict(), LTAGE::predict(), TAGE_SC_L::predict(), sc_dt::scfx_rep::q_clear(), sc_dt::scfx_rep::q_incr(), sc_dt::quantization_scfx_rep(), sc_dt::scfx_rep::resize_to(), sc_dt::scfx_rep::round(), MPP_StatisticalCorrector_8KB::scHistoryUpdate(), MPP_StatisticalCorrector_64KB::scHistoryUpdate(), MPP_StatisticalCorrector::scPredict(), StatisticalCorrector::scPredict(), sc_dt::sc_bitref< X >::set_bit(), LoopPredictor::specLoopUpdate(), LTAGE::squash(), TAGE::squash(), MultiperspectivePerceptronTAGE::squash(), LoopPredictor::squash(), TAGEBase::squash(), MultiperspectivePerceptron::squash(), LoopPredictor::squashLoop(), TAGEBase::tagePredict(), MultiperspectivePerceptron::train(), TAGE::uncondBranch(), MultiperspectivePerceptronTAGE::uncondBranch(), MultiperspectivePerceptron::uncondBranch(), LTAGE::update(), TAGE::update(), TAGE_SC_L::update(), MultiperspectivePerceptronTAGE::update(), MultiperspectivePerceptron::update(), MultiperspectivePerceptronTAGE::updateHistories(), TAGEBase::updateHistories(), MultiperspectivePerceptronTAGE::updatePartial(), LoopPredictor::updateStats(), StatisticalCorrector::updateStats(), and TAGEBase::updateStats().

bo

Bitfield<25, 21> PowerISA::bo

Definition at line 62 of file types.hh.

Referenced by copyOutStat64Buf(), copyOutStatBuf(), copyOutStatfsBuf(), copyStringArray(), dumpDmesgEntry(), getrlimitFunc(), prlimitFunc(), and VirtQueue::VirtQueue().

bt

Bitfield<25, 21> PowerISA::bt

Definition at line 71 of file types.hh.

ca

Bitfield<29> PowerISA::ca

Definition at line 57 of file miscregs.hh.

cr1

PowerISA::cr1

Definition at line 51 of file miscregs.hh.

Referenced by SMMUv3::writeControl().

d

Bitfield<15, 0> PowerISA::d

Definition at line 54 of file types.hh.

eq

Bitfield<29> PowerISA::eq

Definition at line 48 of file miscregs.hh.

Referenced by abortHandler(), ThermalModel::doStep(), ThermalResistor::getEquation(), ThermalDomain::getEquation(), ThermalCapacitor::getEquation(), LinearSystem::operator[](), pybind_init_event(), and LinearSystem::toStr().

fe

Bitfield<13> PowerISA::fe

Definition at line 81 of file miscregs.hh.

fex

Bitfield<30> PowerISA::fex

Definition at line 62 of file miscregs.hh.

fg

Bitfield<14> PowerISA::fg

Definition at line 80 of file miscregs.hh.

fi

Bitfield<17> PowerISA::fi

Definition at line 75 of file miscregs.hh.

fr

Bitfield<18> PowerISA::fr

Definition at line 74 of file miscregs.hh.

FramePointerReg

const int PowerISA::FramePointerReg = 31

Definition at line 88 of file registers.hh.

fu

Bitfield<12> PowerISA::fu

Definition at line 82 of file miscregs.hh.

Referenced by Minor::Execute::commit(), Minor::Execute::evaluate(), Minor::Execute::Execute(), FuncUnit::FuncUnit(), FUPool::FUPool(), Minor::Execute::getCommittingThread(), and Minor::Execute::issue().

fxm

Bitfield<19, 12> PowerISA::fxm

Definition at line 76 of file types.hh.

gt

Bitfield<30> PowerISA::gt

Definition at line 47 of file miscregs.hh.

GuestByteOrder

const ByteOrder PowerISA::GuestByteOrder = ByteOrder::big

Definition at line 39 of file isa_traits.hh.

li

Bitfield<25, 2> PowerISA::li

Definition at line 58 of file types.hh.

lt

Bitfield<31> PowerISA::lt

Definition at line 45 of file miscregs.hh.

Referenced by MessageBuffer::reanalyzeList().

MaxMiscDestRegs

const int PowerISA::MaxMiscDestRegs = PowerISAInst::MaxMiscDestRegs + 1

Definition at line 45 of file registers.hh.

Referenced by BaseO3DynInst< Impl >::setMiscReg().

mb

Bitfield<10, 6> PowerISA::mb

Definition at line 49 of file types.hh.

Referenced by PowerISA::IntRotateOp::generateDisassembly().

me

Bitfield< 5, 1> PowerISA::me

Definition at line 50 of file types.hh.

Referenced by PowerISA::IntRotateOp::generateDisassembly().

miscRegName

const char* const PowerISA::miscRegName[NUM_MISCREGS]

Initial value:

= {
}

Definition at line 41 of file miscregs.hh.

ni

Bitfield<3> PowerISA::ni

Definition at line 92 of file miscregs.hh.

Referenced by TCPIface::establishConnection(), GarnetNetwork::GarnetNetwork(), and TCPIface::TCPIface().

NumCCRegs

const int PowerISA::NumCCRegs = 0

Definition at line 78 of file registers.hh.

Referenced by copyRegs().

NumFloatArchRegs

const int PowerISA::NumFloatArchRegs = 32

Definition at line 68 of file registers.hh.

Referenced by PowerISA::RemoteGDB::PowerGdbRegCache::getRegs(), and PowerISA::RemoteGDB::PowerGdbRegCache::setRegs().

NumFloatRegs

const int PowerISA::NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs

Definition at line 73 of file registers.hh.

Referenced by copyRegs().

NumFloatSpecialRegs

const int PowerISA::NumFloatSpecialRegs = 0

Definition at line 69 of file registers.hh.

NumIntArchRegs

const int PowerISA::NumIntArchRegs = 32

Definition at line 63 of file registers.hh.

Referenced by PowerISA::RemoteGDB::PowerGdbRegCache::getRegs(), and PowerISA::RemoteGDB::PowerGdbRegCache::setRegs().

NumInternalProcRegs

const int PowerISA::NumInternalProcRegs = 0

Definition at line 70 of file registers.hh.

NumIntRegs

const int PowerISA::NumIntRegs = NumIntArchRegs + NumIntSpecialRegs

Definition at line 72 of file registers.hh.

Referenced by copyRegs().

NumIntSpecialRegs

const int PowerISA::NumIntSpecialRegs = 9

Definition at line 67 of file registers.hh.

NumMiscRegs

const int PowerISA::NumMiscRegs = NUM_MISCREGS

Definition at line 79 of file registers.hh.

NumVecElemPerVecReg

constexpr unsigned PowerISA::NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg

constexpr

Definition at line 52 of file registers.hh.

NumVecPredRegs

const int PowerISA::NumVecPredRegs = 1

Definition at line 76 of file registers.hh.

NumVecRegs

const int PowerISA::NumVecRegs = 1

Definition at line 74 of file registers.hh.

oe

Bitfield< 10 > PowerISA::oe

Definition at line 88 of file miscregs.hh.

ov

Bitfield<30> PowerISA::ov

Definition at line 56 of file miscregs.hh.

ox

Bitfield<28> PowerISA::ox

Definition at line 64 of file miscregs.hh.

PageBytes

const Addr PowerISA::PageBytes = ULL(1) << PageShift

Definition at line 42 of file isa_traits.hh.

Referenced by PowerProcess::argsInit().

PageShift

const Addr PowerISA::PageShift = 12

Definition at line 41 of file isa_traits.hh.

ra

Bitfield<20, 16> PowerISA::ra

Definition at line 45 of file types.hh.

Referenced by ArmISA::FsFreebsd::initState().

rc31

Bitfield<0> PowerISA::rc31

Definition at line 67 of file types.hh.

ReturnValueReg

const int PowerISA::ReturnValueReg = 3

Definition at line 82 of file registers.hh.

Referenced by GuestABI::Result< PowerProcess::SyscallABI, SyscallReturn >::store().

rn

Bitfield<2,1> PowerISA::rn

Definition at line 93 of file miscregs.hh.

rs

PowerISA::rs

Definition at line 44 of file types.hh.

Referenced by PowerISA::IntRotateOp::rotateValue().

sh

Bitfield<15, 11> PowerISA::sh

Definition at line 48 of file types.hh.

si

Bitfield<15, 0> PowerISA::si

Definition at line 53 of file types.hh.

so

Bitfield<28> PowerISA::so

Definition at line 49 of file miscregs.hh.

Referenced by Stats::Group::regStats(), and BaseDynInst< Impl >::strictlyOrdered().

spr

Bitfield<20, 11> PowerISA::spr

Definition at line 57 of file types.hh.

StackPointerReg

const int PowerISA::StackPointerReg = 1

Definition at line 89 of file registers.hh.

SyscallNumReg

const int PowerISA::SyscallNumReg = 0

Definition at line 94 of file registers.hh.

SyscallPseudoReturnReg

const int PowerISA::SyscallPseudoReturnReg = 3

Definition at line 95 of file registers.hh.

SyscallSuccessReg

const int PowerISA::SyscallSuccessReg = 3

Definition at line 96 of file registers.hh.

ue

Bitfield<6> PowerISA::ue

Definition at line 89 of file miscregs.hh.

ux

Bitfield<27> PowerISA::ux

Definition at line 65 of file miscregs.hh.

ve

Bitfield<8> PowerISA::ve

Definition at line 87 of file miscregs.hh.

VecPredRegHasPackedRepr

constexpr bool PowerISA::VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr

constexpr

Definition at line 60 of file registers.hh.

VecPredRegSizeBits

constexpr size_t PowerISA::VecPredRegSizeBits = ::DummyVecPredRegSizeBits

constexpr

Definition at line 59 of file registers.hh.

VecRegSizeBytes

constexpr size_t PowerISA::VecRegSizeBytes = ::DummyVecRegSizeBytes

constexpr

Definition at line 53 of file registers.hh.

vx

Bitfield<29> PowerISA::vx

Definition at line 63 of file miscregs.hh.

Referenced by ArmISA::VldMultOp64::VldMultOp64(), ArmISA::VldSingleOp64::VldSingleOp64(), ArmISA::VstMultOp64::VstMultOp64(), and ArmISA::VstSingleOp64::VstSingleOp64().

vxcvi

Bitfield<9> PowerISA::vxcvi

Definition at line 86 of file miscregs.hh.

vxidi

Bitfield<22> PowerISA::vxidi

Definition at line 70 of file miscregs.hh.

vximz

Bitfield<20> PowerISA::vximz

Definition at line 72 of file miscregs.hh.

vxisi

Bitfield<23> PowerISA::vxisi

Definition at line 69 of file miscregs.hh.

vxsnan

Bitfield<24> PowerISA::vxsnan

Definition at line 68 of file miscregs.hh.

vxvc

Bitfield<19> PowerISA::vxvc

Definition at line 73 of file miscregs.hh.

vxzdz

Bitfield<21> PowerISA::vxzdz

Definition at line 71 of file miscregs.hh.

xe

Bitfield<4> PowerISA::xe

Definition at line 91 of file miscregs.hh.

Referenced by TEST_F().

xx

Bitfield<25> PowerISA::xx

Definition at line 67 of file miscregs.hh.

ze

Bitfield<5> PowerISA::ze

Definition at line 90 of file miscregs.hh.

ZeroReg

const int PowerISA::ZeroReg = NumIntRegs - 1

Definition at line 92 of file registers.hh.

zx

Bitfield<26> PowerISA::zx

Definition at line 66 of file miscregs.hh.