gem5  v20.1.0.0
pc.cc
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1 /*
2  * Copyright (c) 2008 The Regents of The University of Michigan
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28 
33 #include "dev/x86/pc.hh"
34 
35 #include <deque>
36 #include <string>
37 #include <vector>
38 
39 #include "arch/x86/intmessage.hh"
40 #include "arch/x86/x86_traits.hh"
41 #include "cpu/intr_control.hh"
42 #include "dev/x86/i82094aa.hh"
43 #include "dev/x86/i8254.hh"
44 #include "dev/x86/i8259.hh"
45 #include "dev/x86/south_bridge.hh"
46 #include "sim/system.hh"
47 
48 Pc::Pc(const Params *p)
49  : Platform(p), system(p->system)
50 {
51  southBridge = NULL;
52 }
53 
54 void
56 {
57  assert(southBridge);
58 
59  /*
60  * Initialize the timer.
61  */
62  auto &timer = *southBridge->pit;
63  //Timer 0, mode 2, no bcd, 16 bit count
64  timer.writeControl(0x34);
65  //Timer 0, latch command
66  timer.writeControl(0x00);
67  //Write a 16 bit count of 0
68  timer.writeCounter(0, 0);
69  timer.writeCounter(0, 0);
70 
71  /*
72  * Initialize the I/O APIC.
73  */
75  X86ISA::I82094AA::RedirTableEntry entry = 0;
76  entry.deliveryMode = X86ISA::DeliveryMode::ExtInt;
77  entry.vector = 0x20;
78  ioApic.writeReg(0x10, entry.bottomDW);
79  ioApic.writeReg(0x11, entry.topDW);
80  entry.deliveryMode = X86ISA::DeliveryMode::Fixed;
81  entry.vector = 0x24;
82  ioApic.writeReg(0x18, entry.bottomDW);
83  ioApic.writeReg(0x19, entry.topDW);
84  entry.mask = 1;
85  entry.vector = 0x21;
86  ioApic.writeReg(0x12, entry.bottomDW);
87  ioApic.writeReg(0x13, entry.topDW);
88  entry.vector = 0x20;
89  ioApic.writeReg(0x14, entry.bottomDW);
90  ioApic.writeReg(0x15, entry.topDW);
91  entry.vector = 0x28;
92  ioApic.writeReg(0x20, entry.bottomDW);
93  ioApic.writeReg(0x21, entry.topDW);
94  entry.vector = 0x2C;
95  ioApic.writeReg(0x28, entry.bottomDW);
96  ioApic.writeReg(0x29, entry.topDW);
97  entry.vector = 0x2E;
98  ioApic.writeReg(0x2C, entry.bottomDW);
99  ioApic.writeReg(0x2D, entry.topDW);
100  entry.vector = 0x30;
101  ioApic.writeReg(0x30, entry.bottomDW);
102  ioApic.writeReg(0x31, entry.topDW);
103 
104  /*
105  * Mask the PICs. I'm presuming the BIOS/bootloader would have cleared
106  * these out and masked them before passing control to the OS.
107  */
110 }
111 
112 void
114 {
117 }
118 
119 void
121 {
122  warn_once("Don't know what interrupt to clear for console.\n");
123  //panic("Need implementation\n");
124 }
125 
126 void
127 Pc::postPciInt(int line)
128 {
130 }
131 
132 void
134 {
135  warn_once("Tried to clear PCI interrupt %d\n", line);
136 }
137 
138 Pc *
139 PcParams::create()
140 {
141  return new Pc(this);
142 }
x86_traits.hh
system.hh
south_bridge.hh
SouthBridge::pic1
X86ISA::I8259 * pic1
Definition: south_bridge.hh:51
warn_once
#define warn_once(...)
Definition: logging.hh:243
Pc::Pc
Pc(const Params *p)
Definition: pc.cc:48
intmessage.hh
Pc::init
void init() override
Do platform initialization stuff.
Definition: pc.cc:55
Pc::postConsoleInt
void postConsoleInt() override
Cause the cpu to post a serial interrupt to the CPU.
Definition: pc.cc:113
X86ISA::system
Bitfield< 15 > system
Definition: misc.hh:997
X86ISA::I82094AA::writeReg
void writeReg(uint8_t offset, uint32_t value)
Definition: i82094aa.cc:129
pc.hh
i82094aa.hh
X86ISA::I8254::writeControl
void writeControl(uint8_t val)
Definition: i8254.hh:117
Pc::clearPciInt
void clearPciInt(int line) override
Clear a posted PCI->CPU interrupt.
Definition: pc.cc:133
X86ISA::I82094AA::signalInterrupt
void signalInterrupt(int line)
Definition: i82094aa.cc:179
Platform
Definition: platform.hh:49
X86ISA::I8259::maskAll
void maskAll()
Definition: i8259.hh:109
Pc::southBridge
SouthBridge * southBridge
Definition: pc.hh:50
Pc
Definition: pc.hh:45
Platform::Params
PlatformParams Params
Definition: platform.hh:56
SouthBridge::ioApic
X86ISA::I82094AA * ioApic
Definition: south_bridge.hh:55
Pc::postPciInt
void postPciInt(int line) override
Cause the chipset to post a cpi interrupt to the CPU.
Definition: pc.cc:127
X86ISA::I8259::signalInterrupt
void signalInterrupt(int line)
Definition: i8259.cc:271
Pc::clearConsoleInt
void clearConsoleInt() override
Clear a posted CPU interrupt.
Definition: pc.cc:120
intr_control.hh
SouthBridge::pit
X86ISA::I8254 * pit
Definition: south_bridge.hh:50
X86ISA::I82094AA
Definition: i82094aa.hh:46
i8259.hh
MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:323
X86ISA::I82094AA::deliveryMode
Bitfield< 10, 8 > deliveryMode
Definition: i82094aa.hh:61
SouthBridge::pic2
X86ISA::I8259 * pic2
Definition: south_bridge.hh:52
i8254.hh

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