gem5  v20.1.0.0
i8259.cc
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1 /*
2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are
7  * met: redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer;
9  * redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution;
12  * neither the name of the copyright holders nor the names of its
13  * contributors may be used to endorse or promote products derived from
14  * this software without specific prior written permission.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  */
28 
29 #include "dev/x86/i8259.hh"
30 
31 #include "base/bitfield.hh"
32 #include "base/trace.hh"
33 #include "debug/I8259.hh"
34 #include "dev/x86/i82094aa.hh"
35 #include "mem/packet.hh"
36 #include "mem/packet_access.hh"
37 
39  : BasicPioDevice(p, 2),
40  latency(p->pio_latency),
41  mode(p->mode), slave(p->slave),
42  IRR(0), ISR(0), IMR(0),
43  readIRR(true), initControlWord(0), autoEOI(false)
44 {
45  for (int i = 0; i < p->port_output_connection_count; i++) {
46  output.push_back(new IntSourcePin<I8259>(
47  csprintf("%s.output[%d]", name(), i), i, this));
48  }
49 
50  int in_count = p->port_inputs_connection_count;
51  panic_if(in_count >= NumLines,
52  "I8259 only supports 8 inputs, but there are %d.", in_count);
53  for (int i = 0; i < in_count; i++) {
54  inputs.push_back(new IntSinkPin<I8259>(
55  csprintf("%s.inputs[%d]", name(), i), i, this));
56  }
57 
58  for (bool &state: pinStates)
59  state = false;
60 }
61 
62 void
64 {
66 
67  for (auto *input: inputs)
68  pinStates[input->getId()] = input->state();
69 }
70 
71 Tick
73 {
74  assert(pkt->getSize() == 1);
75  switch(pkt->getAddr() - pioAddr)
76  {
77  case 0x0:
78  if (readIRR) {
79  DPRINTF(I8259, "Reading IRR as %#x.\n", IRR);
80  pkt->setLE(IRR);
81  } else {
82  DPRINTF(I8259, "Reading ISR as %#x.\n", ISR);
83  pkt->setLE(ISR);
84  }
85  break;
86  case 0x1:
87  DPRINTF(I8259, "Reading IMR as %#x.\n", IMR);
88  pkt->setLE(IMR);
89  break;
90  }
91  pkt->makeAtomicResponse();
92  return latency;
93 }
94 
95 Tick
97 {
98  assert(pkt->getSize() == 1);
99  uint8_t val = pkt->getLE<uint8_t>();
100  switch (pkt->getAddr() - pioAddr) {
101  case 0x0:
102  if (bits(val, 4)) {
103  DPRINTF(I8259, "Received initialization command word 1.\n");
104  IMR = 0;
105  edgeTriggered = bits(val, 3);
106  DPRINTF(I8259, "%s triggered mode.\n",
107  edgeTriggered ? "Edge" : "Level");
108  cascadeMode = !bits(val, 1);
109  DPRINTF(I8259, "%s mode.\n",
110  cascadeMode ? "Cascade" : "Single");
111  expectICW4 = bits(val, 0);
112  if (!expectICW4) {
113  autoEOI = false;
114  }
115  initControlWord = 1;
116  DPRINTF(I8259, "Expecting %d more bytes.\n", expectICW4 ? 3 : 2);
117  } else if (bits(val, 4, 3) == 0) {
118  DPRINTF(I8259, "Received operation command word 2.\n");
119  switch (bits(val, 7, 5)) {
120  case 0x0:
121  DPRINTF(I8259,
122  "Subcommand: Rotate in auto-EOI mode (clear).\n");
123  break;
124  case 0x1:
125  {
126  int line = findMsbSet(ISR);
127  DPRINTF(I8259, "Subcommand: Nonspecific EOI on line %d.\n",
128  line);
129  handleEOI(line);
130  }
131  break;
132  case 0x2:
133  DPRINTF(I8259, "Subcommand: No operation.\n");
134  break;
135  case 0x3:
136  {
137  int line = bits(val, 2, 0);
138  DPRINTF(I8259, "Subcommand: Specific EIO on line %d.\n",
139  line);
140  handleEOI(line);
141  }
142  break;
143  case 0x4:
144  DPRINTF(I8259, "Subcommand: Rotate in auto-EOI mode (set).\n");
145  break;
146  case 0x5:
147  DPRINTF(I8259, "Subcommand: Rotate on nonspecific EOI.\n");
148  break;
149  case 0x6:
150  DPRINTF(I8259, "Subcommand: Set priority command.\n");
151  DPRINTF(I8259, "Lowest: IRQ%d Highest IRQ%d.\n",
152  bits(val, 2, 0), (bits(val, 2, 0) + 1) % 8);
153  break;
154  case 0x7:
155  DPRINTF(I8259, "Subcommand: Rotate on specific EOI.\n");
156  DPRINTF(I8259, "Lowest: IRQ%d Highest IRQ%d.\n",
157  bits(val, 2, 0), (bits(val, 2, 0) + 1) % 8);
158  break;
159  }
160  } else if (bits(val, 4, 3) == 1) {
161  DPRINTF(I8259, "Received operation command word 3.\n");
162  if (bits(val, 7)) {
163  DPRINTF(I8259, "%s special mask mode.\n",
164  bits(val, 6) ? "Set" : "Clear");
165  }
166  if (bits(val, 1)) {
167  readIRR = bits(val, 0);
168  DPRINTF(I8259, "Read %s.\n", readIRR ? "IRR" : "ISR");
169  }
170  }
171  break;
172  case 0x1:
173  switch (initControlWord) {
174  case 0x0:
175  DPRINTF(I8259, "Received operation command word 1.\n");
176  DPRINTF(I8259, "Wrote IMR value %#x.\n", val);
177  IMR = val;
178  break;
179  case 0x1:
180  DPRINTF(I8259, "Received initialization command word 2.\n");
181  vectorOffset = val & ~mask(3);
182  DPRINTF(I8259, "Responsible for vectors %#x-%#x.\n",
183  vectorOffset, vectorOffset | mask(3));
184  if (cascadeMode) {
185  initControlWord++;
186  } else {
187  cascadeBits = 0;
188  initControlWord = 0;
189  }
190  break;
191  case 0x2:
192  DPRINTF(I8259, "Received initialization command word 3.\n");
193  if (mode == Enums::I8259Master) {
194  DPRINTF(I8259, "Responders attached to "
195  "IRQs:%s%s%s%s%s%s%s%s\n",
196  bits(val, 0) ? " 0" : "",
197  bits(val, 1) ? " 1" : "",
198  bits(val, 2) ? " 2" : "",
199  bits(val, 3) ? " 3" : "",
200  bits(val, 4) ? " 4" : "",
201  bits(val, 5) ? " 5" : "",
202  bits(val, 6) ? " 6" : "",
203  bits(val, 7) ? " 7" : "");
204  cascadeBits = val;
205  } else {
206  DPRINTF(I8259, "Responder ID is %d.\n", val & mask(3));
207  cascadeBits = val & mask(3);
208  }
209  if (expectICW4)
210  initControlWord++;
211  else
212  initControlWord = 0;
213  break;
214  case 0x3:
215  DPRINTF(I8259, "Received initialization command word 4.\n");
216  if (bits(val, 4)) {
217  DPRINTF(I8259, "Special fully nested mode.\n");
218  } else {
219  DPRINTF(I8259, "Not special fully nested mode.\n");
220  }
221  if (bits(val, 3) == 0) {
222  DPRINTF(I8259, "Nonbuffered.\n");
223  } else if (bits(val, 2) == 0) {
224  DPRINTF(I8259, "Buffered.\n");
225  } else {
226  DPRINTF(I8259, "Unrecognized buffer mode.\n");
227  }
228  autoEOI = bits(val, 1);
229  DPRINTF(I8259, "%s End Of Interrupt.\n",
230  autoEOI ? "Automatic" : "Normal");
231 
232  DPRINTF(I8259, "%s mode.\n", bits(val, 0) ? "80x86" : "MCX-80/85");
233  initControlWord = 0;
234  break;
235  }
236  break;
237  }
238  pkt->makeAtomicResponse();
239  return latency;
240 }
241 
242 void
244 {
245  ISR &= ~(1 << line);
246  // There may be an interrupt that was waiting which can
247  // now be sent.
248  if (IRR)
249  requestInterrupt(findMsbSet(IRR));
250 }
251 
252 void
254 {
255  if (bits(ISR, 7, line) == 0) {
256  if (!output.empty()) {
257  DPRINTF(I8259, "Propogating interrupt.\n");
258  for (auto *wire: output) {
259  wire->raise();
260  //XXX This is a hack.
261  wire->lower();
262  }
263  } else {
264  warn("Received interrupt but didn't have "
265  "anyone to tell about it.\n");
266  }
267  }
268 }
269 
270 void
272 {
273  DPRINTF(I8259, "Interrupt requested for line %d.\n", line);
274  if (line >= NumLines)
275  fatal("Line number %d doesn't exist. The max is %d.\n",
276  line, NumLines - 1);
277  if (bits(IMR, line)) {
278  DPRINTF(I8259, "Interrupt %d was masked.\n", line);
279  } else {
280  IRR |= 1 << line;
281  requestInterrupt(line);
282  }
283 }
284 
285 void
287 {
288  DPRINTF(I8259, "Interrupt signal raised for pin %d.\n", number);
289  if (number >= NumLines)
290  fatal("Line number %d doesn't exist. The max is %d.\n",
291  number, NumLines - 1);
292  if (!pinStates[number])
293  signalInterrupt(number);
294  pinStates[number] = true;
295 }
296 
297 void
299 {
300  DPRINTF(I8259, "Interrupt signal lowered for pin %d.\n", number);
301  if (number >= NumLines)
302  fatal("Line number %d doesn't exist. The max is %d.\n",
303  number, NumLines - 1);
304  pinStates[number] = false;
305 }
306 
307 int
309 {
310  /*
311  * This code only handles one responder. Since that's how the PC platform
312  * always uses the 8259 PIC, there shouldn't be any need for more. If
313  * there -is- a need for more for some reason, "responder" can become a
314  * vector of responders.
315  */
316  int line = findMsbSet(IRR);
317  IRR &= ~(1 << line);
318  DPRINTF(I8259, "Interrupt %d was accepted.\n", line);
319  if (autoEOI) {
320  handleEOI(line);
321  } else {
322  ISR |= 1 << line;
323  }
324  if (slave && bits(cascadeBits, line)) {
325  DPRINTF(I8259, "Interrupt was from responder who will "
326  "provide the vector.\n");
327  return slave->getVector();
328  }
329  return line | vectorOffset;
330 }
331 
332 void
334 {
335  SERIALIZE_ARRAY(pinStates, NumLines);
337  SERIALIZE_SCALAR(IRR);
340  SERIALIZE_SCALAR(vectorOffset);
341  SERIALIZE_SCALAR(cascadeMode);
342  SERIALIZE_SCALAR(cascadeBits);
343  SERIALIZE_SCALAR(edgeTriggered);
344  SERIALIZE_SCALAR(readIRR);
345  SERIALIZE_SCALAR(expectICW4);
346  SERIALIZE_SCALAR(initControlWord);
347  SERIALIZE_SCALAR(autoEOI);
348 }
349 
350 void
352 {
353  UNSERIALIZE_ARRAY(pinStates, NumLines);
355  UNSERIALIZE_SCALAR(IRR);
358  UNSERIALIZE_SCALAR(vectorOffset);
359  UNSERIALIZE_SCALAR(cascadeMode);
360  UNSERIALIZE_SCALAR(cascadeBits);
361  UNSERIALIZE_SCALAR(edgeTriggered);
362  UNSERIALIZE_SCALAR(readIRR);
363  UNSERIALIZE_SCALAR(expectICW4);
364  UNSERIALIZE_SCALAR(initControlWord);
365  UNSERIALIZE_SCALAR(autoEOI);
366 }
367 
369 I8259Params::create()
370 {
371  return new X86ISA::I8259(this);
372 }
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:183
X86ISA::I8259::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: i8259.cc:351
output
static void output(const char *filename)
Definition: debug.cc:60
Packet::makeAtomicResponse
void makeAtomicResponse()
Definition: packet.hh:1016
X86ISA::I8259::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: i8259.cc:333
warn
#define warn(...)
Definition: logging.hh:239
UNSERIALIZE_SCALAR
#define UNSERIALIZE_SCALAR(scalar)
Definition: serialize.hh:797
Packet::getAddr
Addr getAddr() const
Definition: packet.hh:754
PioDevice::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: io_device.cc:56
ArmISA::i
Bitfield< 7 > i
Definition: miscregs_types.hh:63
findMsbSet
int findMsbSet(uint64_t val)
Returns the bit position of the MSB that is set in the input.
Definition: bitfield.hh:234
IntSourcePin
Definition: intpin.hh:109
X86ISA::I8259
Definition: i8259.hh:40
X86ISA::I8259::NumLines
static const int NumLines
Definition: i8259.hh:43
X86ISA::I8259::I8259
I8259(Params *p)
Definition: i8259.cc:38
Tick
uint64_t Tick
Tick count type.
Definition: types.hh:63
X86ISA::I8259::raiseInterruptPin
void raiseInterruptPin(int number)
Definition: i8259.cc:286
Packet::getSize
unsigned getSize() const
Definition: packet.hh:764
X86ISA::I8259::pinStates
bool pinStates[NumLines]
Definition: i8259.hh:44
packet.hh
SERIALIZE_ENUM
#define SERIALIZE_ENUM(scalar)
Definition: serialize.hh:813
X86ISA::I8259::requestInterrupt
void requestInterrupt(int line)
Definition: i8259.cc:253
cp
Definition: cprintf.cc:40
X86ISA::I8259::read
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: i8259.cc:72
bitfield.hh
X86ISA::I8259::write
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: i8259.cc:96
i82094aa.hh
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:234
PioDevice::Params
PioDeviceParams Params
Definition: io_device.hh:131
ArmISA::mode
Bitfield< 4, 0 > mode
Definition: miscregs_types.hh:70
IntSinkPin
Definition: intpin.hh:75
ISR
@ ISR
Definition: ns_gige_reg.h:43
SERIALIZE_ARRAY
#define SERIALIZE_ARRAY(member, size)
Definition: serialize.hh:832
X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
X86ISA::I8259::getVector
int getVector()
Definition: i8259.cc:308
SERIALIZE_SCALAR
#define SERIALIZE_SCALAR(scalar)
Definition: serialize.hh:790
packet_access.hh
X86ISA::I8259::inputs
std::vector< IntSinkPin< I8259 > * > inputs
Definition: i8259.hh:50
SimObject::name
virtual const std::string name() const
Definition: sim_object.hh:133
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:197
Packet::getLE
T getLE() const
Get the data in the packet byte swapped from little endian to host endian.
Definition: packet_access.hh:75
X86ISA::I8259::signalInterrupt
void signalInterrupt(int line)
Definition: i8259.cc:271
X86ISA::p
Bitfield< 0 > p
Definition: pagetable.hh:151
UNSERIALIZE_ARRAY
#define UNSERIALIZE_ARRAY(member, size)
Definition: serialize.hh:840
X86ISA::I8259::output
std::vector< IntSourcePin< I8259 > * > output
Definition: i8259.hh:49
Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:257
IMR
@ IMR
Definition: ns_gige_reg.h:44
BasicPioDevice
Definition: io_device.hh:150
X86ISA::I8259::lowerInterruptPin
void lowerInterruptPin(int number)
Definition: i8259.cc:298
i8259.hh
Packet::setLE
void setLE(T v)
Set the value in the data pointer to v as little endian.
Definition: packet_access.hh:105
CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:63
X86ISA::mask
mask
Definition: misc.hh:796
UNSERIALIZE_ENUM
#define UNSERIALIZE_ENUM(scalar)
Definition: serialize.hh:820
trace.hh
X86ISA::I8259::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: i8259.cc:63
MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:323
CheckpointIn
Definition: serialize.hh:67
X86ISA::I8259::handleEOI
void handleEOI(int line)
Definition: i8259.cc:243
csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:158
bits
T bits(T val, int first, int last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:75

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