gem5  v20.1.0.0
i8254xGBe_defs.hh
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1 /*
2  * Copyright (c) 2006 The Regents of The University of Michigan
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are
7  * met: redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer;
9  * redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution;
12  * neither the name of the copyright holders nor the names of its
13  * contributors may be used to endorse or promote products derived from
14  * this software without specific prior written permission.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  */
28 
29 /* @file
30  * Register and structure descriptions for Intel's 8254x line of gigabit ethernet controllers.
31  */
32 #include "base/bitfield.hh"
33 
34 namespace iGbReg {
35 
36 
37 // Registers used by the Intel GbE NIC
38 const uint32_t REG_CTRL = 0x00000;
39 const uint32_t REG_STATUS = 0x00008;
40 const uint32_t REG_EECD = 0x00010;
41 const uint32_t REG_EERD = 0x00014;
42 const uint32_t REG_CTRL_EXT = 0x00018;
43 const uint32_t REG_MDIC = 0x00020;
44 const uint32_t REG_FCAL = 0x00028;
45 const uint32_t REG_FCAH = 0x0002C;
46 const uint32_t REG_FCT = 0x00030;
47 const uint32_t REG_VET = 0x00038;
48 const uint32_t REG_PBA = 0x01000;
49 const uint32_t REG_ICR = 0x000C0;
50 const uint32_t REG_ITR = 0x000C4;
51 const uint32_t REG_ICS = 0x000C8;
52 const uint32_t REG_IMS = 0x000D0;
53 const uint32_t REG_IMC = 0x000D8;
54 const uint32_t REG_IAM = 0x000E0;
55 const uint32_t REG_RCTL = 0x00100;
56 const uint32_t REG_FCTTV = 0x00170;
57 const uint32_t REG_TIPG = 0x00410;
58 const uint32_t REG_AIFS = 0x00458;
59 const uint32_t REG_LEDCTL = 0x00e00;
60 const uint32_t REG_EICR = 0x01580;
61 const uint32_t REG_IVAR0 = 0x01700;
62 const uint32_t REG_FCRTL = 0x02160;
63 const uint32_t REG_FCRTH = 0x02168;
64 const uint32_t REG_RDBAL = 0x02800;
65 const uint32_t REG_RDBAH = 0x02804;
66 const uint32_t REG_RDLEN = 0x02808;
67 const uint32_t REG_SRRCTL = 0x0280C;
68 const uint32_t REG_RDH = 0x02810;
69 const uint32_t REG_RDT = 0x02818;
70 const uint32_t REG_RDTR = 0x02820;
71 const uint32_t REG_RXDCTL = 0x02828;
72 const uint32_t REG_RADV = 0x0282C;
73 const uint32_t REG_TCTL = 0x00400;
74 const uint32_t REG_TDBAL = 0x03800;
75 const uint32_t REG_TDBAH = 0x03804;
76 const uint32_t REG_TDLEN = 0x03808;
77 const uint32_t REG_TDH = 0x03810;
78 const uint32_t REG_TXDCA_CTL = 0x03814;
79 const uint32_t REG_TDT = 0x03818;
80 const uint32_t REG_TIDV = 0x03820;
81 const uint32_t REG_TXDCTL = 0x03828;
82 const uint32_t REG_TADV = 0x0382C;
83 const uint32_t REG_TDWBAL = 0x03838;
84 const uint32_t REG_TDWBAH = 0x0383C;
85 const uint32_t REG_CRCERRS = 0x04000;
86 const uint32_t REG_RXCSUM = 0x05000;
87 const uint32_t REG_RLPML = 0x05004;
88 const uint32_t REG_RFCTL = 0x05008;
89 const uint32_t REG_MTA = 0x05200;
90 const uint32_t REG_RAL = 0x05400;
91 const uint32_t REG_RAH = 0x05404;
92 const uint32_t REG_VFTA = 0x05600;
93 
94 const uint32_t REG_WUC = 0x05800;
95 const uint32_t REG_WUFC = 0x05808;
96 const uint32_t REG_WUS = 0x05810;
97 const uint32_t REG_MANC = 0x05820;
98 const uint32_t REG_SWSM = 0x05B50;
99 const uint32_t REG_FWSM = 0x05B54;
100 const uint32_t REG_SWFWSYNC = 0x05B5C;
101 
102 const uint8_t EEPROM_READ_OPCODE_SPI = 0x03;
103 const uint8_t EEPROM_RDSR_OPCODE_SPI = 0x05;
104 const uint8_t EEPROM_SIZE = 64;
105 const uint16_t EEPROM_CSUM = 0xBABA;
106 
107 const uint8_t VLAN_FILTER_TABLE_SIZE = 128;
108 const uint8_t RCV_ADDRESS_TABLE_SIZE = 24;
109 const uint8_t MULTICAST_TABLE_SIZE = 128;
110 const uint32_t STATS_REGS_SIZE = 0x228;
111 
112 
113 // Registers in that are accessed in the PHY
114 const uint8_t PHY_PSTATUS = 0x1;
115 const uint8_t PHY_PID = 0x2;
116 const uint8_t PHY_EPID = 0x3;
117 const uint8_t PHY_GSTATUS = 10;
118 const uint8_t PHY_EPSTATUS = 15;
119 const uint8_t PHY_AGC = 18;
120 
121 // Receive Descriptor Status Flags
122 const uint16_t RXDS_DYNINT = 0x800;
123 const uint16_t RXDS_UDPV = 0x400;
124 const uint16_t RXDS_CRCV = 0x100;
125 const uint16_t RXDS_PIF = 0x080;
126 const uint16_t RXDS_IPCS = 0x040;
127 const uint16_t RXDS_TCPCS = 0x020;
128 const uint16_t RXDS_UDPCS = 0x010;
129 const uint16_t RXDS_VP = 0x008;
130 const uint16_t RXDS_IXSM = 0x004;
131 const uint16_t RXDS_EOP = 0x002;
132 const uint16_t RXDS_DD = 0x001;
133 
134 // Receive Descriptor Error Flags
135 const uint8_t RXDE_RXE = 0x80;
136 const uint8_t RXDE_IPE = 0x40;
137 const uint8_t RXDE_TCPE = 0x20;
138 const uint8_t RXDE_SEQ = 0x04;
139 const uint8_t RXDE_SE = 0x02;
140 const uint8_t RXDE_CE = 0x01;
141 
142 // Receive Descriptor Extended Error Flags
143 const uint16_t RXDEE_HBO = 0x008;
144 const uint16_t RXDEE_CE = 0x010;
145 const uint16_t RXDEE_LE = 0x020;
146 const uint16_t RXDEE_PE = 0x080;
147 const uint16_t RXDEE_OSE = 0x100;
148 const uint16_t RXDEE_USE = 0x200;
149 const uint16_t RXDEE_TCPE = 0x400;
150 const uint16_t RXDEE_IPE = 0x800;
151 
152 
153 // Receive Descriptor Types
154 const uint8_t RXDT_LEGACY = 0x00;
155 const uint8_t RXDT_ADV_ONEBUF = 0x01;
156 const uint8_t RXDT_ADV_SPLIT_A = 0x05;
157 
158 // Receive Descriptor Packet Types
159 const uint16_t RXDP_IPV4 = 0x001;
160 const uint16_t RXDP_IPV4E = 0x002;
161 const uint16_t RXDP_IPV6 = 0x004;
162 const uint16_t RXDP_IPV6E = 0x008;
163 const uint16_t RXDP_TCP = 0x010;
164 const uint16_t RXDP_UDP = 0x020;
165 const uint16_t RXDP_SCTP = 0x040;
166 const uint16_t RXDP_NFS = 0x080;
167 
168 // Interrupt types
170 {
171  IT_NONE = 0x00000, //dummy value
172  IT_TXDW = 0x00001,
173  IT_TXQE = 0x00002,
174  IT_LSC = 0x00004,
175  IT_RXSEQ = 0x00008,
176  IT_RXDMT = 0x00010,
177  IT_RXO = 0x00040,
178  IT_RXT = 0x00080,
179  IT_MADC = 0x00200,
180  IT_RXCFG = 0x00400,
181  IT_GPI0 = 0x02000,
182  IT_GPI1 = 0x04000,
183  IT_TXDLOW = 0x08000,
184  IT_SRPD = 0x10000,
185  IT_ACK = 0x20000
186 };
187 
188 // Receive Descriptor struct
189 struct RxDesc {
190  union {
191  struct {
193  uint16_t len;
194  uint16_t csum;
195  uint8_t status;
196  uint8_t errors;
197  uint16_t vlan;
198  } legacy;
199  struct {
202  } adv_read;
203  struct {
204  uint16_t rss_type:4;
205  uint16_t pkt_type:12;
206  uint16_t __reserved1:5;
207  uint16_t header_len:10;
208  uint16_t sph:1;
209  union {
210  struct {
211  uint16_t id;
212  uint16_t csum;
213  };
214  uint32_t rss_hash;
215  };
216  uint32_t status:20;
217  uint32_t errors:12;
218  uint16_t pkt_len;
219  uint16_t vlan_tag;
220  } adv_wb ;
221  };
222 };
223 
224 struct TxDesc {
225  uint64_t d1;
226  uint64_t d2;
227 };
228 
229 namespace TxdOp {
230 const uint8_t TXD_CNXT = 0x0;
231 const uint8_t TXD_DATA = 0x1;
232 const uint8_t TXD_ADVCNXT = 0x2;
233 const uint8_t TXD_ADVDATA = 0x3;
234 
235 inline bool isLegacy(TxDesc *d) { return !bits(d->d2,29,29); }
236 inline uint8_t getType(TxDesc *d) { return bits(d->d2, 23,20); }
237 inline bool isType(TxDesc *d, uint8_t type) { return getType(d) == type; }
238 inline bool isTypes(TxDesc *d, uint8_t t1, uint8_t t2) { return isType(d, t1) || isType(d, t2); }
239 inline bool isAdvDesc(TxDesc *d) { return !isLegacy(d) && isTypes(d, TXD_ADVDATA,TXD_ADVCNXT); }
240 inline bool isContext(TxDesc *d) { return !isLegacy(d) && isTypes(d,TXD_CNXT, TXD_ADVCNXT); }
241 inline bool isData(TxDesc *d) { return !isLegacy(d) && isTypes(d, TXD_DATA, TXD_ADVDATA); }
242 
243 inline Addr getBuf(TxDesc *d) { assert(isLegacy(d) || isData(d)); return d->d1; }
244 inline Addr getLen(TxDesc *d) { if (isLegacy(d)) return bits(d->d2,15,0); else return bits(d->d2, 19,0); }
245 inline void setDd(TxDesc *d) { replaceBits(d->d2, 35, 32, ULL(1)); }
246 
247 inline bool ide(TxDesc *d) { return bits(d->d2, 31,31) && (getType(d) == TXD_DATA || isLegacy(d)); }
248 inline bool vle(TxDesc *d) { assert(isLegacy(d) || isData(d)); return bits(d->d2, 30,30); }
249 inline bool rs(TxDesc *d) { return bits(d->d2, 27,27); }
250 inline bool ic(TxDesc *d) { assert(isLegacy(d) || isData(d)); return isLegacy(d) && bits(d->d2, 26,26); }
251 inline bool tse(TxDesc *d) {
252  if (isTypes(d, TXD_CNXT, TXD_DATA))
253  return bits(d->d2, 26,26);
254  if (isType(d, TXD_ADVDATA))
255  return bits(d->d2, 31, 31);
256  return false;
257 }
258 
259 inline bool ifcs(TxDesc *d) { assert(isLegacy(d) || isData(d)); return bits(d->d2, 25,25); }
260 inline bool eop(TxDesc *d) { assert(isLegacy(d) || isData(d)); return bits(d->d2, 24,24); }
261 inline bool ip(TxDesc *d) { assert(isContext(d)); return bits(d->d2, 25,25); }
262 inline bool tcp(TxDesc *d) { assert(isContext(d)); return bits(d->d2, 24,24); }
263 
264 inline uint8_t getCso(TxDesc *d) { assert(isLegacy(d)); return bits(d->d2, 23,16); }
265 inline uint8_t getCss(TxDesc *d) { assert(isLegacy(d)); return bits(d->d2, 47,40); }
266 
267 inline bool ixsm(TxDesc *d) { return isData(d) && bits(d->d2, 40,40); }
268 inline bool txsm(TxDesc *d) { return isData(d) && bits(d->d2, 41,41); }
269 
270 inline int tucse(TxDesc *d) { assert(isContext(d)); return bits(d->d1,63,48); }
271 inline int tucso(TxDesc *d) { assert(isContext(d)); return bits(d->d1,47,40); }
272 inline int tucss(TxDesc *d) { assert(isContext(d)); return bits(d->d1,39,32); }
273 inline int ipcse(TxDesc *d) { assert(isContext(d)); return bits(d->d1,31,16); }
274 inline int ipcso(TxDesc *d) { assert(isContext(d)); return bits(d->d1,15,8); }
275 inline int ipcss(TxDesc *d) { assert(isContext(d)); return bits(d->d1,7,0); }
276 inline int mss(TxDesc *d) { assert(isContext(d)); return bits(d->d2,63,48); }
277 inline int hdrlen(TxDesc *d) {
278  assert(isContext(d));
279  if (!isAdvDesc(d))
280  return bits(d->d2,47,40);
281  return bits(d->d2, 47,40) + bits(d->d1, 8,0) + bits(d->d1, 15, 9);
282 }
283 
284 inline int getTsoLen(TxDesc *d) { assert(isType(d, TXD_ADVDATA)); return bits(d->d2, 63,46); }
285 inline int utcmd(TxDesc *d) { assert(isContext(d)); return bits(d->d2,24,31); }
286 } // namespace TxdOp
287 
288 
289 #define ADD_FIELD32(NAME, OFFSET, BITS) \
290  inline uint32_t NAME() { return bits(_data, OFFSET+BITS-1, OFFSET); } \
291  inline void NAME(uint32_t d) { replaceBits(_data, OFFSET+BITS-1, OFFSET,d); }
292 
293 #define ADD_FIELD64(NAME, OFFSET, BITS) \
294  inline uint64_t NAME() { return bits(_data, OFFSET+BITS-1, OFFSET); } \
295  inline void NAME(uint64_t d) { replaceBits(_data, OFFSET+BITS-1, OFFSET,d); }
296 
297 struct Regs : public Serializable {
298  template<class T>
299  struct Reg {
300  T _data;
301  T operator()() { return _data; }
302  const Reg<T> &operator=(T d) { _data = d; return *this;}
303  bool operator==(T d) { return d == _data; }
304  void operator()(T d) { _data = d; }
305  Reg() { _data = 0; }
307  {
309  }
311  {
313  }
314  };
315 
316  struct CTRL : public Reg<uint32_t> { // 0x0000 CTRL Register
318  ADD_FIELD32(fd,0,1); // full duplex
319  ADD_FIELD32(bem,1,1); // big endian mode
320  ADD_FIELD32(pcipr,2,1); // PCI priority
321  ADD_FIELD32(lrst,3,1); // link reset
322  ADD_FIELD32(tme,4,1); // test mode enable
323  ADD_FIELD32(asde,5,1); // Auto-speed detection
324  ADD_FIELD32(slu,6,1); // Set link up
325  ADD_FIELD32(ilos,7,1); // invert los-of-signal
326  ADD_FIELD32(speed,8,2); // speed selection bits
327  ADD_FIELD32(be32,10,1); // big endian mode 32
328  ADD_FIELD32(frcspd,11,1); // force speed
329  ADD_FIELD32(frcdpx,12,1); // force duplex
330  ADD_FIELD32(duden,13,1); // dock/undock enable
331  ADD_FIELD32(dudpol,14,1); // dock/undock polarity
332  ADD_FIELD32(fphyrst,15,1); // force phy reset
333  ADD_FIELD32(extlen,16,1); // external link status enable
334  ADD_FIELD32(rsvd,17,1); // reserved
335  ADD_FIELD32(sdp0d,18,1); // software controlled pin data
336  ADD_FIELD32(sdp1d,19,1); // software controlled pin data
337  ADD_FIELD32(sdp2d,20,1); // software controlled pin data
338  ADD_FIELD32(sdp3d,21,1); // software controlled pin data
339  ADD_FIELD32(sdp0i,22,1); // software controlled pin dir
340  ADD_FIELD32(sdp1i,23,1); // software controlled pin dir
341  ADD_FIELD32(sdp2i,24,1); // software controlled pin dir
342  ADD_FIELD32(sdp3i,25,1); // software controlled pin dir
343  ADD_FIELD32(rst,26,1); // reset
344  ADD_FIELD32(rfce,27,1); // receive flow control enable
345  ADD_FIELD32(tfce,28,1); // transmit flow control enable
346  ADD_FIELD32(rte,29,1); // routing tag enable
347  ADD_FIELD32(vme,30,1); // vlan enable
348  ADD_FIELD32(phyrst,31,1); // phy reset
349  };
351 
352  struct STATUS : public Reg<uint32_t> { // 0x0008 STATUS Register
354  ADD_FIELD32(fd,0,1); // full duplex
355  ADD_FIELD32(lu,1,1); // link up
356  ADD_FIELD32(func,2,2); // function id
357  ADD_FIELD32(txoff,4,1); // transmission paused
358  ADD_FIELD32(tbimode,5,1); // tbi mode
359  ADD_FIELD32(speed,6,2); // link speed
360  ADD_FIELD32(asdv,8,2); // auto speed detection value
361  ADD_FIELD32(mtxckok,10,1); // mtx clock running ok
362  ADD_FIELD32(pci66,11,1); // In 66Mhz pci slot
363  ADD_FIELD32(bus64,12,1); // in 64 bit slot
364  ADD_FIELD32(pcix,13,1); // Pci mode
365  ADD_FIELD32(pcixspd,14,2); // pci x speed
366  };
368 
369  struct EECD : public Reg<uint32_t> { // 0x0010 EECD Register
371  ADD_FIELD32(sk,0,1); // clack input to the eeprom
372  ADD_FIELD32(cs,1,1); // chip select to eeprom
373  ADD_FIELD32(din,2,1); // data input to eeprom
374  ADD_FIELD32(dout,3,1); // data output bit
375  ADD_FIELD32(fwe,4,2); // flash write enable
376  ADD_FIELD32(ee_req,6,1); // request eeprom access
377  ADD_FIELD32(ee_gnt,7,1); // grant eeprom access
378  ADD_FIELD32(ee_pres,8,1); // eeprom present
379  ADD_FIELD32(ee_size,9,1); // eeprom size
380  ADD_FIELD32(ee_sz1,10,1); // eeprom size
381  ADD_FIELD32(rsvd,11,2); // reserved
382  ADD_FIELD32(ee_type,13,1); // type of eeprom
383  } ;
385 
386  struct EERD : public Reg<uint32_t> { // 0x0014 EERD Register
388  ADD_FIELD32(start,0,1); // start read
389  ADD_FIELD32(done,1,1); // done read
390  ADD_FIELD32(addr,2,14); // address
391  ADD_FIELD32(data,16,16); // data
392  };
394 
395  struct CTRL_EXT : public Reg<uint32_t> { // 0x0018 CTRL_EXT Register
397  ADD_FIELD32(gpi_en,0,4); // enable interrupts from gpio
398  ADD_FIELD32(phyint,5,1); // reads the phy internal int status
399  ADD_FIELD32(sdp2_data,6,1); // data from gpio sdp
400  ADD_FIELD32(spd3_data,7,1); // data frmo gpio sdp
401  ADD_FIELD32(spd2_iodir,10,1); // direction of sdp2
402  ADD_FIELD32(spd3_iodir,11,1); // direction of sdp2
403  ADD_FIELD32(asdchk,12,1); // initiate auto-speed-detection
404  ADD_FIELD32(eerst,13,1); // reset the eeprom
405  ADD_FIELD32(spd_byps,15,1); // bypass speed select
406  ADD_FIELD32(ro_dis,17,1); // disable relaxed memory ordering
407  ADD_FIELD32(vreg,21,1); // power down the voltage regulator
408  ADD_FIELD32(link_mode,22,2); // interface to talk to the link
409  ADD_FIELD32(iame, 27,1); // interrupt acknowledge auto-mask ??
410  ADD_FIELD32(drv_loaded, 28,1);// driver is loaded and incharge of device
411  ADD_FIELD32(timer_clr, 29,1); // clear interrupt timers after IMS clear ??
412  };
414 
415  struct MDIC : public Reg<uint32_t> { // 0x0020 MDIC Register
417  ADD_FIELD32(data,0,16); // data
418  ADD_FIELD32(regadd,16,5); // register address
419  ADD_FIELD32(phyadd,21,5); // phy addresses
420  ADD_FIELD32(op,26,2); // opcode
421  ADD_FIELD32(r,28,1); // ready
422  ADD_FIELD32(i,29,1); // interrupt
423  ADD_FIELD32(e,30,1); // error
424  };
426 
427  struct ICR : public Reg<uint32_t> { // 0x00C0 ICR Register
429  ADD_FIELD32(txdw,0,1) // tx descr witten back
430  ADD_FIELD32(txqe,1,1) // tx queue empty
431  ADD_FIELD32(lsc,2,1) // link status change
432  ADD_FIELD32(rxseq,3,1) // rcv sequence error
433  ADD_FIELD32(rxdmt0,4,1) // rcv descriptor min thresh
434  ADD_FIELD32(rsvd1,5,1) // reserved
435  ADD_FIELD32(rxo,6,1) // receive overrunn
436  ADD_FIELD32(rxt0,7,1) // receiver timer interrupt
437  ADD_FIELD32(mdac,9,1) // mdi/o access complete
438  ADD_FIELD32(rxcfg,10,1) // recv /c/ ordered sets
439  ADD_FIELD32(phyint,12,1) // phy interrupt
440  ADD_FIELD32(gpi1,13,1) // gpi int 1
441  ADD_FIELD32(gpi2,14,1) // gpi int 2
442  ADD_FIELD32(txdlow,15,1) // transmit desc low thresh
443  ADD_FIELD32(srpd,16,1) // small receive packet detected
444  ADD_FIELD32(ack,17,1); // receive ack frame
445  ADD_FIELD32(int_assert, 31,1); // interrupt caused a system interrupt
446  };
448 
449  uint32_t imr; // register that contains the current interrupt mask
450 
451  struct ITR : public Reg<uint32_t> { // 0x00C4 ITR Register
453  ADD_FIELD32(interval, 0,16); // minimum inter-interrutp inteval
454  // specified in 256ns interrupts
455  };
457 
458  // When CTRL_EXT.IAME and the ICR.INT_ASSERT is 1 an ICR read or write
459  // causes the IAM register contents to be written into the IMC
460  // automatically clearing all interrupts that have a bit in the IAM set
461  uint32_t iam;
462 
463  struct RCTL : public Reg<uint32_t> { // 0x0100 RCTL Register
465  ADD_FIELD32(rst,0,1); // Reset
466  ADD_FIELD32(en,1,1); // Enable
467  ADD_FIELD32(sbp,2,1); // Store bad packets
468  ADD_FIELD32(upe,3,1); // Unicast Promiscuous enabled
469  ADD_FIELD32(mpe,4,1); // Multicast promiscuous enabled
470  ADD_FIELD32(lpe,5,1); // long packet reception enabled
471  ADD_FIELD32(lbm,6,2); //
472  ADD_FIELD32(rdmts,8,2); //
473  ADD_FIELD32(mo,12,2); //
474  ADD_FIELD32(mdr,14,1); //
475  ADD_FIELD32(bam,15,1); //
476  ADD_FIELD32(bsize,16,2); //
477  ADD_FIELD32(vfe,18,1); //
478  ADD_FIELD32(cfien,19,1); //
479  ADD_FIELD32(cfi,20,1); //
480  ADD_FIELD32(dpf,22,1); // discard pause frames
481  ADD_FIELD32(pmcf,23,1); // pass mac control frames
482  ADD_FIELD32(bsex,25,1); // buffer size extension
483  ADD_FIELD32(secrc,26,1); // strip ethernet crc from incoming packet
484  unsigned descSize()
485  {
486  switch(bsize()) {
487  case 0: return bsex() == 0 ? 2048 : 0;
488  case 1: return bsex() == 0 ? 1024 : 16384;
489  case 2: return bsex() == 0 ? 512 : 8192;
490  case 3: return bsex() == 0 ? 256 : 4096;
491  default:
492  return 0;
493  }
494  }
495  };
497 
498  struct FCTTV : public Reg<uint32_t> { // 0x0170 FCTTV
500  ADD_FIELD32(ttv,0,16); // Transmit Timer Value
501  };
503 
504  struct TCTL : public Reg<uint32_t> { // 0x0400 TCTL Register
506  ADD_FIELD32(rst,0,1); // Reset
507  ADD_FIELD32(en,1,1); // Enable
508  ADD_FIELD32(bce,2,1); // busy check enable
509  ADD_FIELD32(psp,3,1); // pad short packets
510  ADD_FIELD32(ct,4,8); // collision threshold
511  ADD_FIELD32(cold,12,10); // collision distance
512  ADD_FIELD32(swxoff,22,1); // software xoff transmission
513  ADD_FIELD32(pbe,23,1); // packet burst enable
514  ADD_FIELD32(rtlc,24,1); // retransmit late collisions
515  ADD_FIELD32(nrtu,25,1); // on underrun no TX
516  ADD_FIELD32(mulr,26,1); // multiple request
517  };
519 
520  struct PBA : public Reg<uint32_t> { // 0x1000 PBA Register
522  ADD_FIELD32(rxa,0,16);
523  ADD_FIELD32(txa,16,16);
524  };
526 
527  struct FCRTL : public Reg<uint32_t> { // 0x2160 FCRTL Register
529  ADD_FIELD32(rtl,3,28); // make this bigger than the spec so we can have
530  // a larger buffer
531  ADD_FIELD32(xone, 31,1);
532  };
534 
535  struct FCRTH : public Reg<uint32_t> { // 0x2168 FCRTL Register
537  ADD_FIELD32(rth,3,13); // make this bigger than the spec so we can have
538  //a larger buffer
539  ADD_FIELD32(xfce, 31,1);
540  };
542 
543  struct RDBA : public Reg<uint64_t> { // 0x2800 RDBA Register
545  ADD_FIELD64(rdbal,0,32); // base address of rx descriptor ring
546  ADD_FIELD64(rdbah,32,32); // base address of rx descriptor ring
547  };
549 
550  struct RDLEN : public Reg<uint32_t> { // 0x2808 RDLEN Register
552  ADD_FIELD32(len,7,13); // number of bytes in the descriptor buffer
553  };
555 
556  struct SRRCTL : public Reg<uint32_t> { // 0x280C SRRCTL Register
558  ADD_FIELD32(pktlen, 0, 8);
559  ADD_FIELD32(hdrlen, 8, 8); // guess based on header, not documented
560  ADD_FIELD32(desctype, 25,3); // type of descriptor 000 legacy, 001 adv,
561  //101 hdr split
562  unsigned bufLen() { return pktlen() << 10; }
563  unsigned hdrLen() { return hdrlen() << 6; }
564  };
566 
567  struct RDH : public Reg<uint32_t> { // 0x2810 RDH Register
569  ADD_FIELD32(rdh,0,16); // head of the descriptor ring
570  };
572 
573  struct RDT : public Reg<uint32_t> { // 0x2818 RDT Register
575  ADD_FIELD32(rdt,0,16); // tail of the descriptor ring
576  };
578 
579  struct RDTR : public Reg<uint32_t> { // 0x2820 RDTR Register
581  ADD_FIELD32(delay,0,16); // receive delay timer
582  ADD_FIELD32(fpd, 31,1); // flush partial descriptor block ??
583  };
585 
586  struct RXDCTL : public Reg<uint32_t> { // 0x2828 RXDCTL Register
588  ADD_FIELD32(pthresh,0,6); // prefetch threshold, less that this
589  // consider prefetch
590  ADD_FIELD32(hthresh,8,6); // number of descriptors in host mem to
591  // consider prefetch
592  ADD_FIELD32(wthresh,16,6); // writeback threshold
593  ADD_FIELD32(gran,24,1); // granularity 0 = desc, 1 = cacheline
594  };
596 
597  struct RADV : public Reg<uint32_t> { // 0x282C RADV Register
599  ADD_FIELD32(idv,0,16); // absolute interrupt delay
600  };
602 
603  struct RSRPD : public Reg<uint32_t> { // 0x2C00 RSRPD Register
605  ADD_FIELD32(idv,0,12); // size to interrutp on small packets
606  };
608 
609  struct TDBA : public Reg<uint64_t> { // 0x3800 TDBAL Register
611  ADD_FIELD64(tdbal,0,32); // base address of transmit descriptor ring
612  ADD_FIELD64(tdbah,32,32); // base address of transmit descriptor ring
613  };
615 
616  struct TDLEN : public Reg<uint32_t> { // 0x3808 TDLEN Register
618  ADD_FIELD32(len,7,13); // number of bytes in the descriptor buffer
619  };
621 
622  struct TDH : public Reg<uint32_t> { // 0x3810 TDH Register
624  ADD_FIELD32(tdh,0,16); // head of the descriptor ring
625  };
627 
628  struct TXDCA_CTL : public Reg<uint32_t> { // 0x3814 TXDCA_CTL Register
630  ADD_FIELD32(cpu_mask, 0, 5);
631  ADD_FIELD32(enabled, 5,1);
632  ADD_FIELD32(relax_ordering, 6, 1);
633  };
635 
636  struct TDT : public Reg<uint32_t> { // 0x3818 TDT Register
638  ADD_FIELD32(tdt,0,16); // tail of the descriptor ring
639  };
641 
642  struct TIDV : public Reg<uint32_t> { // 0x3820 TIDV Register
644  ADD_FIELD32(idv,0,16); // interrupt delay
645  };
647 
648  struct TXDCTL : public Reg<uint32_t> { // 0x3828 TXDCTL Register
650  ADD_FIELD32(pthresh, 0,6); // if number of descriptors control has is
651  // below this number, a prefetch is considered
652  ADD_FIELD32(hthresh,8,8); // number of valid descriptors is host memory
653  // before a prefetch is considered
654  ADD_FIELD32(wthresh,16,6); // number of descriptors to keep until
655  // writeback is considered
656  ADD_FIELD32(gran, 24,1); // granulatiry of above values (0 = cacheline,
657  // 1 == desscriptor)
658  ADD_FIELD32(lwthresh,25,7); // xmit descriptor low thresh, interrupt
659  // below this level
660  };
662 
663  struct TADV : public Reg<uint32_t> { // 0x382C TADV Register
665  ADD_FIELD32(idv,0,16); // absolute interrupt delay
666  };
668 /*
669  struct TDWBA : public Reg<uint64_t> { // 0x3838 TDWBA Register
670  using Reg<uint64_t>::operator=;
671  ADD_FIELD64(en,0,1); // enable transmit description ring address writeback
672  ADD_FIELD64(tdwbal,2,32); // base address of transmit descriptor ring address writeback
673  ADD_FIELD64(tdwbah,32,32); // base address of transmit descriptor ring
674  };
675  TDWBA tdwba;*/
676  uint64_t tdwba;
677 
678  struct RXCSUM : public Reg<uint32_t> { // 0x5000 RXCSUM Register
680  ADD_FIELD32(pcss,0,8);
681  ADD_FIELD32(ipofld,8,1);
682  ADD_FIELD32(tuofld,9,1);
683  ADD_FIELD32(pcsd, 13,1);
684  };
686 
687  uint32_t rlpml; // 0x5004 RLPML probably maximum accepted packet size
688 
689  struct RFCTL : public Reg<uint32_t> { // 0x5008 RFCTL Register
691  ADD_FIELD32(iscsi_dis,0,1);
692  ADD_FIELD32(iscsi_dwc,1,5);
693  ADD_FIELD32(nfsw_dis,6,1);
694  ADD_FIELD32(nfsr_dis,7,1);
695  ADD_FIELD32(nfs_ver,8,2);
696  ADD_FIELD32(ipv6_dis,10,1);
697  ADD_FIELD32(ipv6xsum_dis,11,1);
698  ADD_FIELD32(ackdis,13,1);
699  ADD_FIELD32(ipfrsp_dis,14,1);
700  ADD_FIELD32(exsten,15,1);
701  };
703 
704  struct MANC : public Reg<uint32_t> { // 0x5820 MANC Register
706  ADD_FIELD32(smbus,0,1); // SMBus enabled #####
707  ADD_FIELD32(asf,1,1); // ASF enabled #####
708  ADD_FIELD32(ronforce,2,1); // reset of force
709  ADD_FIELD32(rsvd,3,5); // reserved
710  ADD_FIELD32(rmcp1,8,1); // rcmp1 filtering
711  ADD_FIELD32(rmcp2,9,1); // rcmp2 filtering
712  ADD_FIELD32(ipv4,10,1); // enable ipv4
713  ADD_FIELD32(ipv6,11,1); // enable ipv6
714  ADD_FIELD32(snap,12,1); // accept snap
715  ADD_FIELD32(arp,13,1); // filter arp #####
716  ADD_FIELD32(neighbor,14,1); // neighbor discovery
717  ADD_FIELD32(arp_resp,15,1); // arp response
718  ADD_FIELD32(tcorst,16,1); // tco reset happened
719  ADD_FIELD32(rcvtco,17,1); // receive tco enabled ######
720  ADD_FIELD32(blkphyrst,18,1);// block phy resets ########
721  ADD_FIELD32(rcvall,19,1); // receive all
722  ADD_FIELD32(macaddrfltr,20,1); // mac address filtering ######
723  ADD_FIELD32(mng2host,21,1); // mng2 host packets #######
724  ADD_FIELD32(ipaddrfltr,22,1); // ip address filtering
725  ADD_FIELD32(xsumfilter,23,1); // checksum filtering
726  ADD_FIELD32(brfilter,24,1); // broadcast filtering
727  ADD_FIELD32(smbreq,25,1); // smb request
728  ADD_FIELD32(smbgnt,26,1); // smb grant
729  ADD_FIELD32(smbclkin,27,1); // smbclkin
730  ADD_FIELD32(smbdatain,28,1); // smbdatain
731  ADD_FIELD32(smbdataout,29,1); // smb data out
732  ADD_FIELD32(smbclkout,30,1); // smb clock out
733  };
735 
736  struct SWSM : public Reg<uint32_t> { // 0x5B50 SWSM register
738  ADD_FIELD32(smbi,0,1); // Semaphone bit
739  ADD_FIELD32(swesmbi, 1,1); // Software eeporm semaphore
740  ADD_FIELD32(wmng, 2,1); // Wake MNG clock
741  ADD_FIELD32(reserved, 3, 29);
742  };
744 
745  struct FWSM : public Reg<uint32_t> { // 0x5B54 FWSM register
747  ADD_FIELD32(eep_fw_semaphore,0,1);
748  ADD_FIELD32(fw_mode, 1,3);
749  ADD_FIELD32(ide, 4,1);
750  ADD_FIELD32(sol, 5,1);
751  ADD_FIELD32(eep_roload, 6,1);
752  ADD_FIELD32(reserved, 7,8);
753  ADD_FIELD32(fw_val_bit, 15, 1);
754  ADD_FIELD32(reset_cnt, 16, 3);
755  ADD_FIELD32(ext_err_ind, 19, 6);
756  ADD_FIELD32(reserved2, 25, 7);
757  };
759 
760  uint32_t sw_fw_sync;
761 
762  void serialize(CheckpointOut &cp) const override
763  {
764  paramOut(cp, "ctrl", ctrl._data);
765  paramOut(cp, "sts", sts._data);
766  paramOut(cp, "eecd", eecd._data);
767  paramOut(cp, "eerd", eerd._data);
768  paramOut(cp, "ctrl_ext", ctrl_ext._data);
769  paramOut(cp, "mdic", mdic._data);
770  paramOut(cp, "icr", icr._data);
772  paramOut(cp, "itr", itr._data);
774  paramOut(cp, "rctl", rctl._data);
775  paramOut(cp, "fcttv", fcttv._data);
776  paramOut(cp, "tctl", tctl._data);
777  paramOut(cp, "pba", pba._data);
778  paramOut(cp, "fcrtl", fcrtl._data);
779  paramOut(cp, "fcrth", fcrth._data);
780  paramOut(cp, "rdba", rdba._data);
781  paramOut(cp, "rdlen", rdlen._data);
782  paramOut(cp, "srrctl", srrctl._data);
783  paramOut(cp, "rdh", rdh._data);
784  paramOut(cp, "rdt", rdt._data);
785  paramOut(cp, "rdtr", rdtr._data);
786  paramOut(cp, "rxdctl", rxdctl._data);
787  paramOut(cp, "radv", radv._data);
788  paramOut(cp, "rsrpd", rsrpd._data);
789  paramOut(cp, "tdba", tdba._data);
790  paramOut(cp, "tdlen", tdlen._data);
791  paramOut(cp, "tdh", tdh._data);
792  paramOut(cp, "txdca_ctl", txdca_ctl._data);
793  paramOut(cp, "tdt", tdt._data);
794  paramOut(cp, "tidv", tidv._data);
795  paramOut(cp, "txdctl", txdctl._data);
796  paramOut(cp, "tadv", tadv._data);
797  //paramOut(cp, "tdwba", tdwba._data);
799  paramOut(cp, "rxcsum", rxcsum._data);
801  paramOut(cp, "rfctl", rfctl._data);
802  paramOut(cp, "manc", manc._data);
803  paramOut(cp, "swsm", swsm._data);
804  paramOut(cp, "fwsm", fwsm._data);
806  }
807 
808  void unserialize(CheckpointIn &cp) override
809  {
810  paramIn(cp, "ctrl", ctrl._data);
811  paramIn(cp, "sts", sts._data);
812  paramIn(cp, "eecd", eecd._data);
813  paramIn(cp, "eerd", eerd._data);
814  paramIn(cp, "ctrl_ext", ctrl_ext._data);
815  paramIn(cp, "mdic", mdic._data);
816  paramIn(cp, "icr", icr._data);
818  paramIn(cp, "itr", itr._data);
820  paramIn(cp, "rctl", rctl._data);
821  paramIn(cp, "fcttv", fcttv._data);
822  paramIn(cp, "tctl", tctl._data);
823  paramIn(cp, "pba", pba._data);
824  paramIn(cp, "fcrtl", fcrtl._data);
825  paramIn(cp, "fcrth", fcrth._data);
826  paramIn(cp, "rdba", rdba._data);
827  paramIn(cp, "rdlen", rdlen._data);
828  paramIn(cp, "srrctl", srrctl._data);
829  paramIn(cp, "rdh", rdh._data);
830  paramIn(cp, "rdt", rdt._data);
831  paramIn(cp, "rdtr", rdtr._data);
832  paramIn(cp, "rxdctl", rxdctl._data);
833  paramIn(cp, "radv", radv._data);
834  paramIn(cp, "rsrpd", rsrpd._data);
835  paramIn(cp, "tdba", tdba._data);
836  paramIn(cp, "tdlen", tdlen._data);
837  paramIn(cp, "tdh", tdh._data);
838  paramIn(cp, "txdca_ctl", txdca_ctl._data);
839  paramIn(cp, "tdt", tdt._data);
840  paramIn(cp, "tidv", tidv._data);
841  paramIn(cp, "txdctl", txdctl._data);
842  paramIn(cp, "tadv", tadv._data);
844  //paramIn(cp, "tdwba", tdwba._data);
845  paramIn(cp, "rxcsum", rxcsum._data);
847  paramIn(cp, "rfctl", rfctl._data);
848  paramIn(cp, "manc", manc._data);
849  paramIn(cp, "swsm", swsm._data);
850  paramIn(cp, "fwsm", fwsm._data);
852  }
853 };
854 } // namespace iGbReg
iGbReg::REG_FCTTV
const uint32_t REG_FCTTV
Definition: i8254xGBe_defs.hh:56
iGbReg::IT_ACK
@ IT_ACK
Definition: i8254xGBe_defs.hh:185
iGbReg::Regs::EERD::ADD_FIELD32
ADD_FIELD32(start, 0, 1)
iGbReg::REG_ICR
const uint32_t REG_ICR
Definition: i8254xGBe_defs.hh:49
iGbReg::Regs::CTRL
Definition: i8254xGBe_defs.hh:316
iGbReg::TxdOp::eop
bool eop(TxDesc *d)
Definition: i8254xGBe_defs.hh:260
iGbReg::REG_RDH
const uint32_t REG_RDH
Definition: i8254xGBe_defs.hh:68
iGbReg::VLAN_FILTER_TABLE_SIZE
const uint8_t VLAN_FILTER_TABLE_SIZE
Definition: i8254xGBe_defs.hh:107
iGbReg::REG_PBA
const uint32_t REG_PBA
Definition: i8254xGBe_defs.hh:48
iGbReg::IT_RXCFG
@ IT_RXCFG
Definition: i8254xGBe_defs.hh:180
iGbReg::REG_CTRL_EXT
const uint32_t REG_CTRL_EXT
Definition: i8254xGBe_defs.hh:42
iGbReg::RXDEE_USE
const uint16_t RXDEE_USE
Definition: i8254xGBe_defs.hh:148
iGbReg::RXDS_DD
const uint16_t RXDS_DD
Definition: i8254xGBe_defs.hh:132
iGbReg::REG_RXCSUM
const uint32_t REG_RXCSUM
Definition: i8254xGBe_defs.hh:86
iGbReg::IT_RXO
@ IT_RXO
Definition: i8254xGBe_defs.hh:177
iGbReg::IT_RXDMT
@ IT_RXDMT
Definition: i8254xGBe_defs.hh:176
iGbReg::REG_RAL
const uint32_t REG_RAL
Definition: i8254xGBe_defs.hh:90
replaceBits
void replaceBits(T &val, int first, int last, B bit_val)
A convenience function to replace bits first to last of val with bit_val in place.
Definition: bitfield.hh:179
iGbReg::REG_WUC
const uint32_t REG_WUC
Definition: i8254xGBe_defs.hh:94
iGbReg::Regs
Definition: i8254xGBe_defs.hh:297
iGbReg::REG_RDTR
const uint32_t REG_RDTR
Definition: i8254xGBe_defs.hh:70
iGbReg::RXDP_UDP
const uint16_t RXDP_UDP
Definition: i8254xGBe_defs.hh:164
iGbReg::Regs::rfctl
RFCTL rfctl
Definition: i8254xGBe_defs.hh:702
iGbReg::Regs::radv
RADV radv
Definition: i8254xGBe_defs.hh:601
iGbReg::RxDesc::len
uint16_t len
Definition: i8254xGBe_defs.hh:193
data
const char data[]
Definition: circlebuf.test.cc:42
iGbReg::Regs::RDBA::ADD_FIELD64
ADD_FIELD64(rdbal, 0, 32)
iGbReg::RXDS_PIF
const uint16_t RXDS_PIF
Definition: i8254xGBe_defs.hh:125
iGbReg::TxDesc::d2
uint64_t d2
Definition: i8254xGBe_defs.hh:226
ArmISA::t2
Bitfield< 2 > t2
Definition: miscregs_types.hh:228
UNSERIALIZE_SCALAR
#define UNSERIALIZE_SCALAR(scalar)
Definition: serialize.hh:797
iGbReg::RXDEE_HBO
const uint16_t RXDEE_HBO
Definition: i8254xGBe_defs.hh:143
iGbReg::Regs::Reg::unserialize
void unserialize(CheckpointIn &cp)
Definition: i8254xGBe_defs.hh:310
iGbReg::PHY_PID
const uint8_t PHY_PID
Definition: i8254xGBe_defs.hh:115
iGbReg::RxDesc::errors
uint32_t errors
Definition: i8254xGBe_defs.hh:217
iGbReg::RCV_ADDRESS_TABLE_SIZE
const uint8_t RCV_ADDRESS_TABLE_SIZE
Definition: i8254xGBe_defs.hh:108
iGbReg::Regs::TXDCA_CTL
Definition: i8254xGBe_defs.hh:628
ArmISA::i
Bitfield< 7 > i
Definition: miscregs_types.hh:63
iGbReg::RxDesc::header_len
uint16_t header_len
Definition: i8254xGBe_defs.hh:207
iGbReg::Regs::mdic
MDIC mdic
Definition: i8254xGBe_defs.hh:425
iGbReg::EEPROM_READ_OPCODE_SPI
const uint8_t EEPROM_READ_OPCODE_SPI
Definition: i8254xGBe_defs.hh:102
iGbReg::Regs::RFCTL::ADD_FIELD32
ADD_FIELD32(iscsi_dis, 0, 1)
iGbReg::RXDT_ADV_SPLIT_A
const uint8_t RXDT_ADV_SPLIT_A
Definition: i8254xGBe_defs.hh:156
iGbReg::REG_RLPML
const uint32_t REG_RLPML
Definition: i8254xGBe_defs.hh:87
iGbReg::TxDesc::d1
uint64_t d1
Definition: i8254xGBe_defs.hh:225
Serializable
Basic support for object serialization.
Definition: serialize.hh:172
iGbReg::IT_MADC
@ IT_MADC
Definition: i8254xGBe_defs.hh:179
iGbReg::RxDesc::pkt_type
uint16_t pkt_type
Definition: i8254xGBe_defs.hh:205
iGbReg::Regs::tdlen
TDLEN tdlen
Definition: i8254xGBe_defs.hh:620
iGbReg::Regs::ITR
Definition: i8254xGBe_defs.hh:451
iGbReg::REG_IMC
const uint32_t REG_IMC
Definition: i8254xGBe_defs.hh:53
iGbReg::Regs::STATUS
Definition: i8254xGBe_defs.hh:352
iGbReg::Regs::tdwba
uint64_t tdwba
Definition: i8254xGBe_defs.hh:676
ArmISA::fd
Bitfield< 14, 12 > fd
Definition: types.hh:159
iGbReg::RXDEE_LE
const uint16_t RXDEE_LE
Definition: i8254xGBe_defs.hh:145
iGbReg::TxdOp::TXD_ADVCNXT
const uint8_t TXD_ADVCNXT
Definition: i8254xGBe_defs.hh:232
iGbReg::PHY_EPSTATUS
const uint8_t PHY_EPSTATUS
Definition: i8254xGBe_defs.hh:118
iGbReg::Regs::rsrpd
RSRPD rsrpd
Definition: i8254xGBe_defs.hh:607
ArmISA::rxo
Bitfield< 27 > rxo
Definition: miscregs_types.hh:728
iGbReg::Regs::TDBA::ADD_FIELD64
ADD_FIELD64(tdbal, 0, 32)
type
uint8_t type
Definition: inet.hh:421
iGbReg::TxdOp::tcp
bool tcp(TxDesc *d)
Definition: i8254xGBe_defs.hh:262
X86ISA::vme
Bitfield< 0 > vme
Definition: misc.hh:638
iGbReg::Regs::imr
uint32_t imr
Definition: i8254xGBe_defs.hh:449
iGbReg::TxdOp::ipcss
int ipcss(TxDesc *d)
Definition: i8254xGBe_defs.hh:275
iGbReg::Regs::Reg::operator==
bool operator==(T d)
Definition: i8254xGBe_defs.hh:303
iGbReg::RXDP_IPV4E
const uint16_t RXDP_IPV4E
Definition: i8254xGBe_defs.hh:160
iGbReg::RxDesc::adv_read
struct iGbReg::RxDesc::@84::@87 adv_read
iGbReg::IT_LSC
@ IT_LSC
Definition: i8254xGBe_defs.hh:174
iGbReg::REG_FCAL
const uint32_t REG_FCAL
Definition: i8254xGBe_defs.hh:44
iGbReg::Regs::FCTTV::ADD_FIELD32
ADD_FIELD32(ttv, 0, 16)
ArmISA::rsvd
Bitfield< 29, 28 > rsvd
Definition: miscregs_types.hh:409
X86ISA::op
Bitfield< 4 > op
Definition: types.hh:78
iGbReg::Regs::RSRPD
Definition: i8254xGBe_defs.hh:603
iGbReg::Regs::Reg::serialize
void serialize(CheckpointOut &cp) const
Definition: i8254xGBe_defs.hh:306
iGbReg::TxdOp::isLegacy
bool isLegacy(TxDesc *d)
Definition: i8254xGBe_defs.hh:235
iGbReg::TxdOp::setDd
void setDd(TxDesc *d)
Definition: i8254xGBe_defs.hh:245
iGbReg::TxdOp::isAdvDesc
bool isAdvDesc(TxDesc *d)
Definition: i8254xGBe_defs.hh:239
iGbReg::TxdOp::hdrlen
int hdrlen(TxDesc *d)
Definition: i8254xGBe_defs.hh:277
iGbReg::IT_TXDW
@ IT_TXDW
Definition: i8254xGBe_defs.hh:172
iGbReg::Regs::PBA
Definition: i8254xGBe_defs.hh:520
iGbReg::REG_SRRCTL
const uint32_t REG_SRRCTL
Definition: i8254xGBe_defs.hh:67
iGbReg::Regs::srrctl
SRRCTL srrctl
Definition: i8254xGBe_defs.hh:565
iGbReg::RXDS_UDPCS
const uint16_t RXDS_UDPCS
Definition: i8254xGBe_defs.hh:128
iGbReg::REG_RAH
const uint32_t REG_RAH
Definition: i8254xGBe_defs.hh:91
iGbReg::Regs::TDLEN::ADD_FIELD32
ADD_FIELD32(len, 7, 13)
iGbReg::Regs::EECD
Definition: i8254xGBe_defs.hh:369
iGbReg::RXDE_SEQ
const uint8_t RXDE_SEQ
Definition: i8254xGBe_defs.hh:138
iGbReg::Regs::RFCTL
Definition: i8254xGBe_defs.hh:689
iGbReg::Regs::txdctl
TXDCTL txdctl
Definition: i8254xGBe_defs.hh:661
iGbReg::Regs::RCTL::ADD_FIELD32
ADD_FIELD32(rst, 0, 1)
iGbReg::RXDS_UDPV
const uint16_t RXDS_UDPV
Definition: i8254xGBe_defs.hh:123
iGbReg::RXDP_IPV6
const uint16_t RXDP_IPV6
Definition: i8254xGBe_defs.hh:161
iGbReg::REG_WUFC
const uint32_t REG_WUFC
Definition: i8254xGBe_defs.hh:95
iGbReg::RXDE_CE
const uint8_t RXDE_CE
Definition: i8254xGBe_defs.hh:140
iGbReg::IT_TXQE
@ IT_TXQE
Definition: i8254xGBe_defs.hh:173
iGbReg::TxdOp::ipcse
int ipcse(TxDesc *d)
Definition: i8254xGBe_defs.hh:273
iGbReg::Regs::rdt
RDT rdt
Definition: i8254xGBe_defs.hh:577
iGbReg::TxdOp::getCso
uint8_t getCso(TxDesc *d)
Definition: i8254xGBe_defs.hh:264
iGbReg::TxdOp::utcmd
int utcmd(TxDesc *d)
Definition: i8254xGBe_defs.hh:285
iGbReg::RxDesc::id
uint16_t id
Definition: i8254xGBe_defs.hh:211
iGbReg::RxDesc::sph
uint16_t sph
Definition: i8254xGBe_defs.hh:208
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Definition: i8254xGBe_defs.hh:57
iGbReg::RXDT_LEGACY
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Definition: i8254xGBe_defs.hh:154
iGbReg::Regs::TXDCTL
Definition: i8254xGBe_defs.hh:648
iGbReg::TxdOp::isType
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Definition: i8254xGBe_defs.hh:237
iGbReg::TxdOp::rs
bool rs(TxDesc *d)
Definition: i8254xGBe_defs.hh:249
iGbReg::Regs::eerd
EERD eerd
Definition: i8254xGBe_defs.hh:393
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Definition: types.cc:38
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Definition: i8254xGBe_defs.hh:597
iGbReg::REG_AIFS
const uint32_t REG_AIFS
Definition: i8254xGBe_defs.hh:58
iGbReg::TxdOp::tucse
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Definition: i8254xGBe_defs.hh:270
iGbReg::Regs::RSRPD::ADD_FIELD32
ADD_FIELD32(idv, 0, 12)
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IntTypes
Definition: i8254xGBe_defs.hh:169
iGbReg::RXDP_NFS
const uint16_t RXDP_NFS
Definition: i8254xGBe_defs.hh:166
iGbReg::TxdOp::ic
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Definition: i8254xGBe_defs.hh:250
iGbReg::Regs::manc
MANC manc
Definition: i8254xGBe_defs.hh:734
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ADD_FIELD32(delay, 0, 16)
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Definition: i8254xGBe_defs.hh:413
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const uint32_t REG_TDWBAL
Definition: i8254xGBe_defs.hh:83
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Definition: i8254xGBe_defs.hh:642
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Definition: i8254xGBe_defs.hh:248
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const uint32_t REG_STATUS
Definition: i8254xGBe_defs.hh:39
iGbReg::Regs::MANC::ADD_FIELD32
ADD_FIELD32(smbus, 0, 1)
iGbReg::Regs::RDH::ADD_FIELD32
ADD_FIELD32(rdh, 0, 16)
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Definition: i8254xGBe_defs.hh:663
iGbReg::Regs::RDLEN
Definition: i8254xGBe_defs.hh:550
iGbReg::Regs::FWSM
Definition: i8254xGBe_defs.hh:745
iGbReg::REG_TDLEN
const uint32_t REG_TDLEN
Definition: i8254xGBe_defs.hh:76
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RDBA rdba
Definition: i8254xGBe_defs.hh:548
iGbReg::Regs::CTRL_EXT
Definition: i8254xGBe_defs.hh:395
iGbReg::RxDesc::vlan_tag
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Definition: i8254xGBe_defs.hh:219
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Definition: i8254xGBe_defs.hh:195
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const uint32_t REG_TCTL
Definition: i8254xGBe_defs.hh:73
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Definition: cprintf.cc:40
iGbReg::Regs::RXDCTL
Definition: i8254xGBe_defs.hh:586
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@ IT_TXDLOW
Definition: i8254xGBe_defs.hh:183
iGbReg::Regs::fcrtl
FCRTL fcrtl
Definition: i8254xGBe_defs.hh:533
iGbReg::Regs::fcttv
FCTTV fcttv
Definition: i8254xGBe_defs.hh:502
iGbReg::REG_FCT
const uint32_t REG_FCT
Definition: i8254xGBe_defs.hh:46
Stats::enabled
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Definition: statistics.cc:545
iGbReg::REG_RDBAH
const uint32_t REG_RDBAH
Definition: i8254xGBe_defs.hh:65
iGbReg::REG_VET
const uint32_t REG_VET
Definition: i8254xGBe_defs.hh:47
iGbReg::Regs::swsm
SWSM swsm
Definition: i8254xGBe_defs.hh:743
iGbReg::TxdOp::isData
bool isData(TxDesc *d)
Definition: i8254xGBe_defs.hh:241
bitfield.hh
iGbReg::REG_RDT
const uint32_t REG_RDT
Definition: i8254xGBe_defs.hh:69
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Definition: i8254xGBe_defs.hh:105
iGbReg::REG_RDBAL
const uint32_t REG_RDBAL
Definition: i8254xGBe_defs.hh:64
iGbReg::TxdOp::ixsm
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Definition: i8254xGBe_defs.hh:267
iGbReg
Definition: i8254xGBe_defs.hh:34
iGbReg::Regs::tidv
TIDV tidv
Definition: i8254xGBe_defs.hh:646
iGbReg::REG_RFCTL
const uint32_t REG_RFCTL
Definition: i8254xGBe_defs.hh:88
iGbReg::Regs::Reg::operator()
T operator()()
Definition: i8254xGBe_defs.hh:301
iGbReg::RxDesc::buf
Addr buf
Definition: i8254xGBe_defs.hh:192
iGbReg::REG_ICS
const uint32_t REG_ICS
Definition: i8254xGBe_defs.hh:51
iGbReg::Regs::itr
ITR itr
Definition: i8254xGBe_defs.hh:456
iGbReg::Regs::RCTL
Definition: i8254xGBe_defs.hh:463
iGbReg::Regs::Reg::operator=
const Reg< T > & operator=(T d)
Definition: i8254xGBe_defs.hh:302
iGbReg::TxdOp::getLen
Addr getLen(TxDesc *d)
Definition: i8254xGBe_defs.hh:244
iGbReg::TxdOp::tucso
int tucso(TxDesc *d)
Definition: i8254xGBe_defs.hh:271
iGbReg::Regs::rdh
RDH rdh
Definition: i8254xGBe_defs.hh:571
iGbReg::Regs::TDLEN
Definition: i8254xGBe_defs.hh:616
iGbReg::REG_EECD
const uint32_t REG_EECD
Definition: i8254xGBe_defs.hh:40
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Bitfield< 9 > d
Definition: miscregs_types.hh:60
iGbReg::Regs::FCRTL::ADD_FIELD32
ADD_FIELD32(rtl, 3, 28)
iGbReg::PHY_PSTATUS
const uint8_t PHY_PSTATUS
Definition: i8254xGBe_defs.hh:114
iGbReg::Regs::FCRTL
Definition: i8254xGBe_defs.hh:527
iGbReg::Regs::tdt
TDT tdt
Definition: i8254xGBe_defs.hh:640
iGbReg::REG_LEDCTL
const uint32_t REG_LEDCTL
Definition: i8254xGBe_defs.hh:59
iGbReg::Regs::RDT::ADD_FIELD32
ADD_FIELD32(rdt, 0, 16)
iGbReg::TxdOp::getCss
uint8_t getCss(TxDesc *d)
Definition: i8254xGBe_defs.hh:265
iGbReg::Regs::Reg
Definition: i8254xGBe_defs.hh:299
iGbReg::EEPROM_RDSR_OPCODE_SPI
const uint8_t EEPROM_RDSR_OPCODE_SPI
Definition: i8254xGBe_defs.hh:103
MipsISA::r
r
Definition: pra_constants.hh:95
iGbReg::Regs::RXCSUM
Definition: i8254xGBe_defs.hh:678
iGbReg::RxDesc::adv_wb
struct iGbReg::RxDesc::@84::@88 adv_wb
iGbReg::Regs::TCTL
Definition: i8254xGBe_defs.hh:504
iGbReg::STATS_REGS_SIZE
const uint32_t STATS_REGS_SIZE
Definition: i8254xGBe_defs.hh:110
iGbReg::Regs::TDT
Definition: i8254xGBe_defs.hh:636
iGbReg::RXDEE_IPE
const uint16_t RXDEE_IPE
Definition: i8254xGBe_defs.hh:150
iGbReg::TxdOp::mss
int mss(TxDesc *d)
Definition: i8254xGBe_defs.hh:276
iGbReg::RXDE_TCPE
const uint8_t RXDE_TCPE
Definition: i8254xGBe_defs.hh:137
iGbReg::Regs::CTRL_EXT::ADD_FIELD32
ADD_FIELD32(gpi_en, 0, 4)
iGbReg::RXDEE_PE
const uint16_t RXDEE_PE
Definition: i8254xGBe_defs.hh:146
iGbReg::Regs::FCRTH
Definition: i8254xGBe_defs.hh:535
iGbReg::REG_FWSM
const uint32_t REG_FWSM
Definition: i8254xGBe_defs.hh:99
iGbReg::IT_GPI1
@ IT_GPI1
Definition: i8254xGBe_defs.hh:182
iGbReg::Regs::RDT
Definition: i8254xGBe_defs.hh:573
iGbReg::Regs::MANC
Definition: i8254xGBe_defs.hh:704
iGbReg::REG_TDBAH
const uint32_t REG_TDBAH
Definition: i8254xGBe_defs.hh:75
iGbReg::REG_RADV
const uint32_t REG_RADV
Definition: i8254xGBe_defs.hh:72
iGbReg::Regs::sts
STATUS sts
Definition: i8254xGBe_defs.hh:367
iGbReg::REG_RXDCTL
const uint32_t REG_RXDCTL
Definition: i8254xGBe_defs.hh:71
iGbReg::RxDesc::errors
uint8_t errors
Definition: i8254xGBe_defs.hh:196
iGbReg::Regs::FCRTH::ADD_FIELD32
ADD_FIELD32(rth, 3, 13)
iGbReg::RxDesc::vlan
uint16_t vlan
Definition: i8254xGBe_defs.hh:197
iGbReg::IT_NONE
@ IT_NONE
Definition: i8254xGBe_defs.hh:171
iGbReg::Regs::SRRCTL::hdrLen
unsigned hdrLen()
Definition: i8254xGBe_defs.hh:563
iGbReg::TxdOp::txsm
bool txsm(TxDesc *d)
Definition: i8254xGBe_defs.hh:268
iGbReg::REG_MANC
const uint32_t REG_MANC
Definition: i8254xGBe_defs.hh:97
iGbReg::Regs::Reg::Reg
Reg()
Definition: i8254xGBe_defs.hh:305
iGbReg::RXDE_RXE
const uint8_t RXDE_RXE
Definition: i8254xGBe_defs.hh:135
iGbReg::REG_EERD
const uint32_t REG_EERD
Definition: i8254xGBe_defs.hh:41
iGbReg::IT_RXT
@ IT_RXT
Definition: i8254xGBe_defs.hh:178
iGbReg::Regs::MDIC
Definition: i8254xGBe_defs.hh:415
iGbReg::TxdOp::ipcso
int ipcso(TxDesc *d)
Definition: i8254xGBe_defs.hh:274
iGbReg::REG_CTRL
const uint32_t REG_CTRL
Definition: i8254xGBe_defs.hh:38
iGbReg::RxDesc::hdr
Addr hdr
Definition: i8254xGBe_defs.hh:201
iGbReg::REG_TIDV
const uint32_t REG_TIDV
Definition: i8254xGBe_defs.hh:80
iGbReg::Regs::SRRCTL::ADD_FIELD32
ADD_FIELD32(pktlen, 0, 8)
iGbReg::REG_SWFWSYNC
const uint32_t REG_SWFWSYNC
Definition: i8254xGBe_defs.hh:100
iGbReg::RXDP_SCTP
const uint16_t RXDP_SCTP
Definition: i8254xGBe_defs.hh:165
iGbReg::Regs::FWSM::ADD_FIELD32
ADD_FIELD32(eep_fw_semaphore, 0, 1)
ArmISA::en
Bitfield< 30 > en
Definition: miscregs_types.hh:455
iGbReg::IT_SRPD
@ IT_SRPD
Definition: i8254xGBe_defs.hh:184
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
iGbReg::Regs::ICR
Definition: i8254xGBe_defs.hh:427
iGbReg::Regs::fcrth
FCRTH fcrth
Definition: i8254xGBe_defs.hh:541
iGbReg::TxdOp::getTsoLen
int getTsoLen(TxDesc *d)
Definition: i8254xGBe_defs.hh:284
iGbReg::Regs::RCTL::descSize
unsigned descSize()
Definition: i8254xGBe_defs.hh:484
iGbReg::Regs::SRRCTL
Definition: i8254xGBe_defs.hh:556
iGbReg::Regs::rctl
RCTL rctl
Definition: i8254xGBe_defs.hh:496
SERIALIZE_SCALAR
#define SERIALIZE_SCALAR(scalar)
Definition: serialize.hh:790
iGbReg::Regs::SRRCTL::bufLen
unsigned bufLen()
Definition: i8254xGBe_defs.hh:562
iGbReg::RXDEE_CE
const uint16_t RXDEE_CE
Definition: i8254xGBe_defs.hh:144
iGbReg::RXDS_IPCS
const uint16_t RXDS_IPCS
Definition: i8254xGBe_defs.hh:126
iGbReg::Regs::RDBA
Definition: i8254xGBe_defs.hh:543
iGbReg::RXDP_IPV4
const uint16_t RXDP_IPV4
Definition: i8254xGBe_defs.hh:159
iGbReg::Regs::ctrl
CTRL ctrl
Definition: i8254xGBe_defs.hh:350
iGbReg::TxdOp::tucss
int tucss(TxDesc *d)
Definition: i8254xGBe_defs.hh:272
ArmISA::e
Bitfield< 9 > e
Definition: miscregs_types.hh:61
iGbReg::REG_TDH
const uint32_t REG_TDH
Definition: i8254xGBe_defs.hh:77
iGbReg::RXDP_IPV6E
const uint16_t RXDP_IPV6E
Definition: i8254xGBe_defs.hh:162
iGbReg::Regs::TCTL::ADD_FIELD32
ADD_FIELD32(rst, 0, 1)
iGbReg::Regs::tdba
TDBA tdba
Definition: i8254xGBe_defs.hh:614
iGbReg::Regs::rdtr
RDTR rdtr
Definition: i8254xGBe_defs.hh:584
iGbReg::RXDP_TCP
const uint16_t RXDP_TCP
Definition: i8254xGBe_defs.hh:163
iGbReg::TxdOp::ide
bool ide(TxDesc *d)
Definition: i8254xGBe_defs.hh:247
iGbReg::Regs::fwsm
FWSM fwsm
Definition: i8254xGBe_defs.hh:758
iGbReg::TxdOp::isTypes
bool isTypes(TxDesc *d, uint8_t t1, uint8_t t2)
Definition: i8254xGBe_defs.hh:238
iGbReg::Regs::MDIC::ADD_FIELD32
ADD_FIELD32(data, 0, 16)
iGbReg::Regs::RDLEN::ADD_FIELD32
ADD_FIELD32(len, 7, 13)
iGbReg::Regs::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: i8254xGBe_defs.hh:762
iGbReg::Regs::TDT::ADD_FIELD32
ADD_FIELD32(tdt, 0, 16)
iGbReg::Regs::TDBA
Definition: i8254xGBe_defs.hh:609
iGbReg::RxDesc::legacy
struct iGbReg::RxDesc::@84::@86 legacy
iGbReg::REG_IMS
const uint32_t REG_IMS
Definition: i8254xGBe_defs.hh:52
iGbReg::Regs::RXCSUM::ADD_FIELD32
ADD_FIELD32(pcss, 0, 8)
iGbReg::Regs::EERD
Definition: i8254xGBe_defs.hh:386
iGbReg::IT_RXSEQ
@ IT_RXSEQ
Definition: i8254xGBe_defs.hh:175
iGbReg::RXDS_EOP
const uint16_t RXDS_EOP
Definition: i8254xGBe_defs.hh:131
iGbReg::REG_RDLEN
const uint32_t REG_RDLEN
Definition: i8254xGBe_defs.hh:66
iGbReg::REG_FCAH
const uint32_t REG_FCAH
Definition: i8254xGBe_defs.hh:45
iGbReg::REG_TDBAL
const uint32_t REG_TDBAL
Definition: i8254xGBe_defs.hh:74
iGbReg::Regs::Reg::_data
T _data
Definition: i8254xGBe_defs.hh:300
iGbReg::TxDesc
Definition: i8254xGBe_defs.hh:224
iGbReg::RXDS_VP
const uint16_t RXDS_VP
Definition: i8254xGBe_defs.hh:129
iGbReg::Regs::Reg::operator()
void operator()(T d)
Definition: i8254xGBe_defs.hh:304
iGbReg::REG_MDIC
const uint32_t REG_MDIC
Definition: i8254xGBe_defs.hh:43
iGbReg::Regs::RXDCTL::ADD_FIELD32
ADD_FIELD32(pthresh, 0, 6)
iGbReg::REG_IAM
const uint32_t REG_IAM
Definition: i8254xGBe_defs.hh:54
iGbReg::Regs::txdca_ctl
TXDCA_CTL txdca_ctl
Definition: i8254xGBe_defs.hh:634
iGbReg::Regs::tctl
TCTL tctl
Definition: i8254xGBe_defs.hh:518
iGbReg::Regs::RADV::ADD_FIELD32
ADD_FIELD32(idv, 0, 16)
iGbReg::Regs::TXDCTL::ADD_FIELD32
ADD_FIELD32(pthresh, 0, 6)
iGbReg::TxdOp::TXD_ADVDATA
const uint8_t TXD_ADVDATA
Definition: i8254xGBe_defs.hh:233
iGbReg::RxDesc::__reserved1
uint16_t __reserved1
Definition: i8254xGBe_defs.hh:206
iGbReg::REG_TXDCA_CTL
const uint32_t REG_TXDCA_CTL
Definition: i8254xGBe_defs.hh:78
iGbReg::Regs::FCTTV
Definition: i8254xGBe_defs.hh:498
iGbReg::Regs::EECD::ADD_FIELD32
ADD_FIELD32(sk, 0, 1)
iGbReg::TxdOp::ip
bool ip(TxDesc *d)
Definition: i8254xGBe_defs.hh:261
iGbReg::RXDEE_OSE
const uint16_t RXDEE_OSE
Definition: i8254xGBe_defs.hh:147
ArmISA::len
Bitfield< 18, 16 > len
Definition: miscregs_types.hh:439
iGbReg::REG_TXDCTL
const uint32_t REG_TXDCTL
Definition: i8254xGBe_defs.hh:81
iGbReg::Regs::TDH::ADD_FIELD32
ADD_FIELD32(tdh, 0, 16)
addr
ip6_addr_t addr
Definition: inet.hh:423
iGbReg::Regs::CTRL::ADD_FIELD32
ADD_FIELD32(fd, 0, 1)
paramIn
void paramIn(CheckpointIn &cp, const string &name, ExtMachInst &machInst)
Definition: types.cc:69
iGbReg::PHY_EPID
const uint8_t PHY_EPID
Definition: i8254xGBe_defs.hh:116
iGbReg::Regs::rxcsum
RXCSUM rxcsum
Definition: i8254xGBe_defs.hh:685
iGbReg::RxDesc::rss_type
uint16_t rss_type
Definition: i8254xGBe_defs.hh:204
iGbReg::Regs::pba
PBA pba
Definition: i8254xGBe_defs.hh:525
iGbReg::REG_SWSM
const uint32_t REG_SWSM
Definition: i8254xGBe_defs.hh:98
iGbReg::RXDT_ADV_ONEBUF
const uint8_t RXDT_ADV_ONEBUF
Definition: i8254xGBe_defs.hh:155
iGbReg::REG_EICR
const uint32_t REG_EICR
Definition: i8254xGBe_defs.hh:60
iGbReg::RxDesc::pkt
Addr pkt
Definition: i8254xGBe_defs.hh:200
iGbReg::REG_TDWBAH
const uint32_t REG_TDWBAH
Definition: i8254xGBe_defs.hh:84
CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:63
iGbReg::Regs::TDH
Definition: i8254xGBe_defs.hh:622
iGbReg::MULTICAST_TABLE_SIZE
const uint8_t MULTICAST_TABLE_SIZE
Definition: i8254xGBe_defs.hh:109
ArmISA::t1
Bitfield< 1 > t1
Definition: miscregs_types.hh:229
iGbReg::TxdOp::tse
bool tse(TxDesc *d)
Definition: i8254xGBe_defs.hh:251
iGbReg::Regs::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: i8254xGBe_defs.hh:808
iGbReg::REG_IVAR0
const uint32_t REG_IVAR0
Definition: i8254xGBe_defs.hh:61
iGbReg::RxDesc
Definition: i8254xGBe_defs.hh:189
iGbReg::TxdOp::TXD_CNXT
const uint8_t TXD_CNXT
Definition: i8254xGBe_defs.hh:230
iGbReg::Regs::sw_fw_sync
uint32_t sw_fw_sync
Definition: i8254xGBe_defs.hh:760
iGbReg::Regs::RDH
Definition: i8254xGBe_defs.hh:567
iGbReg::Regs::rlpml
uint32_t rlpml
Definition: i8254xGBe_defs.hh:687
iGbReg::RXDEE_TCPE
const uint16_t RXDEE_TCPE
Definition: i8254xGBe_defs.hh:149
iGbReg::RxDesc::rss_hash
uint32_t rss_hash
Definition: i8254xGBe_defs.hh:214
iGbReg::RXDS_DYNINT
const uint16_t RXDS_DYNINT
Definition: i8254xGBe_defs.hh:122
iGbReg::TxdOp::TXD_DATA
const uint8_t TXD_DATA
Definition: i8254xGBe_defs.hh:231
iGbReg::REG_RCTL
const uint32_t REG_RCTL
Definition: i8254xGBe_defs.hh:55
iGbReg::TxdOp::ifcs
bool ifcs(TxDesc *d)
Definition: i8254xGBe_defs.hh:259
iGbReg::REG_FCRTL
const uint32_t REG_FCRTL
Definition: i8254xGBe_defs.hh:62
iGbReg::Regs::TXDCA_CTL::ADD_FIELD32
ADD_FIELD32(cpu_mask, 0, 5)
iGbReg::Regs::rxdctl
RXDCTL rxdctl
Definition: i8254xGBe_defs.hh:595
iGbReg::REG_TADV
const uint32_t REG_TADV
Definition: i8254xGBe_defs.hh:82
iGbReg::REG_MTA
const uint32_t REG_MTA
Definition: i8254xGBe_defs.hh:89
iGbReg::Regs::TADV::ADD_FIELD32
ADD_FIELD32(idv, 0, 16)
iGbReg::Regs::RDTR
Definition: i8254xGBe_defs.hh:579
iGbReg::TxdOp::getType
uint8_t getType(TxDesc *d)
Definition: i8254xGBe_defs.hh:236
iGbReg::PHY_AGC
const uint8_t PHY_AGC
Definition: i8254xGBe_defs.hh:119
iGbReg::Regs::icr
ICR icr
Definition: i8254xGBe_defs.hh:447
CheckpointIn
Definition: serialize.hh:67
iGbReg::RXDS_TCPCS
const uint16_t RXDS_TCPCS
Definition: i8254xGBe_defs.hh:127
iGbReg::RxDesc::status
uint32_t status
Definition: i8254xGBe_defs.hh:216
iGbReg::RXDE_IPE
const uint8_t RXDE_IPE
Definition: i8254xGBe_defs.hh:136
iGbReg::PHY_GSTATUS
const uint8_t PHY_GSTATUS
Definition: i8254xGBe_defs.hh:117
iGbReg::REG_WUS
const uint32_t REG_WUS
Definition: i8254xGBe_defs.hh:96
iGbReg::REG_VFTA
const uint32_t REG_VFTA
Definition: i8254xGBe_defs.hh:92
iGbReg::TxdOp::getBuf
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Definition: i8254xGBe_defs.hh:243
iGbReg::Regs::SWSM::ADD_FIELD32
ADD_FIELD32(smbi, 0, 1)
iGbReg::Regs::eecd
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Definition: i8254xGBe_defs.hh:384
iGbReg::REG_ITR
const uint32_t REG_ITR
Definition: i8254xGBe_defs.hh:50
iGbReg::Regs::SWSM
Definition: i8254xGBe_defs.hh:736
iGbReg::RXDS_IXSM
const uint16_t RXDS_IXSM
Definition: i8254xGBe_defs.hh:130
iGbReg::RxDesc::pkt_len
uint16_t pkt_len
Definition: i8254xGBe_defs.hh:218
iGbReg::RxDesc::csum
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Definition: i8254xGBe_defs.hh:194
ULL
#define ULL(N)
uint64_t constant
Definition: types.hh:50
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Definition: i8254xGBe_defs.hh:554
iGbReg::Regs::PBA::ADD_FIELD32
ADD_FIELD32(rxa, 0, 16)
iGbReg::Regs::TIDV::ADD_FIELD32
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iGbReg::RXDS_CRCV
const uint16_t RXDS_CRCV
Definition: i8254xGBe_defs.hh:124
iGbReg::Regs::STATUS::ADD_FIELD32
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iGbReg::RXDE_SE
const uint8_t RXDE_SE
Definition: i8254xGBe_defs.hh:139
iGbReg::REG_TDT
const uint32_t REG_TDT
Definition: i8254xGBe_defs.hh:79
iGbReg::Regs::tadv
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Definition: i8254xGBe_defs.hh:667
iGbReg::REG_CRCERRS
const uint32_t REG_CRCERRS
Definition: i8254xGBe_defs.hh:85
iGbReg::TxdOp::isContext
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Definition: i8254xGBe_defs.hh:240
iGbReg::Regs::ITR::ADD_FIELD32
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iGbReg::Regs::ICR::ADD_FIELD32
ADD_FIELD32(txdw, 0, 1) ADD_FIELD32(txqe
bits
T bits(T val, int first, int last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:75
iGbReg::IT_GPI0
@ IT_GPI0
Definition: i8254xGBe_defs.hh:181
iGbReg::Regs::tdh
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Definition: i8254xGBe_defs.hh:626
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Definition: i8254xGBe_defs.hh:104
iGbReg::REG_FCRTH
const uint32_t REG_FCRTH
Definition: i8254xGBe_defs.hh:63

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