gem5
v20.1.0.0
dev
arm
smmu_v3_cmdexec.cc
Go to the documentation of this file.
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/*
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* Copyright (c) 2013, 2018-2019 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "
dev/arm/smmu_v3_cmdexec.hh
"
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#include "
base/bitfield.hh
"
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#include "
dev/arm/smmu_v3.hh
"
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void
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SMMUCommandExecProcess::main
(
Yield
&yield)
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{
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SMMUAction
a
;
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a
.type =
ACTION_INITIAL_NOP
;
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a
.pkt = NULL;
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a
.ifc =
nullptr
;
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a
.delay = 0;
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yield(
a
);
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while
(
true
) {
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busy
=
true
;
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while
(
true
) {
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// Masking depending on CMDQ_BASE.LOG2SIZE (log(number of
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// queue entries)). Example: a value of 0b101 (32 entries)
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// generates a 0b11111 mask.
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int
size_mask =
mask
(
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smmu
.
regs
.
cmdq_base
&
Q_BASE_SIZE_MASK
);
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// In this case the wrap bit is considered (+1)
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int
size_mask_wrap =
mask
(
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(
smmu
.
regs
.
cmdq_base
&
Q_BASE_SIZE_MASK
) + 1);
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if
((
smmu
.
regs
.
cmdq_cons
& size_mask_wrap) ==
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(
smmu
.
regs
.
cmdq_prod
& size_mask_wrap))
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break
;
// command queue empty
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Addr
cmd_addr =
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(
smmu
.
regs
.
cmdq_base
&
Q_BASE_ADDR_MASK
) +
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(
smmu
.
regs
.
cmdq_cons
& size_mask) *
sizeof
(
SMMUCommand
);
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// This deliberately resets the error field in cmdq_cons!
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smmu
.
regs
.
cmdq_cons
= (
smmu
.
regs
.
cmdq_cons
+ 1) & size_mask_wrap;
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doRead
(yield, cmd_addr, &
cmd
,
sizeof
(
SMMUCommand
));
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smmu
.
processCommand
(
cmd
);
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}
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busy
=
false
;
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// No more commands to process, signal the SMMU as drained
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smmu
.
signalDrainDone
();
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doSleep
(yield);
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}
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}
SMMURegs::cmdq_base
uint64_t cmdq_base
Definition:
smmu_v3_defs.hh:142
ACTION_INITIAL_NOP
@ ACTION_INITIAL_NOP
Definition:
smmu_v3_proc.hh:56
SMMUProcess::doSleep
void doSleep(Yield &yield)
Definition:
smmu_v3_proc.cc:137
m5::Coroutine::CallerType
CallerType: A reference to an object of this class will be passed to the coroutine task.
Definition:
coroutine.hh:83
SMMUv3::regs
SMMURegs regs
Definition:
smmu_v3.hh:146
SMMURegs::cmdq_prod
uint32_t cmdq_prod
Definition:
smmu_v3_defs.hh:143
smmu_v3_cmdexec.hh
SMMURegs::cmdq_cons
uint32_t cmdq_cons
Definition:
smmu_v3_defs.hh:144
Q_BASE_ADDR_MASK
@ Q_BASE_ADDR_MASK
Definition:
smmu_v3_defs.hh:93
SMMUCommand
Definition:
smmu_v3_defs.hh:348
ArmISA::a
Bitfield< 8 > a
Definition:
miscregs_types.hh:62
bitfield.hh
SMMUCommandExecProcess::main
virtual void main(Yield &yield)
Definition:
smmu_v3_cmdexec.cc:44
SMMUAction
Definition:
smmu_v3_proc.hh:66
SMMUCommandExecProcess::busy
bool busy
Definition:
smmu_v3_cmdexec.hh:51
SMMUProcess::doRead
void doRead(Yield &yield, Addr addr, void *ptr, size_t size)
Definition:
smmu_v3_proc.cc:69
Drainable::signalDrainDone
void signalDrainDone() const
Signal that an object is drained.
Definition:
drain.hh:301
Q_BASE_SIZE_MASK
@ Q_BASE_SIZE_MASK
Definition:
smmu_v3_defs.hh:94
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition:
types.hh:142
smmu_v3.hh
SMMUProcess::smmu
SMMUv3 & smmu
Definition:
smmu_v3_proc.hh:106
SMMUv3::processCommand
void processCommand(const SMMUCommand &cmd)
Definition:
smmu_v3.cc:383
SMMUCommandExecProcess::cmd
SMMUCommand cmd
Definition:
smmu_v3_cmdexec.hh:49
ArmISA::mask
Bitfield< 28, 24 > mask
Definition:
miscregs_types.hh:711
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