gem5  v20.1.0.0
stage2_lookup.cc
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37 
39 
40 #include "arch/arm/faults.hh"
41 #include "arch/arm/system.hh"
42 #include "arch/arm/table_walker.hh"
43 #include "arch/arm/tlb.hh"
44 #include "cpu/base.hh"
45 #include "cpu/thread_context.hh"
46 #include "debug/Checkpoint.hh"
47 #include "debug/TLB.hh"
48 #include "debug/TLBVerbose.hh"
49 #include "sim/system.hh"
50 
51 using namespace ArmISA;
52 
53 Fault
55 
56 {
57  fault = stage2Tlb->getTE(&stage2Te, req, tc, mode, this, timing,
59  // Call finish if we're done already
60  if ((fault != NoFault) || (stage2Te != NULL)) {
61  // Since we directly requested the table entry (which we need later on
62  // to merge the attributes) then we've skipped some stage2 permissions
63  // checking. So call translate on stage 2 to do the checking. As the
64  // entry is now in the TLB this should always hit the cache.
65  if (fault == NoFault) {
66  if (ELIs64(tc, EL2))
68  else
70  }
71 
72  mergeTe(req, mode);
73  *destTe = stage1Te;
74  }
75  return fault;
76 }
77 
78 void
80 {
81  // Check again that we haven't got a fault
82  if (fault == NoFault) {
83  assert(stage2Te != NULL);
84 
85  // Now we have the table entries for both stages of translation
86  // merge them and insert the result into the stage 1 TLB. See
87  // CombineS1S2Desc() in pseudocode
89  stage1Te.xn |= stage2Te->xn;
90 
91  if (stage1Te.size > stage2Te->size) {
92  // Size mismatch also implies vpn mismatch (this is shifted by
93  // sizebits!).
94  stage1Te.vpn = s1Req->getVaddr() >> stage2Te->N;
97  stage1Te.N = stage2Te->N;
98  } else if (stage1Te.size < stage2Te->size) {
99  // Guest 4K could well be section-backed by host hugepage! In this
100  // case a 4K entry is added but pfn needs to be adjusted. New PFN =
101  // offset into section PFN given by stage2 IPA treated as a stage1
102  // page size.
103  const Addr pa = (stage2Te->pfn << stage2Te->N);
104  const Addr ipa = (stage1Te.pfn << stage1Te.N);
105  stage1Te.pfn = (pa | (ipa & mask(stage2Te->N))) >> stage1Te.N;
106  // Size remains smaller of the two.
107  } else {
108  // Matching sizes
110  }
111 
118  } else {
120  }
121 
123 
124  if (stage2Te->innerAttrs == 0 ||
125  stage1Te.innerAttrs == 0) {
126  // either encoding Non-cacheable
127  stage1Te.innerAttrs = 0;
128  } else if (stage2Te->innerAttrs == 2 ||
129  stage1Te.innerAttrs == 2) {
130  // either encoding Write-Through cacheable
131  stage1Te.innerAttrs = 2;
132  } else {
133  // both encodings Write-Back
134  stage1Te.innerAttrs = 3;
135  }
136 
137  if (stage2Te->outerAttrs == 0 ||
138  stage1Te.outerAttrs == 0) {
139  // either encoding Non-cacheable
140  stage1Te.outerAttrs = 0;
141  } else if (stage2Te->outerAttrs == 2 ||
142  stage1Te.outerAttrs == 2) {
143  // either encoding Write-Through cacheable
144  stage1Te.outerAttrs = 2;
145  } else {
146  // both encodings Write-Back
147  stage1Te.outerAttrs = 3;
148  }
149 
152  if (stage1Te.innerAttrs == 0 &&
153  stage1Te.outerAttrs == 0) {
154  // something Non-cacheable at each level is outer shareable
155  stage1Te.shareable = true;
156  stage1Te.outerShareable = true;
157  }
158  } else {
159  stage1Te.shareable = true;
160  stage1Te.outerShareable = true;
161  }
163  }
164 
165  // if there's a fault annotate it,
166  if (fault != NoFault) {
167  // If the second stage of translation generated a fault add the
168  // details of the original stage 1 virtual address
169  reinterpret_cast<ArmFault *>(fault.get())->annotate(ArmFault::OVA,
170  s1Req->getVaddr());
171  }
172  complete = true;
173 }
174 
175 void
176 Stage2LookUp::finish(const Fault &_fault, const RequestPtr &req,
178 {
179  fault = _fault;
180  // if we haven't got the table entry get it now
181  if ((fault == NoFault) && (stage2Te == NULL)) {
182  fault = stage2Tlb->getTE(&stage2Te, req, tc, mode, this,
184  }
185 
186  // Now we have the stage 2 table entry we need to merge it with the stage
187  // 1 entry we were given at the start
188  mergeTe(req, mode);
189 
190  if (fault != NoFault) {
191  // Returning with a fault requires the original request
192  transState->finish(fault, s1Req, tc, mode);
193  } else if (timing) {
194  // Now notify the original stage 1 translation that we finally have
195  // a result
197  }
198  // if we have been asked to delete ourselfs do it now
199  if (selfDelete) {
200  delete this;
201  }
202 }
203 
ArmISA::Stage2LookUp::stage2Te
TlbEntry * stage2Te
Definition: stage2_lookup.hh:67
BaseTLB::Translation::finish
virtual void finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc, Mode mode)=0
ArmISA::EL2
@ EL2
Definition: types.hh:624
ArmISA::Stage2LookUp::mode
BaseTLB::Mode mode
Definition: stage2_lookup.hh:63
system.hh
ArmISA::Stage2LookUp::secure
bool secure
Definition: stage2_lookup.hh:72
ArmISA::TlbEntry::N
uint8_t N
Definition: pagetable.hh:110
BaseTLB::Mode
Mode
Definition: tlb.hh:57
RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:82
tlb.hh
ArmISA::TlbEntry::MemoryType::Device
@ Device
system.hh
table_walker.hh
ArmISA
Definition: ccregs.hh:41
ArmISA::Stage2LookUp::stage2Tlb
TLB * stage2Tlb
Definition: stage2_lookup.hh:59
ArmISA::Stage2LookUp::fault
Fault fault
Definition: stage2_lookup.hh:69
ArmISA::Stage2LookUp::finish
void finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc, BaseTLB::Mode mode)
Definition: stage2_lookup.cc:176
ArmISA::ELIs64
bool ELIs64(ThreadContext *tc, ExceptionLevel el)
Definition: utility.cc:377
ArmISA::TlbEntry::innerAttrs
uint8_t innerAttrs
Definition: pagetable.hh:111
ArmISA::TLB::checkPermissions64
Fault checkPermissions64(TlbEntry *te, const RequestPtr &req, Mode mode, ThreadContext *tc)
Definition: tlb.cc:675
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:88
ArmISA::ArmFault
Definition: faults.hh:60
ArmISA::TlbEntry::mtype
MemoryType mtype
Definition: pagetable.hh:117
ArmISA::TlbEntry::MemoryType::StronglyOrdered
@ StronglyOrdered
Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:240
ArmISA::Stage2LookUp::s1Req
RequestPtr s1Req
Definition: stage2_lookup.hh:61
ArmISA::Stage2LookUp::tranType
TLB::ArmTranslationType tranType
Definition: stage2_lookup.hh:66
stage2_lookup.hh
ArmISA::mode
Bitfield< 4, 0 > mode
Definition: miscregs_types.hh:70
ArmISA::TlbEntry::pfn
Addr pfn
Definition: pagetable.hh:98
ArmISA::Stage2LookUp::timing
bool timing
Definition: stage2_lookup.hh:64
ArmISA::TLB::checkPermissions
Fault checkPermissions(TlbEntry *te, const RequestPtr &req, Mode mode)
Definition: tlb.cc:497
ArmISA::TlbEntry::shareable
bool shareable
Definition: pagetable.hh:137
ArmISA::Stage2LookUp::selfDelete
bool selfDelete
Definition: stage2_lookup.hh:71
faults.hh
NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:245
ArmISA::TlbEntry::outerAttrs
uint8_t outerAttrs
Definition: pagetable.hh:112
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
ArmISA::Stage2LookUp::getTe
Fault getTe(ThreadContext *tc, TlbEntry *destTe)
Definition: stage2_lookup.cc:54
ArmISA::Stage2LookUp::stage1Te
TlbEntry stage1Te
Definition: stage2_lookup.hh:60
ArmISA::ArmFault::OVA
@ OVA
Definition: faults.hh:131
ArmISA::TlbEntry
Definition: pagetable.hh:81
ArmISA::Stage2LookUp::req
RequestPtr req
Definition: stage2_lookup.hh:68
ArmISA::TlbEntry::xn
bool xn
Definition: pagetable.hh:141
base.hh
ArmISA::TlbEntry::outerShareable
bool outerShareable
Definition: pagetable.hh:138
ArmISA::TlbEntry::size
Addr size
Definition: pagetable.hh:99
ArmISA::Stage2LookUp::complete
bool complete
Definition: stage2_lookup.hh:70
ArmISA::Stage2LookUp::functional
bool functional
Definition: stage2_lookup.hh:65
ArmISA::TlbEntry::vpn
Addr vpn
Definition: pagetable.hh:100
ArmISA::Stage2LookUp::mergeTe
void mergeTe(const RequestPtr &req, BaseTLB::Mode mode)
Definition: stage2_lookup.cc:79
ArmISA::TlbEntry::updateAttributes
void updateAttributes()
Definition: pagetable.hh:242
ArmISA::Stage2LookUp::stage1Tlb
TLB * stage1Tlb
Definition: stage2_lookup.hh:58
ArmISA::TlbEntry::MemoryType::Normal
@ Normal
ArmISA::pa
Bitfield< 39, 12 > pa
Definition: miscregs_types.hh:650
ArmISA::TLB::getTE
Fault getTE(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool timing, bool functional, bool is_secure, ArmTranslationType tranType)
Definition: tlb.cc:1463
ArmISA::TlbEntry::nonCacheable
bool nonCacheable
Definition: pagetable.hh:134
ArmISA::Stage2LookUp::transState
TLB::Translation * transState
Definition: stage2_lookup.hh:62
thread_context.hh
ArmISA::TLB::translateComplete
Fault translateComplete(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode, ArmTranslationType tranType, bool callFromS2)
Definition: tlb.cc:1222
ArmISA::mask
Bitfield< 28, 24 > mask
Definition: miscregs_types.hh:711

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