| _cacheLineSize | BaseCPU | protected |
| _cpuId | BaseCPU | protected |
| _dataRequestorId | BaseCPU | protected |
| _drainManager | Drainable | private |
| _drainState | Drainable | mutableprivate |
| _instRequestorId | BaseCPU | protected |
| _params | SimObject | protected |
| _pid | BaseCPU | protected |
| _socketId | BaseCPU | protected |
| _switchedOut | BaseCPU | protected |
| _taskId | BaseCPU | protected |
| activateContext(ThreadID thread_num) | BaseCPU | virtual |
| addressMonitor | BaseCPU | private |
| addStat(Stats::Info *info) | Stats::Group | |
| addStatGroup(const char *name, Group *block) | Stats::Group | |
| armMonitor(ThreadID tid, Addr address) | BaseCPU | |
| BaseCPU(const BaseCPUParams ¶ms, sc_core::sc_module *_evs) | Iris::BaseCPU | |
| BaseCPU::BaseCPU(const Params ¶ms, bool is_checker=false) | BaseCPU | |
| baseStats | BaseCPU | |
| cacheLineSize() const | BaseCPU | inline |
| checkInterrupts(ThreadID tid) const | BaseCPU | inline |
| clearInterrupt(ThreadID tid, int int_num, int index) | BaseCPU | inline |
| clearInterrupts(ThreadID tid) | BaseCPU | inline |
| clockDomain | Clocked | private |
| Clocked(ClockDomain &clk_domain) | Clocked | inlineprotected |
| Clocked(Clocked &)=delete | Clocked | protected |
| clockEdge(Cycles cycles=Cycles(0)) const | Clocked | inline |
| ClockedObject(const ClockedObjectParams &p) | ClockedObject | |
| clockPeriod() const | Clocked | inline |
| clockPeriodUpdated() override | Iris::BaseCPU | inlineprotectedvirtual |
| contextToThread(ContextID cid) | BaseCPU | inline |
| CPU_STATE_ON enum value | BaseCPU | protected |
| CPU_STATE_SLEEP enum value | BaseCPU | protected |
| CPU_STATE_WAKEUP enum value | BaseCPU | protected |
| cpuId() const | BaseCPU | inline |
| cpuList | BaseCPU | privatestatic |
| CPUState enum name | BaseCPU | protected |
| curCycle() const | Clocked | inline |
| currentFunctionEnd | BaseCPU | private |
| currentFunctionStart | BaseCPU | private |
| currentSection() | Serializable | static |
| cycle | Clocked | mutableprivate |
| cyclesToTicks(Cycles c) const | Clocked | inline |
| dataRequestorId() const | BaseCPU | inline |
| deschedule(Event &event) | EventManager | inline |
| deschedule(Event *event) | EventManager | inline |
| deschedulePowerGatingEvent() | BaseCPU | |
| dmDrain() | Drainable | private |
| dmDrainResume() | Drainable | private |
| drain() override | SimObject | inlinevirtual |
| Drainable() | Drainable | protected |
| drainResume() | Drainable | inlineprotectedvirtual |
| drainState() const | Drainable | inline |
| enableFunctionTrace() | BaseCPU | private |
| enterPwrGating() | BaseCPU | protected |
| enterPwrGatingEvent | BaseCPU | protected |
| EventManager(EventManager &em) | EventManager | inline |
| EventManager(EventManager *em) | EventManager | inline |
| EventManager(EventQueue *eq) | EventManager | inline |
| eventq | EventManager | protected |
| eventQueue() const | EventManager | inline |
| evs | Iris::BaseCPU | protected |
| evs_base_cpu | Iris::BaseCPU | protected |
| find(const char *name) | SimObject | static |
| findContext(ThreadContext *tc) | BaseCPU | |
| flushTLBs() | BaseCPU | |
| frequency() const | Clocked | inline |
| functionEntryTick | BaseCPU | private |
| functionTraceStream | BaseCPU | private |
| functionTracingEnabled | BaseCPU | private |
| getContext(int tn) | BaseCPU | inlinevirtual |
| getCpuAddrMonitor(ThreadID tid) | BaseCPU | inline |
| getCurrentInstCount(ThreadID tid) | BaseCPU | |
| getDataPort() override | Iris::BaseCPU | inlinevirtual |
| getInstPort() override | Iris::BaseCPU | inlinevirtual |
| getInterruptController(ThreadID tid) | BaseCPU | inline |
| getPid() const | BaseCPU | inline |
| getPort(const std::string &if_name, PortID idx=InvalidPortID) override | BaseCPU | virtual |
| getProbeManager() | SimObject | |
| getSendFunctional() override | Iris::BaseCPU | inlinevirtual |
| getStatGroups() const | Stats::Group | |
| getStats() const | Stats::Group | |
| getTracer() | BaseCPU | inline |
| globalStats | BaseCPU | protectedstatic |
| Group()=delete | Stats::Group | |
| Group(const Group &)=delete | Stats::Group | |
| Group(Group *parent, const char *name=nullptr) | Stats::Group | |
| haltContext(ThreadID thread_num) | BaseCPU | virtual |
| init() override | Iris::BaseCPU | protectedvirtual |
| initState() | SimObject | virtual |
| instCnt | BaseCPU | protected |
| instCount() | BaseCPU | inline |
| instRequestorId() const | BaseCPU | inline |
| interrupts | BaseCPU | protected |
| invldPid | BaseCPU | static |
| loadState(CheckpointIn &cp) | SimObject | virtual |
| memInvalidate() | SimObject | inlinevirtual |
| memWriteback() | SimObject | inlinevirtual |
| mergedParent | Stats::Group | private |
| mergedStatGroups | Stats::Group | private |
| mergeStatGroup(Group *block) | Stats::Group | |
| mwait(ThreadID tid, PacketPtr pkt) | BaseCPU | |
| mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseMMU *mmu) | BaseCPU | |
| name() const | SimObject | inlinevirtual |
| nextCycle() const | Clocked | inline |
| notifyFork() | Drainable | inlinevirtual |
| numContexts() | BaseCPU | inline |
| numSimulatedCPUs() | BaseCPU | inlinestatic |
| numSimulatedInsts() | BaseCPU | inlinestatic |
| numSimulatedOps() | BaseCPU | inlinestatic |
| numThreads | BaseCPU | |
| SimObject::operator=(const Group &)=delete | Stats::Group | |
| Clocked::operator=(Clocked &)=delete | Clocked | protected |
| PARAMS(BaseCPU) | BaseCPU | |
| Params typedef | ClockedObject | |
| params() const | SimObject | inline |
| path | Serializable | privatestatic |
| PCMask | BaseCPU | static |
| pmuProbePoint(const char *name) | BaseCPU | protected |
| postInterrupt(ThreadID tid, int int_num, int index) | BaseCPU | |
| powerGatingOnIdle | BaseCPU | protected |
| powerState | ClockedObject | |
| ppActiveCycles | BaseCPU | protected |
| ppAllCycles | BaseCPU | protected |
| ppRetiredBranches | BaseCPU | protected |
| ppRetiredInsts | BaseCPU | protected |
| ppRetiredInstsPC | BaseCPU | protected |
| ppRetiredLoads | BaseCPU | protected |
| ppRetiredStores | BaseCPU | protected |
| ppSleeping | BaseCPU | protected |
| preDumpStats() | Stats::Group | virtual |
| previousCycle | BaseCPU | protected |
| previousState | BaseCPU | protected |
| probeInstCommit(const StaticInstPtr &inst, Addr pc) | BaseCPU | virtual |
| probeManager | SimObject | private |
| pwrGatingLatency | BaseCPU | protected |
| registerThreadContexts() | BaseCPU | |
| regProbeListeners() | SimObject | virtual |
| regProbePoints() override | BaseCPU | virtual |
| regStats() override | BaseCPU | virtual |
| reschedule(Event &event, Tick when, bool always=false) | EventManager | inline |
| reschedule(Event *event, Tick when, bool always=false) | EventManager | inline |
| resetClock() const | Clocked | inlineprotected |
| resetStats() | Stats::Group | virtual |
| resolveStat(std::string name) const | Stats::Group | |
| schedule(Event &event, Tick when) | EventManager | inline |
| schedule(Event *event, Tick when) | EventManager | inline |
| scheduleInstStop(ThreadID tid, Counter insts, const char *cause) | BaseCPU | |
| schedulePowerGatingEvent() | BaseCPU | |
| Serializable() | Serializable | |
| serialize(CheckpointOut &cp) const override | BaseCPU | virtual |
| serializeAll(CheckpointOut &cp) | SimObject | static |
| Serializable::serializeAll(const std::string &cpt_dir) | Serializable | static |
| serializeSection(CheckpointOut &cp, const char *name) const | Serializable | |
| serializeSection(CheckpointOut &cp, const std::string &name) const | Serializable | inline |
| serializeThread(CheckpointOut &cp, ThreadID tid) const override | Iris::BaseCPU | protectedvirtual |
| setCurTick(Tick newVal) | EventManager | inline |
| setPid(uint32_t pid) | BaseCPU | inline |
| signalDrainDone() const | Drainable | inlineprotected |
| SimObject(const Params &p) | SimObject | |
| SimObjectList typedef | SimObject | private |
| simObjectList | SimObject | privatestatic |
| socketId() const | BaseCPU | inline |
| startup() override | BaseCPU | virtual |
| statGroups | Stats::Group | private |
| stats | Stats::Group | private |
| suspendContext(ThreadID thread_num) | BaseCPU | virtual |
| switchedOut() const | BaseCPU | inline |
| switchOut() | BaseCPU | virtual |
| syscallRetryLatency | BaseCPU | |
| system | BaseCPU | |
| takeOverFrom(BaseCPU *cpu) | BaseCPU | virtual |
| taskId() const | BaseCPU | inline |
| taskId(uint32_t id) | BaseCPU | inline |
| threadContexts | BaseCPU | protected |
| tick | Clocked | mutableprivate |
| ticksToCycles(Tick t) const | Clocked | inline |
| totalInsts() const override | Iris::BaseCPU | virtual |
| totalOps() const override | Iris::BaseCPU | inlinevirtual |
| traceFunctions(Addr pc) | BaseCPU | inline |
| traceFunctionsInternal(Addr pc) | BaseCPU | private |
| tracer | BaseCPU | protected |
| unserialize(CheckpointIn &cp) override | BaseCPU | virtual |
| unserializeGlobals(CheckpointIn &cp) | Serializable | static |
| unserializeSection(CheckpointIn &cp, const char *name) | Serializable | |
| unserializeSection(CheckpointIn &cp, const std::string &name) | Serializable | inline |
| unserializeThread(CheckpointIn &cp, ThreadID tid) | BaseCPU | inlinevirtual |
| update() const | Clocked | inlineprivate |
| updateClockPeriod() | Clocked | inline |
| updateCycleCounters(CPUState state) | BaseCPU | inlineprotected |
| verifyMemoryMode() const | BaseCPU | inlinevirtual |
| voltage() const | Clocked | inline |
| waitForRemoteGDB() const | BaseCPU | |
| wakeup(ThreadID tid) override | Iris::BaseCPU | inlinevirtual |
| wakeupEventQueue(Tick when=(Tick) -1) | EventManager | inline |
| workItemBegin() | BaseCPU | inline |
| workItemEnd() | BaseCPU | inline |
| ~BaseCPU() | Iris::BaseCPU | virtual |
| ~Clocked() | Clocked | inlineprotectedvirtual |
| ~Drainable() | Drainable | protectedvirtual |
| ~Group() | Stats::Group | virtual |
| ~Serializable() | Serializable | virtual |
| ~SimObject() | SimObject | virtual |
