gem5  v21.0.0.0
•All Classes Namespaces Files Functions Variables Typedefs Enumerations Enumerator Friends Macros Modules Pages
Class Hierarchy
This inheritance list is sorted roughly, but not completely, alphabetically:
[detail level 123456789]
 C_amd_queue_s
 C_hsa_agent_dispatch_packet_s
 C_hsa_barrier_and_packet_s
 C_hsa_barrier_or_packet_s
 C_hsa_dispatch_packet_s
 C_hsa_queue_s
 C_hsa_signal_s
 Ca_new_struct
 ►CAapcs32
 ►CGuestABI::Aapcs32ArgumentBase
 CGuestABI::Aapcs32ArrayType< T >
 CGuestABI::Aapcs32ArrayType< E[N]>
 CAapcs64
 ►CAapcs64ArgumentBase
 CGuestABI::Aapcs64ArrayType< T >
 CGuestABI::Aapcs64ArrayType< E[N]>
 ►CArmSemihosting::AbiBase
 CAccess
 Cmm::access
 CRegisterBankTest::Access
 CX86ISA::GpuTLB::AccessInfoThis hash map will use the virtual page address as a key and will keep track of total number of accesses per page
 CBankedArray::AccessRecord
 CAccessTraceForAddress
 CEpisode::Action
 ►CActivityRecorderActivityRecorder helper class that informs the CPU if it can switch over to being idle or not
 Cstd::add_const< VecLaneT< T, Const > >
 CAddressManager
 CPrefetcher::IrregularStreamBuffer::AddressMappingAddress Mapping entry, holds an address and a confidence counter
 CAddressMonitor
 CAddressProfiler
 CDecodeCache::AddrMap< Value, CacheChunkShift >A sparse map from an Addr to a Value, stored in page chunks
 CDecodeCache::AddrMap< GenericISA::BasicDecodeCache::AddrMapEntry >
 CGenericISA::BasicDecodeCache< Decoder, EMI >::AddrMapEntry
 CNetwork::AddrMapNode
 CAddrRangeEncapsulates an address range, and supports a number of tests to check if two ranges intersect, if a range contains a specific address etc
 CAddrRangeMap< V, max_cache_size >The AddrRangeMap uses an STL map to implement an interval tree for address decoding
 CAddrRangeMap< AbstractMemory *, 1 >
 CAddrRangeMap< AddrMapEntry, 3 >
 CAddrRangeMap< MemBackdoor >
 CAddrRangeMap< MemBackdoor, 1 >
 CAddrRangeMap< PortID, 3 >
 ►Camba_pv_from_tlm_bridge
 ►Camba_pv_to_tlm_bridge
 ►CAmbaDevice
 Camd_signal_s
 CAMDKernelCode
 CApertureRegister
 CAQLRingBufferInternal ring buffer which is used to prefetch/store copies of the in-memory HSA ring buffer
 CGuestABI::Argument< ABI, Arg, Enabled >
 ►CGuestABI::Argument< Aapcs32, Composite >
 ►CGuestABI::Argument< Aapcs32, Integer >
 CGuestABI::Argument< Aapcs32Vfp, VarArgs< Types... > >
 CGuestABI::Argument< ABI, Arg, typename std::enable_if_t< std::is_base_of< ArmISA::RegABI32, ABI >::value &&std::is_integral< Arg >::value &&ABI::template IsWide< Arg >::value > >
 CGuestABI::Argument< ABI, Arg, typename std::enable_if_t< std::is_base_of< GenericSyscallABI64, ABI >::value &&std::is_integral< Arg >::value > >
 CGuestABI::Argument< ABI, Arg, typename std::enable_if_t< std::is_integral< Arg >::value &&!ABI::template IsWide< Arg >::value > >
 CGuestABI::Argument< Abi, ArmSemihosting::InPlaceArg, typename std::enable_if_t< std::is_base_of< ArmSemihosting::AbiBase, Abi >::value > >
 CGuestABI::Argument< ABI, ConstProxyPtr< T, Proxy > >
 CGuestABI::Argument< ABI, ProxyPtr< T, Proxy > >
 CGuestABI::Argument< ABI, VarArgs< Types... > >
 CGuestABI::Argument< ArmSemihosting::Abi32, Arg, typename std::enable_if_t< std::is_integral< Arg >::value > >
 ►CGuestABI::Argument< ArmSemihosting::Abi32, T >
 CGuestABI::Argument< ArmSemihosting::Abi64, Arg, typename std::enable_if_t< std::is_integral< Arg >::value > >
 ►CGuestABI::Argument< ArmSemihosting::Abi64, T >
 CGuestABI::Argument< SparcISA::SEWorkload::SyscallABI32, Arg, typename std::enable_if_t< std::is_integral< Arg >::value &&SparcISA::SEWorkload::SyscallABI32::IsWide< Arg >::value > >
 CGuestABI::Argument< TestABI, Addr >
 CGuestABI::Argument< TestABI_1D, Arg, typename std::enable_if_t< std::is_floating_point< Arg >::value > >
 CGuestABI::Argument< TestABI_1D, int >
 CGuestABI::Argument< TestABI_2D, Arg, typename std::enable_if_t< std::is_floating_point< Arg >::value > >
 CGuestABI::Argument< TestABI_2D, int >
 CGuestABI::Argument< TestABI_Prepare, int >
 CGuestABI::Argument< TestABI_TcInit, int >
 CGuestABI::Argument< X86ISA::EmuLinux::SyscallABI32, Arg, typename std::enable_if_t< std::is_integral< Arg >::value &&X86ISA::EmuLinux::SyscallABI32::IsWide< Arg >::value > >
 CGuestABI::Argument< X86PseudoInstABI, uint64_t >
 Carr_struct1
 Carr_struct2
 CAssociativeSet< Entry >Copyright (c) 2018 Metempsy Technology Consulting All rights reserved
 CAssociativeSet< Compressor::FrequentValues::VFTEntry >
 CAssociativeSet< Prefetcher::AccessMapPatternMatching::AccessMapEntry >
 CAssociativeSet< Prefetcher::DeltaCorrelatingPredictionTables::DCPTEntry >
 CAssociativeSet< Prefetcher::IndirectMemory::IndirectPatternDetectorEntry >
 CAssociativeSet< Prefetcher::IndirectMemory::PrefetchTableEntry >
 CAssociativeSet< Prefetcher::IrregularStreamBuffer::AddressMappingEntry >
 CAssociativeSet< Prefetcher::IrregularStreamBuffer::TrainingUnitEntry >
 CAssociativeSet< Prefetcher::PIF::IndexEntry >
 CAssociativeSet< Prefetcher::SignaturePath::PatternEntry >
 CAssociativeSet< Prefetcher::SignaturePath::SignatureEntry >
 CAssociativeSet< Prefetcher::SignaturePathV2::GlobalHistoryEntry >
 CAssociativeSet< Prefetcher::STeMS::ActiveGenerationTableEntry >
 ►CAtagHeader
 Cataparams
 ►CAtomicOpFunctor
 ►CAtomicRequestProtocol
 ►CAtomicResponseProtocol
 CAddressManager::AtomicStruct
 CAuxVector< IntType >
 CStats::AvgSampleStorTemplatized storage for distribution that calculates per tick mean and variance
 CStats::AvgStorTemplatized storage and interface to a per-tick average stat
 Cb_new_struct
 CBackingStore
 CBackingStoreEntryA single entry for the backing store
 CMemInterface::BankA basic class to track the bank state, i.e
 CBankedArray
 CBarrier
 ►CStats::Units::BaseParent class of all unit classes
 ►CBase
 ►CBase
 ►CCompressor::Encoder::BaseBase class for encoders
 ►CBaseBufferArgBase class for BufferArg and TypedBufferArg, Not intended to be used directly
 ►CIris::BaseCpuEvs
 ►CBaseGdbRegCacheConcrete subclasses of this abstract class represent how the register values are transmitted on the wire
 ►CBaseGenBase class for all generators, with the shared functionality and virtual functions for entering, executing and leaving the generator
 ►CBaseGicRegisters
 ►CBaseHTMCheckpointTransactional Memory checkpoint
 ►CArmISA::BaseISADeviceBase class for devices that use the MiscReg interfaces
 ►CBaseKvmTimerTimer functions to interrupt VM execution after a number of simulation ticks
 ►CBaseRemoteGDB
 ►CBaseStackTrace
 ►CSparcISA::SEWorkload::BaseSyscallABI
 ►CArmISA::EmuFreebsd::BaseSyscallABI
 ►CArmISA::EmuLinux::BaseSyscallABI
 CGenericISA::BasicDecodeCache< Decoder, EMI >
 CGenericISA::BasicDecodeCache< ArmISA::Decoder, ExtMachInst >
 CGenericISA::BasicDecodeCache< MipsISA::Decoder, ExtMachInst >
 CGenericISA::BasicDecodeCache< PowerISA::Decoder, ExtMachInst >
 CGenericISA::BasicDecodeCache< SparcISA::Decoder, ExtMachInst >
 CBasicSignal
 CSimPoint::BBInfoBasic Block information
 Csc_gem5::Port::Binding
 CBitfieldBackend::BitfieldTypes< Storage >
 CBitfieldBackend::BitUnionBaseType< T >
 CBitfieldBackend::BitUnionBaseType< BitUnionType< T > >
 CVirtIOBlock::BlkRequestVirtIO block device request as sent by guest
 CBlock
 CIdeController::Channel::BMIRegsRegisters used for bus master interface
 CBmpWriter::BmpPixel32
 CBiModeBP::BPHistory
 CTournamentBP::BPHistoryThe branch history information that is created upon predicting a branch
 CIris::ThreadContext::BpInfo
 CMinor::BranchDataForward data betwen Execute and Fetch1 carrying change-of-address/stream information
 CLoopPredictor::BranchInfo
 ►CTAGEBase::BranchInfo
 ►CStatisticalCorrector::BranchInfo
 CArmISA::BrkPoint
 CDefaultBTB::BTBEntry
 CMinor::BubbleIFInterface class for data with 'bubble' values
 CMinor::BubbleTraitsAdaptor< ElemType >Pass on call to the element
 CMinor::BubbleTraitsPtrAdaptor< PtrType, ElemType >Pass on call to the element where the element is a pointer
 CGcn3ISA::BufferRsrcDescriptor
 CBurstHelperA burst helper helps organize and manage a packet that is larger than the memory burst size
 CDecodeCache::AddrMap< Value, CacheChunkShift >::CacheChunk
 CCacheRecorder
 CFlashDevice::CallBackEntry
 Cm5::Coroutine< Arg, Ret >::CallerTypeCallerType: A reference to an object of this class will be passed to the coroutine task
 CPixelConverter::ChannelColor channel conversion and scaling helper class
 CIdeController::Channel
 CX86ISA::I8237::Channel
 CChannelAddrClass holding a guest address in a contiguous channel-local address space
 CChannelAddrRangeThe ChanneelAddrRange class describes a contiguous range of addresses in a contiguous channel-local address space
 CCheck
 CCheckpointIn
 CCheckTable
 CChunkGeneratorThis class takes an arbitrary memory region (address/length pair) and generates a series of appropriately (e.g
 CCircleBuf< T >Circular buffer backed by a vector
 CCircleBuf< char >
 CCircleBuf< value_type >
 Ctlm::circular_buffer< T >
 Ctlm::circular_buffer< REQ >
 Ctlm::circular_buffer< RSP >
 CCircularQueue< T >Circular queue
 CCircularQueue< Addr >
 CCircularQueue< CircularQueue::iterator >
 CCircularQueue< CompactorEntry >
 CCircularQueue< LQEntry >
 CCircularQueue< LSQUnit::SQEntry >
 CCircularQueue< Prefetcher::SBOOE::SandboxEntry >
 CCircularQueue< Prefetcher::STeMS::RegionMissOrderBufferEntry >
 CCircularQueue< RubyPrefetcher::NonUnitFilterEntry >
 CCircularQueue< RubyPrefetcher::UnitFilterEntry >
 CCircularQueue< Tick >
 CVncInput::ClientCutTextMessage
 ►CClockedHelper class for objects that need to be clocked
 CClockRateControlDummyProtocolType
 CCoalescedRequest
 CCompressor::Encoder::Code
 CCoeff8
 CCoeff8x8
 CDRAMInterface::CommandSimple structure to hold the values needed to keep track of commands for DRAMPower
 CItsCommand::CommandEntry
 CMemCmd::CommandInfoStructure that defines attributes and other data associated with a Command
 CCommandReg
 CTimeBufStruct< Impl >::commitComm
 CPrefetcher::PIF::CompactorEntryThe compactor tracks retired instructions addresses, leveraging the spatial and temporal locality among instructions for compaction
 CBmpWriter::CompleteV1Header
 CCompressed
 CCompressor::FrequentValues::CompData::CompressedValueA compressed value contains its encoding, and the compressed data itself
 ►CCompressionData
 CCompressor::Base::CompressionData
 CVirtIOConsole::ConfigConsole configuration structure
 CVirtIOBlock::ConfigBlock device configuration structure
 CVirtIO9PBase::ConfigVirtIO 9p configuration structure
 CSimpleBusAT< NR_OF_INITIATORS, NR_OF_TARGETS >::ConnectionInfo
 CSystem::Threads::const_iterator
 ►CConstProxyPtr< T, Proxy >
 ►CConsumer
 Cm5::stl_helpers::ContainerPrint< T >
 CBaseRemoteGDB::GdbCommand::Context
 CContextDescriptor
 ►Ctlm_utils::convenience_socket_base
 ►Ctlm_utils::convenience_socket_cb_holder
 CFastModel::ScxEvsCortexR52< Types >::CorePins
 CMipsISA::CoreSpecific
 CIntel8254Timer::CounterCounter element for PIT
 CX86ISA::CpuidResult
 CArmISA::Crypto
 CRiscvISA::CSRMetadata
 CCxxConfigDirectoryEntryConfig details entry for a SimObject
 ►CCxxConfigFileBaseConfig file wrapper providing a common interface to CxxConfigManager
 CCxxConfigManagerThis class allows a config file to be read into gem5 (generating the appropriate SimObjects) from C++
 CCxxConfigParamsBase for peer classes of SimObjectParams derived classes with parameter modifying member functions
 CCyclesCycles is a wrapper class for representing cycle counts, i.e
 CDataBlock
 CBaseCache::DataUpdateA data contents update is composed of the updated block's address, the old contents, and the new contents
 CTimeBufStruct< Impl >::decodeComm
 CGcn3ISA::Decoder
 CMinor::Decode::DecodeThreadInfoData members after this line are cycle-to-cycle state
 CDefaultBTB
 CDefaultCommit< Impl >DefaultCommit handles single threaded and SMT commit
 CDefaultDecode< Impl >DefaultDecode class handles both single threaded and SMT decode
 CDefaultDecodeDefaultRename< Impl >Struct that defines the information passed from decode to rename
 CDefaultFetch< Impl >DefaultFetch class handles both single threaded and SMT fetch
 CDefaultFetchDefaultDecode< Impl >Struct that defines the information passed from fetch to decode
 CDefaultIEW< Impl >DefaultIEW handles both single threaded and SMT IEW (issue/execute/writeback)
 CDefaultIEWDefaultCommit< Impl >Struct that defines the information passed from IEW to commit
 CDefaultRename< Impl >DefaultRename handles both single threaded and SMT rename
 CDefaultRenameDefaultIEW< Impl >Struct that defines the information passed from rename to IEW
 Csc_gem5::DefaultReportMessages
 CBridge::DeferredPacketA deferred packet stores a packet along with its scheduled transmission time
 CPacketQueue::DeferredPacketA deferred packet, buffered to transmit later
 CSerialLink::DeferredPacketA deferred packet stores a packet along with its scheduled transmission time
 CSimpleMemory::DeferredPacketA deferred packet stores a packet along with its scheduled transmission time
 CPrefetcher::BOP::DelayQueueEntryIn a first implementation of the BO prefetcher, both banks of the RR were written simultaneously when a prefetched line is inserted into the cache
 Ctlm_utils::peq_with_cb_and_phase< OWNER, TYPES >::delta_list
 CDependencyEntry< DynInstPtr >Node in a linked list
 CDependencyGraph< DynInstPtr >Array of linked list that maintains the dependencies between producing instructions and consuming instructions
 Cstd::deque< T >STL deque class
 Cstd::deque< Bridge::DeferredPacket >
 Cstd::deque< DmaDoneEventUPtr >
 Cstd::deque< DmaPort::DmaReqState * >
 Cstd::deque< DynInstPtr >
 Cstd::deque< ElemType >
 Cstd::deque< EventFunctionWrapper >
 Cstd::deque< FetchRequestPtr >
 Cstd::deque< flit * >
 Cstd::deque< GPUDynInstPtr >
 Cstd::deque< iGbReg::RxDesc * >
 Cstd::deque< iGbReg::TxDesc * >
 Cstd::deque< LSQRequestPtr >
 Cstd::deque< MemPacket * >
 Cstd::deque< Minor::ForwardInstData >
 Cstd::deque< Minor::ForwardLineData >
 Cstd::deque< Minor::LSQ::LSQRequest >
 Cstd::deque< Minor::QueuedInst >
 Cstd::deque< Packet >
 Cstd::deque< Prefetcher::BOP::DelayQueueEntry >
 Cstd::deque< Prefetcher::PIF::CompactorEntry >
 Cstd::deque< RequestPort * >
 Cstd::deque< ResponsePort * >
 Cstd::deque< SequencerRequest * >
 Cstd::deque< SerialLink::DeferredPacket >
 Cstd::deque< SimpleIndirectPredictor::HistoryEntry >
 Cstd::deque< SrcType * >
 Cstd::deque< std::pair< GPUDynInstPtr, SCH_STATUS > >
 Cstd::deque< std::pair< Packet, GPUDynInstPtr > >
 Cstd::deque< std::pair< Packet, Wavefront * > >
 Cstd::deque< std::pair< Tick, EthPacketPtr > >
 Cstd::deque< struct FlashDevice::CallBackEntry >
 Cstd::deque< struct UFSHostDevice::SCSIResumeInfo >
 Cstd::deque< struct UFSHostDevice::taskStart >
 Cstd::deque< struct UFSHostDevice::transferInfo >
 Cstd::deque< struct UFSHostDevice::transferStart >
 Cstd::deque< struct UFSHostDevice::UTPTransferReqDesc * >
 Cstd::deque< struct UFSHostDevice::writeToDiskBurst >
 Cstd::deque< T * >
 Cstd::deque< Tick >
 Cstd::deque< tlm::tlm_analysis_if< T > * >
 Cstd::deque< tlm::tlm_generic_payload * >
 Cstd::deque< TriggerQueue::ValType >
 Cstd::deque< uint8_t * >
 Cstd::deque< uint8_t >
 ►CArmISA::TableWalker::DescriptorBase
 ►CRealViewCtrl::Device
 CPciHost::DeviceInterfaceCallback interface from PCI devices to the host
 CItsCommand::DispatchEntryDispatch entry is a metadata struct which contains information about the command (like the name) and the function object implementing the command
 CStats::DistData
 CDistHeaderPkt
 CStats::DistPrint
 CStats::DistProxy< Stat >
 CStats::DistStorTemplatized storage and interface for a distribution stat
 CHSAPacketProcessor::dma_series_ctxCalls getCurrentEntry once the queueEntry has been dmaRead
 CCopyEngineReg::DmaDesc
 CDMARequest
 CDmesgEntry
 Cdp_regsEthernet device registers
 Cdp_rom
 ►CDrainableInterface for objects that might require draining before checkpointing
 CDrainManager
 CDRAMPowerDRAMPower is a standalone tool which calculates the power consumed by a DRAM in the system
 CDRAMSim2WrapperWrapper class to avoid having DRAMSim2 names like ClockDomain etc clashing with the normal gem5 world
 CDRAMsim3WrapperWrapper class to avoid having DRAMsim3 names like ClockDomain etc clashing with the normal gem5 world
 CTraceCPU::ElasticDataGenThe elastic data memory request generator to read protobuf trace containing execution trace annotated with data and ordering dependencies
 Ctlm_utils::time_ordered_list< PAYLOAD >::element
 CEmbeddedPyBind
 CEmbeddedPython
 Cm5::Coroutine< Arg, Ret >::Empty
 CX86ISA::EmulEnv
 Csc_gem5::enable_if< Cond, T >
 Csc_gem5::enable_if< true, T >
 CGuestABI::enable_if_t< std::is_integral< Integer >::value &&(sizeof(Integer)< sizeof(uint32_t))> >
 CGuestABI::enable_if_t< std::is_integral< Integer >::value &&(sizeof(Integer)<=8)> >
 CExtensionPool< T >::entry
 CIniFile::EntryA single key/value pair
 CSMMUTLB::Entry
 CARMArchTLB::Entry
 CIPACache::Entry
 CWalkCache::Entry
 CConfigCache::Entry
 CEmulationPageTable::Entry
 CEtherSwitch::Interface::PortFifo::EntryOrder
 CExpectedMap< RespType, DataType >::ExpectedState< Type >::EnumClassHash
 CEpisode
 ►Ceth_addr
 ►Ceth_hdr
 CEthPacketData
 CNet::EthPtr
 Csc_gem5::Event
 ►CEventBaseCommon base class for Event and GlobalEvent, so they can share flag and priority definitions and accessor functions
 CHSADriver::EventList
 ►CEventManager
 CEventQueueQueue of events sorted in time order
 CGenericTimer::CoreTimers::EventStream
 CHSADriver::EventTableEntry
 ►Cexception
 ►Csc_gem5::ExceptionWrapperBase
 ►CExecContextThe ExecContext is an abstract base class the provides the interface used by the ISA to manipulate the state of the CPU model
 CExecStage
 CMinor::Execute::ExecuteThreadInfo
 CExpectedMap< RespType, DataType >
 CExpectedMap< RespType, DataType >::ExpectedState< Type >
 CExpectedMap< RespType, DataType >::ExpectedState< DataType >
 CExpectedMap< RespType, DataType >::ExpectedState< RespType >
 CExtensionPool< T >
 CExtensionPool< MultiSocketSimpleSwitchAT::ConnectionInfo >
 CX86ISA::ExtMachInst
 CCompressor::DictionaryCompressor< T >::Factory< Head, Tail >Create a factory to determine if input matches a pattern
 CCompressor::DictionaryCompressor< T >::Factory< Head >Specialization to end the recursion
 ►Cfalse_type
 ►CFaultBase
 CSparcISA::SparcFaultBase::FaultVals
 CArmISA::ArmFault::FaultVals
 CMipsISA::MipsFaultBase::FaultVals
 CLinux::fd_set
 CFDArray
 CMinor::Fetch1::Fetch1ThreadInfoStage cycle-by-cycle state
 CMinor::Fetch2::Fetch2ThreadInfoData members after this line are cycle-to-cycle state
 CFetchUnit::FetchBufDescFetch buffer descriptor
 CFetchStage
 CFetchUnit
 ►CFiberThis class represents a fiber, which is a light weight sort of thread which is cooperatively scheduled and runs sequentially with other fibers, swapping in and out of a single actual thread of execution
 CFifo< T >Simple FIFO implementation backed by a circular buffer
 CFifo< uint8_t >
 ►CFIFOReplData
 CBmpWriter::FileHeader
 CMultiperspectivePerceptron::FilterEntryEntry of the branch filter
 CTraceCPU::FixedRetryGenGenerator to read protobuf trace containing memory requests at fixed timestamps, perform flow control and issue memory requests
 ►CDebug::Flag
 CFlags< T >Wrapper that groups a few flag bits under the same undelying container
 CFlags< FlagsStorage >
 CFlags< FlagsType >
 CFlags< FlagsType >< FlagsType >
 ►Cflit
 CflitBuffer
 CFloat16
 Ctlm_utils::fn_container< signature >
 CTAGEBase::FoldedHistory
 Ccp::Format
 CMinor::ForwardInstDataForward flowing data between Fetch2,Decode,Execute carrying a packet of instructions of a width appropriate to the configured stage widths
 CMinor::ForwardLineDataLine fetch data in the forward direction
 CVncServer::FrameBufferRect
 CVncServer::FrameBufferUpdate
 CVncInput::FrameBufferUpdateReq
 CDefaultRename< Impl >::FreeEntriesStructures whose free entries impact the amount of instructions that can be renamed
 CFUPool::FUIdxQueueClass that implements a circular queue to hold FU indices
 ►CFunctionalRequestProtocol
 ►CFunctionalResponseProtocol
 CFunctionProfile
 ►CFuncUnit
 CFutexKeyFutexKey class defines an unique identifier for a particular futex in the system
 CFXSave
 CBaseRemoteGDB::GdbCommand
 CGenericSatCounter< T >Implements an n bit saturating counter and provides methods to increment, decrement, and read it
 CGenericSatCounter< uint32_t >
 CGenericSatCounter< uint8_t >
 ►CGenericSyscallABI
 ►Cgicv3_comms_fw_if
 CGlobalMemPipeline
 ►CGPUExecContext
 CGcn3ISA::GPUISA
 ►CGPUStaticInstFlags
 CTraceCPU::ElasticDataGen::GraphNodeThe struct GraphNode stores an instruction in the trace file
 ►CStats::GroupStatistics container
 CExternalMaster::Handler
 ►CExternalSlave::Handler
 CTraceCPU::ElasticDataGen::HardwareResourceModels structures that hold the in-flight nodes
 ►Chash
 Cstd::hash< BasicBlockRange >
 Cstd::hash< ChannelAddr >
 Cstd::hash< FutexKey >The unordered_map structure needs the parenthesis operator defined for std::hash if a user defined key is used
 Cstd::hash< MachineID >
 Cstd::hash< RegId >
 Cstd::hash< X86ISA::ExtMachInst >
 CUFSHostDevice::HCIMemHost Controller Interface This is a set of registers that allow the driver to control the transactions to the flash devices
 CDistHeaderPkt::Header
 CVirtQueue::VirtRing< T >::Header
 CHistogram
 CSimpleIndirectPredictor::HistoryEntry
 ►CMultiperspectivePerceptron::HistorySpecBase class to implement the predictor tables
 CStats::HistStorTemplatized storage and interface for a histogram stat
 CGicv3CPUInterface::hppi_t
 Chsa_agent_dispatch_packet_sAgent dispatch packet
 Chsa_agent_sStruct containing an opaque handle to an agent, a device that participates in the HSA memory model
 Chsa_barrier_and_packet_sBarrier-AND packet
 Chsa_barrier_or_packet_sBarrier-OR packet
 Chsa_cache_sCache handle
 Chsa_callback_data_sApplication data handle that is passed to the serialization and deserialization functions
 Chsa_code_object_reader_sCode object reader handle
 Chsa_code_object_sStruct containing an opaque handle to a code object, which contains ISA for finalized kernels and indirect functions together with information about the global or readonly segment variables they reference
 Chsa_code_symbol_sCode object symbol handle
 Chsa_dim3_sThree-dimensional coordinate
 Chsa_executable_sStruct containing an opaque handle to an executable, which contains ISA for finalized kernels and indirect functions together with the allocated global or readonly segment variables they reference
 Chsa_executable_symbol_sExecutable symbol handle
 Chsa_isa_sInstruction set architecture
 Chsa_kernel_dispatch_packet_sAQL kernel dispatch packet
 Chsa_loaded_code_object_sLoaded code object handle
 Chsa_packet_header_s
 Chsa_queue_sUser mode queue
 Chsa_region_sA memory region represents a block of virtual memory with certain properties
 Chsa_signal_group_sGroup of signals
 Chsa_signal_sSignal handle
 Chsa_wavefront_sWavefront handle
 CHSAQueueDescriptor
 CHSAQueueEntry
 CHUFFMTBL_ENTRY
 CHWScheduler
 Csc_dt::ieee_double
 Csc_dt::ieee_float
 CTimeBufStruct< Impl >::iewComm
 ►CLoader::ImageFile
 CLoader::ImageFileData
 ►CImgWriter
 CGcn3ISA::InFmt_DS
 CGcn3ISA::InFmt_DS_1
 CGcn3ISA::InFmt_EXP
 CGcn3ISA::InFmt_EXP_1
 CGcn3ISA::InFmt_FLAT
 CGcn3ISA::InFmt_FLAT_1
 CGcn3ISA::InFmt_INST
 CGcn3ISA::InFmt_MIMG
 CGcn3ISA::InFmt_MIMG_1
 CGcn3ISA::InFmt_MTBUF
 CGcn3ISA::InFmt_MTBUF_1
 CGcn3ISA::InFmt_MUBUF
 CGcn3ISA::InFmt_MUBUF_1
 CGcn3ISA::InFmt_SMEM
 CGcn3ISA::InFmt_SMEM_1
 CGcn3ISA::InFmt_SOP1
 CGcn3ISA::InFmt_SOP2
 CGcn3ISA::InFmt_SOPC
 CGcn3ISA::InFmt_SOPK
 CGcn3ISA::InFmt_SOPP
 CGcn3ISA::InFmt_VINTRP
 CGcn3ISA::InFmt_VOP1
 CGcn3ISA::InFmt_VOP2
 CGcn3ISA::InFmt_VOP3
 CGcn3ISA::InFmt_VOP3_1
 CGcn3ISA::InFmt_VOP3_SDST_ENC
 CGcn3ISA::InFmt_VOP_DPP
 CGcn3ISA::InFmt_VOP_SDWA
 CGcn3ISA::InFmt_VOPC
 ►CStats::Info
 CSinic::Regs::Info
 ►CStats::InfoAccess
 CBmpWriter::InfoHeaderV1
 CIniFileThis class represents the contents of a ".ini" file
 CArmSemihosting::InPlaceArg
 CMinor::Latch< Data >::InputEncapsulate wires on either input or output of the latch
 CNetworkInterface::InputPort
 CTraceCPU::ElasticDataGen::InputStreamThe InputStream encapsulates a trace file and the internal buffers and populates GraphNodes based on the input
 CTraceGen::InputStreamThe InputStream encapsulates a trace file and the internal buffers and populates TraceElements based on the input
 CTraceCPU::FixedRetryGen::InputStreamThe InputStream encapsulates a trace file and the internal buffers and populates TraceElements based on the input
 Ctlm_utils::instance_specific_extension_accessor
 Ctlm_utils::instance_specific_extension_container
 Ctlm_utils::instance_specific_extension_container_pool
 Ctlm_utils::instance_specific_extensions_per_accessor
 CX86ISA::Decoder::InstBytes
 ►CInstDecoder
 ►CTrace::TarmacBaseRecord::InstEntryTARMAC instruction trace record
 ►CInstEntry
 CElasticTrace::InstExecInfo
 CGcn3ISA::InstFormat
 CMinor::InstIdId for lines and instructions
 Cinstr
 ►CTrace::InstRecord
 CInstResult
 CInstructionQueue< Impl >A standard instruction queue class
 CIob::IntBusy
 CIob::IntCtl
 CX86ISA::SMBios::SMBiosTable::SMBiosHeader::IntermediateHeader
 CMultiSocketSimpleSwitchAT::internalPEQTypes
 CIob::IntMan
 CArmV8KvmCPU::IntRegInfoMapping between integer registers in gem5 and KVM
 ►Cip6_hdr
 CNet::ip6_opt_dstopts
 CNet::ip6_opt_fragment
 ►CNet::ip6_opt_hdr
 CNet::ip6_opt_routing_type2
 CNet::Ip6Ptr
 ►Cip_hdr
 ►Cip_opt
 ►CNet::IpAddress
 CNet::IpPtr
 CSimpleIndirectPredictor::IPredEntry
 Csc_gem5::is_const< T >
 Csc_gem5::is_const< const T >
 Csc_gem5::is_more_const< CT, T >
 Csc_gem5::is_same< T, U >
 Csc_gem5::is_same< T, T >
 ►Ctlm_utils::ispex_base
 CIssueStruct< Impl >
 CCircularQueue< T >::iteratorIterator to the circular queue
 ►Citerator
 CItsAction
 CVncInput::KeyEventMessage
 Ckfd_event_data
 Ckfd_hsa_memory_exception_data
 Ckfd_ioctl_alloc_memory_of_gpu_args
 Ckfd_ioctl_alloc_memory_of_scratch_args
 Ckfd_ioctl_create_event_args
 Ckfd_ioctl_create_queue_args
 Ckfd_ioctl_cross_memory_copy_args
 Ckfd_ioctl_dbg_address_watch_args
 Ckfd_ioctl_dbg_register_args
 Ckfd_ioctl_dbg_unregister_args
 Ckfd_ioctl_dbg_wave_control_args
 Ckfd_ioctl_destroy_event_args
 Ckfd_ioctl_destroy_queue_args
 Ckfd_ioctl_free_memory_of_gpu_args
 Ckfd_ioctl_get_clock_counters_args
 Ckfd_ioctl_get_dmabuf_info_args
 Ckfd_ioctl_get_process_apertures_args
 Ckfd_ioctl_get_process_apertures_new_args
 Ckfd_ioctl_get_tile_config_args
 Ckfd_ioctl_get_version_args
 Ckfd_ioctl_import_dmabuf_args
 Ckfd_ioctl_ipc_export_handle_args
 Ckfd_ioctl_ipc_import_handle_args
 Ckfd_ioctl_map_memory_to_gpu_args
 Ckfd_ioctl_open_graphic_handle_args
 Ckfd_ioctl_reset_event_args
 Ckfd_ioctl_set_cu_mask_args
 Ckfd_ioctl_set_event_args
 Ckfd_ioctl_set_memory_policy_args
 Ckfd_ioctl_set_process_dgpu_aperture_args
 Ckfd_ioctl_set_trap_handler_args
 Ckfd_ioctl_unmap_memory_from_gpu_args
 Ckfd_ioctl_update_queue_args
 Ckfd_ioctl_wait_events_args
 Ckfd_memory_exception_failure
 Ckfd_memory_range
 Ckfd_process_device_apertures
 CKvmKVM parent interface
 CArmKvmCPU::KvmCoreMiscRegInfo
 CKvmDeviceKVM device wrapper
 CKvmFPReg
 CArmKvmCPU::KvmIntRegInfo
 CPacket::PrintReqState::LabelStackEntryAn entry in the label stack
 CLaneData< LS >LaneSize is an abstraction of a LS byte value for the execution and thread contexts to handle values just depending on its width
 CAddressManager::LastWriter
 CMinor::Latch< Data >Wraps a MinorBuffer with Input/Output interfaces to ensure that units within the model can only see the right end of buffers between them
 CMinor::Latch< Minor::BranchData >
 CMinor::Latch< Minor::ForwardInstData >
 CMinor::Latch< Minor::ForwardLineData >
 CLdsChunkThis represents a slice of the overall LDS, intended to be associated with an individual workgroup
 CLinearEquationThis class describes a linear equation with constant coefficients
 CLinearSystem
 CEtherLink::Link
 CLinkEntry
 CLinkOrder
 Cstd::list< T >STL list class
 Cstd::list< AddrRange >
 Cstd::list< ArmISA::TableWalker::WalkerState * >
 Cstd::list< BasicSignal >
 Cstd::list< CacheBlk::Lock >
 Cstd::list< CxxConfigManager::Renaming >
 Cstd::list< DefaultRename::RenameHistory >
 Cstd::list< DeferredPacket >
 Cstd::list< DynInstPtr >
 Cstd::list< EtherInt * >
 Cstd::list< Event * >
 Cstd::list< InstructionQueue::ListOrderEntry >
 Cstd::list< InstSeqNum >
 Cstd::list< int >
 Cstd::list< iterator >
 Cstd::list< LabelStackEntry >
 Cstd::list< ListOrderEntry >
 Cstd::list< LockedAddr >
 Cstd::list< NodeSeqNum >
 Cstd::list< PacketFifoEntry >
 Cstd::list< PCEvent * >
 Cstd::list< Prefetcher::Base * >
 Cstd::list< Prefetcher::Queued::DeferredPacket >
 Cstd::list< RequestorID >
 Cstd::list< RiscvISA::Walker::WalkerState * >
 Cstd::list< ScEvent * >
 Cstd::list< SimObject * >
 Cstd::list< SimpleMemory::DeferredPacket >
 Cstd::list< SMMUProcess * >
 Cstd::list< SMMUTranslationProcess * >
 Cstd::list< SparcISA::TlbEntry * >
 ►Cstd::list< std::function< void()> >
 Cstd::list< std::pair< int, int > >
 ►Cstd::list< Target >
 Cstd::list< ThreadID >
 Cstd::list< Throttle >
 Cstd::list< Tick >
 Cstd::list< TimeSlot * >
 Cstd::list< TlbEntry * >
 Cstd::list< Trace::TarmacParserRecord::ParserRegEntry >
 Cstd::list< TraceCPU::ElasticDataGen::ReadyNode >
 Cstd::list< Transaction >
 Cstd::list< unsigned >
 Cstd::list< VMA >
 Cstd::list< WriteCluster >
 Cstd::list< X86ISA::Walker::WalkerState * >
 ►CListenSocket
 ►Csc_gem5::ListNode
 CInstructionQueue< Impl >::ListOrderEntryEntry for the list age ordering by op class
 CProcess::LoaderEach instance of a Loader subclass will have a chance to try to load an object file when tryLoaders is called
 CLogger::Loc
 CMultiperspectivePerceptron::LocalHistoriesLocal history entries, each enty contains the history of directions taken by a given branch
 CLocalMemPipeline
 ►CLocatedMaskedPattern
 CCacheBlk::LockRepresents that the indicated thread context has a "lock" on the block, in the LL/SC sense
 CLockedAddrLocked address class that represents a physical address and a context id
 CLogger
 ►CTrace::LoggerDebug logging base class
 CX86ISA::LongModePTE
 CLoopPredictor::LoopEntry
 CLSQ< Impl >
 ►CLSQUnit< Impl >::LSQEntry
 ►CLSQSenderState
 CLSQUnit< Impl >Class that implements the actual LQ and SQ for each specific thread
 Cltseqnum
 CUFSHostDevice::LUNInfoLogic unit information structure
 CX86Linux32::M5_ATTR_PACKED
 CX86ISA::RemoteGDB::AMD64GdbRegCache::M5_ATTR_PACKED
 CArmISA::RemoteGDB::AArch32GdbRegCache::M5_ATTR_PACKED
 CArmISA::RemoteGDB::AArch64GdbRegCache::M5_ATTR_PACKED
 CMachineID
 CPCEventQueue::MapCompare
 CVMA::MappedFileBufferMappedFileBuffer is a wrapper around a region of host memory backed by a file
 ►CMaskedPattern
 ►CMaskedValuePattern
 CMathExpr
 CMatrix64x12
 CMemBackdoor
 CMemCmd
 CMemDepUnit< MemDepPred, Impl >::MemDepEntryMemory dependence entries that track memory operations, marking when the instruction is ready to execute and what instructions depend upon it
 CMemDepUnit< MemDepPred, Impl >Memory dependency unit class
 ►CTrace::TarmacBaseRecord::MemEntryTARMAC memory access trace record (stores only)
 ►CMemEntry
 CLoader::MemoryImage
 CKvmVM::MemorySlotStructures tracking memory slots
 CMemPacketA memory packet stores packets along with the timestamp of when the packet entered the queue, and also the decoded address
 CKvmVM::MemSlot
 CSCMI::Message
 ►CMessage
 CX86ISAInst::MicrocodeRom
 CMipsAccess
 CArmV8KvmCPU::MiscRegInfoMapping between misc registers in gem5 and registers in KVM
 CArmISA::ISA::MiscRegLUTEntryMiscReg metadata
 CArmISA::ISA::MiscRegLUTEntryInitializer
 Csc_gem5::Module
 ►CMultiperspectivePerceptron::MPPBranchInfoBranch information data
 CMSICAP
 CMSIX
 CMSIXCAP
 CMSIXPbaEntry
 CMSIXTable
 Ctlm_utils::multi_init_base_if< TYPES >
 ►Ctlm_utils::multi_init_base_if< tlm::tlm_base_protocol_types >
 Ctlm_utils::multi_target_base_if< TYPES >
 ►Ctlm_utils::multi_target_base_if< tlm::tlm_base_protocol_types >
 Ctlm_utils::multi_to_multi_bind_base< TYPES >
 ►Ctlm_utils::multi_to_multi_bind_base< tlm::tlm_base_protocol_types >
 CInstResult::MultiResult
 Cmy_extended_payload_types
 ►CNamed
 CNetDest
 CMinor::NoBubbleTraits< ElemType >..
 ►CStats::NodeBase class for formula statistic node
 CMathExpr::Node
 CTrie< Key, Value >::Node
 CCompressor::Encoder::Huffman::NodeNode for the Huffman tree
 CStackDistCalc::NodeNode which takes form of Leaf, INode or Root
 CCompressor::Encoder::Huffman::NodeComparatorEntries are not inserted directly into the tree
 CTCPIface::NodeInfoCompute node info and storage for the very first connection from each node (used by the switch)
 Cns_desc32
 Cns_desc64
 CO3CPUImplImplementation specific struct that defines several key types to the CPU, the stages within the CPU, the time buffers, and the DynInst
 CO3ThreadContext< Impl >Derived ThreadContext class for use with the O3CPU
 CO3ThreadState< Impl >Class that has various thread state, such as the status, the current instruction being processed, whether or not the thread has a trap pending or is being externally updated, the ThreadContext pointer, etc
 Csc_gem5::Object
 ►CLoader::ObjectFileFormat
 CObjectMatchObjectMatch contains a vector of expressions
 Coperand
 ►CGcn3ISA::Operand
 ►COperatingSystemThis class encapsulates the types, structures, constants, functions, and syscall-number mappings specific to an operating system syscall interface
 CMathExpr::OpSearch
 CStats::OpString< Op >
 CStats::OpString< std::divides< Result > >
 CStats::OpString< std::minus< Result > >
 CStats::OpString< std::modulus< Result > >
 CStats::OpString< std::multiplies< Result > >
 CStats::OpString< std::negate< Result > >
 CStats::OpString< std::plus< Result > >
 CGcn3ISA::OpTraits< T >Convenience traits so we can automatically infer the correct FP type without looking at the number of dwords (i.e., to determine if we need a float or a double when creating FP constants)
 CGcn3ISA::OpTraits< ScalarRegF64 >
 CGcn3ISA::OpTraits< ScalarRegU64 >
 ►CStats::Output
 CMinor::Latch< Data >::Output
 COutputDirectoryInterface for creating files in a gem5 output directory
 CNetworkInterface::OutputPort
 ►COutputStream
 CTesterThread::OutstandingReq
 COutVcState
 CP9MsgHeader
 CP9MsgInfo
 CPacketFifo
 CPacketFifoEntry
 CProbePoints::PacketInfoA struct to hold on to the essential fields from a packet, so that the packet and underlying request can be safely passed on, and consequently modified or even deleted
 CFlashDevice::PageMapEntryEvery logical address maps to a physical block and a physical page
 CSparcISA::PageTableEntry
 ►CPageTableOps
 Cstd::pair< X, Y >STL pair class
 Cstd::pair< Addr, Addr >
 Cstd::pair< flit_stage, Tick >
 Cstd::pair< GPUDynInstPtr, SCH_STATUS >
 Cstd::pair< int, AtomicOpFunctor * >
 Cstd::pair< int, int >
 Cstd::pair< Packet, GPUDynInstPtr >
 Cstd::pair< Packet, Wavefront * >
 Cstd::pair< std::string, sc_gem5::VcdTraceValBase * >
 Cstd::pair< TCPIface::NodeInfo, int >
 Cstd::pair< Tick, EthPacketPtr >
 Cstd::pair< tlm::tlm_dmi, bool >
 Cstd::pair< VC_state_type, Tick >
 Cstd::pair< Wavefront *, bool >
 CFALRU::PairHashHash table type mapping addresses to cache block pointers
 CCxxConfigDirectoryEntry::ParamDesc
 CParseParam< T, Enable >
 CParseParam< BitUnionType< T > >
 CParseParam< bool >
 CParseParam< std::string >
 CParseParam< T, decltype(to_number("", std::declval< T & >()), void())>
 CParseParam< T, std::enable_if_t< std::is_base_of< typename RegisterBankBase::RegisterBaseBase, T >::value > >
 ►CCompressor::DictionaryCompressor< T >::PatternThe compressed data is composed of multiple pattern entries
 ►CPattern
 CPrefetcher::SignaturePath::PatternStrideEntryA stride entry with its counter
 Cpcap_file_header
 Cpcap_pkthdr
 CLinux::pcb_struct
 ►CPCEvent
 ►CPCEventScope
 CPciBusAddr
 CPrefetcher::Stride::PCTableInfoInformation used to create a new PC table
 CPendingWriteInst
 CPerfectCacheLineState< ENTRY >
 CPerfectCacheMemory< ENTRY >
 CPerfKvmCounterAn instance of a performance counter
 CPerfKvmCounterConfigPerfEvent counter configuration
 CPersistentTable
 CPersistentTableEntry
 CPhysRegFileSimple physical register file class
 ►CPipeStageIFace
 CPixelInternal gem5 representation of a Pixel
 CPixelConverterConfigurable RGB pixel converter
 CVncInput::PixelEncodingsMessage
 CVncInput::PixelFormat
 CVncInput::PixelFormatMessage
 CPlicOutputNOTE: This implementation of CLINT is based on the SiFive U54MC datasheet: https://sifive.cdn.prismic.io/sifive/fab000f6- 0e07-48d0-9602-e437d5367806_sifive_U54MC_rtl_ full_20G1.03.00_manual.pdf
 CPMCAP
 ►CArmISA::PMU::PMUEventEvent definition base class
 CPngWriter::PngPixel24Png Pixel type: not containing padding
 CPngWriter::PngStructHandle
 CVncInput::PointerEventMessage
 CPollQueue
 ►CPortPorts are used to interface objects to each other
 Csc_gem5::Port
 CCxxConfigDirectoryEntry::PortDescSimilar to ParamDesc to describe ports
 CInstructionQueue< Impl >::pqCompareStruct for comparing entries to be added to the priority queue
 CPrdEntry
 CPrdTableEntry
 CBPredUnit::PredictorHistory
 CPrefetchEntry
 CPrefetcher::Base::PrefetchInfoClass containing the information needed by the prefetch to train and generate new prefetch requests
 CGuestABI::Preparer< ABI, Role, Type, Enabled >
 CGuestABI::Preparer< ABI, Role, Type, decltype((void)&Role< ABI, Type >::prepare)>
 Ccp::Print
 ►CPrintableAbstract base class for objects which support being printed to a stream for debugging
 ►CProbeListenerProbeListener base class; here to simplify things like containers containing multiple types of ProbeListener
 CProbeManagerProbeManager is a conduit class that lives on each SimObject, and is used to match up probe listeners with probe points
 CProbePointProbeListener base class; again used to simplify use of ProbePoints in containers and used as to define interface for adding removing listeners to the ProbePoint
 CProbePointArg< Arg >ProbePointArg generates a point for the class of Arg
 CProbePointArg< BaseCache::DataUpdate >
 CProbePointArg< bool >
 CProbePointArg< DynInstPtr >
 CProbePointArg< Packet >
 CProbePointArg< RequestPtr >
 CProbePointArg< std::pair >
 CProbePointArg< std::pair< DynInstPtr, Packet > >
 CProbePointArg< std::pair< SimpleThread *, const RefCountingPtr > >
 CProbePointArg< Temperature >
 Ctlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process::process_handle_class
 Ctlm_utils::simple_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process::process_handle_class
 Ctlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process::process_handle_list
 Ctlm_utils::simple_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process::process_handle_list
 ►Csc_gem5::ProcessFuncWrapper
 CProfileNode
 CProfiler
 ►CSCMI::Protocol
 ►CProtoStreamA ProtoStream provides the shared functionality of the input and output streams
 CProxyPtr< void, Proxy >
 CProxyPtrBuffer< Proxy >
 CArmISA::PTE
 CMipsISA::PTE
 CPowerISA::PTE
 CPXCAP
 Csc_gem5::PythonInitFunc
 Csc_gem5::PythonReadyFunc
 CQTIsaac< ALPHA >
 CQueueContext
 CMinor::QueuedInstContainer class to box instructions in the FUs to make those queues have correct bubble behaviour when stepped
 ►CQoS::QueuePolicyQoS Queue Policy
 CQTIsaac< ALPHA >::randctx
 CTraceCPU::ElasticDataGen::ReadyNodeStruct to store a ready-to-execute node and its execution tick
 ►CRefCountedDerive from RefCounted if you want to enable reference counting of this class
 CRefCountingPtr< T >If you want a reference counting pointer to a mutable object, create it like this:
 CRefCountingPtr< MinorDynInst >
 CRefCountingPtr< StaticInst >
 CiGbReg::Regs::Reg< T >
 CCopyEngineReg::Reg< T >
 ►CCopyEngineReg::Reg< uint16_t >
 ►CiGbReg::Regs::Reg< uint32_t >
 ►CCopyEngineReg::Reg< uint32_t >
 ►CCopyEngineReg::Reg< uint64_t >
 ►CiGbReg::Regs::Reg< uint64_t >
 ►CCopyEngineReg::Reg< uint8_t >
 ►CTrace::TarmacBaseRecord::RegEntryTARMAC register trace record
 ►CRegEntry
 ►CRegIdRegister ID: describe an architectural register with its class and index
 CPrefetcher::STeMS::RegionMissOrderBufferEntryData type of the Region Miss Order Buffer entry
 ►CRegister
 ►CRegister32
 ►CRegisterBankBase
 ►CRegisterBase
 ►CRegisterBankBase::RegisterBaseBase
 ►CRegisterManagerPolicyRegister Manager Policy abstract class
 CFVPBasePwrCtrl::Registers
 CBaseDynInst< Impl >::RegsCollect register related information into a single struct
 Csc_gem5::remove_const< T >
 Csc_gem5::remove_const< const T >
 Csc_gem5::remove_special_fptr< T >
 Csc_gem5::remove_special_fptr< special_result &(*)(T)>
 CTimeBufStruct< Impl >::renameComm
 CDefaultRename< Impl >::RenameHistoryHolds the information for each destination register rename
 CRenameMode< ISA >Helper structure to get the vector register mode for a given ISA
 CRenameMode< ArmISA::ISA >
 CCxxConfigManager::RenamingName substitution when instantiating any object whose name starts with fromPrefix
 ►CRepeatedValuePattern
 ►CReplaceableEntryA replaceable entry is a basic entry in a 2d table-like structure that needs to have replacement functionality
 ►CReplacementPolicy::ReplacementDataThe replacement data needed by replacement policies
 CMinor::ReportIFInterface class for data with reporting/tracing facilities
 Csc_gem5::ReportMsgInfo
 Csc_gem5::ReportSevInfo
 CMinor::ReportTraitsAdaptor< ElemType >...ReportTraits are trait classes with the same functionality as ReportIF, but with elements explicitly passed into the report..
 CMinor::ReportTraitsPtrAdaptor< PtrType >A similar adaptor but for elements held by pointer ElemType should implement ReportIF
 CSnoopFilter::ReqLookupResultA request lookup must be followed by a call to finishRequest to inform the operation's success
 CRequest
 CUFSHostDevice::UTPTransferReqDesc::RequestDescHeaderStruct RequestDescHeader dword0: Descriptor Header DW0 dword1: Descriptor Header DW1 dword2: Descriptor Header DW2 dword3: Descriptor Header DW3
 CRequestorInfoData about a specific requestor
 ►CMinor::ReservableBase class for space reservation requestable objects
 Csc_gem5::Reset
 Csc_core::sc_spawn_options::Reset< T >
 Csc_core::sc_spawn_options::Reset< const sc_core::sc_in< bool > >
 Csc_core::sc_spawn_options::Reset< const sc_core::sc_inout< bool > >
 Csc_core::sc_spawn_options::Reset< const sc_core::sc_out< bool > >
 Csc_core::sc_spawn_options::Reset< const sc_core::sc_signal_in_if< bool > >
 CGuestABI::Result< ABI, Ret, Enabled >
 ►CGuestABI::Result< Aapcs32, Composite >
 CGuestABI::Result< Aapcs32, Composite, typename std::enable_if_t< IsAapcs32Composite< Composite >::value > >
 CGuestABI::Result< Aapcs32, Float, typename std::enable_if_t< std::is_floating_point< Float >::value > >
 ►CGuestABI::Result< Aapcs32, Integer >
 CGuestABI::Result< Aapcs32, Integer, typename std::enable_if_t< std::is_integral< Integer >::value &&(sizeof(Integer)==sizeof(uint32_t))> >
 CGuestABI::Result< Aapcs32, Integer, typename std::enable_if_t< std::is_integral< Integer >::value &&(sizeof(Integer)==sizeof(uint64_t))> >
 CGuestABI::Result< Aapcs32Vfp, Float, typename std::enable_if_t< std::is_floating_point< Float >::value > >
 CGuestABI::Result< Aapcs32Vfp, HA, typename std::enable_if_t< IsAapcs32HomogeneousAggregate< HA >::value > >
 CGuestABI::Result< Aapcs64, Composite, typename std::enable_if_t< IsAapcs64Composite< Composite >::value &&!IsAapcs64Hxa< Composite >::value > >
 CGuestABI::Result< Aapcs64, HA, typename std::enable_if_t< IsAapcs64Hxa< HA >::value > >
 CGuestABI::Result< ABI, SyscallReturn, typename std::enable_if_t< std::is_base_of< ArmISA::EmuFreebsd::BaseSyscallABI, ABI >::value > >
 CGuestABI::Result< ABI, SyscallReturn, typename std::enable_if_t< std::is_base_of< ArmISA::EmuLinux::BaseSyscallABI, ABI >::value > >
 CGuestABI::Result< ABI, SyscallReturn, typename std::enable_if_t< std::is_base_of< SparcISA::SEWorkload::BaseSyscallABI, ABI >::value > >
 CGuestABI::Result< ABI, SyscallReturn, typename std::enable_if_t< std::is_base_of< X86Linux::SyscallABI, ABI >::value > >
 CGuestABI::Result< ABI, void >
 CGuestABI::Result< ArmSemihosting::Abi32, ArmSemihosting::RetErrno >
 CGuestABI::Result< ArmSemihosting::Abi64, ArmSemihosting::RetErrno >
 CGuestABI::Result< MipsISA::SEWorkload::SyscallABI, SyscallReturn >
 CGuestABI::Result< PowerISA::SEWorkload::SyscallABI, SyscallReturn >
 CGuestABI::Result< RiscvISA::SEWorkload::SyscallABI, SyscallReturn >
 CGuestABI::Result< TestABI_1D, int >
 CGuestABI::Result< TestABI_1D, Ret, typename std::enable_if_t< std::is_floating_point< Ret >::value > >
 CGuestABI::Result< TestABI_2D, int >
 CGuestABI::Result< TestABI_2D, Ret, typename std::enable_if_t< std::is_floating_point< Ret >::value > >
 CGuestABI::Result< TestABI_Prepare, Ret >
 CGuestABI::Result< X86PseudoInstABI, T >
 CGuestABI::ResultStorer< ABI, Ret, Enabled >
 CGuestABI::ResultStorer< ABI, Ret, typename std::enable_if_t< std::is_same< void(*)(ThreadContext *, const Ret &, typename ABI::State &), decltype(&Result< ABI, Ret >::store)>::value > >
 CReturnAddrStackReturn address stack class, implements a simple RAS
 Crgb_t
 CArmFreebsd32::rlimitLimit struct for getrlimit/setrlimit
 CArmFreebsd64::rlimitLimit struct for getrlimit/setrlimit
 CArmLinux32::rlimitLimit struct for getrlimit/setrlimit
 CArmLinux64::rlimitLimit struct for getrlimit/setrlimit
 CLinux::rlimitLimit struct for getrlimit/setrlimit
 COperatingSystem::rlimitLimit struct for getrlimit/setrlimit
 CRiscvLinux32::rlimitLimit struct for getrlimit/setrlimit
 CROB< Impl >ROB class
 CRouteInfo
 CRoutingUnit
 CHSAPacketProcessor::RQLEntry
 CArmFreebsd64::rusageFor getrusage()
 CArmFreebsd32::rusageFor getrusage()
 CArmLinux32::rusageFor getrusage()
 CArmLinux64::rusageFor getrusage()
 CLinux::rusage
 COperatingSystem::rusageFor getrusage()
 CiGbReg::RxDesc
 CStats::SampleStorTemplatized storage and interface for a distribution that calculates mean and variance
 CPrefetcher::SBOOE::Sandbox
 CPrefetcher::SBOOE::SandboxEntry
 ►Csc_core::sc_attr_base
 Csc_core::sc_attr_cltn
 Csc_dp::sc_barrier
 ►Csc_dt::sc_bigint< W >
 ►Csc_dt::sc_biguint< W >
 Csc_core::sc_bind_proxy
 Csc_dt::sc_bit
 Csc_dt::sc_bitref< X >
 Csc_dt::sc_bitref_conv_r< T, Traits >
 Csc_dt::sc_bitref_conv_r< T, sc_proxy_traits< sc_bv_base > >
 Csc_dt::sc_bitref_r< T >
 Csc_dt::sc_bv< W >
 Csc_core::sc_byte_heap
 Csc_dt::sc_concref< X, Y >
 Csc_dt::sc_concref_r< X, Y >
 Csc_dt::sc_context< T >
 Csc_core::sc_curr_proc_info
 ►Csc_core::sc_direct_access< Element >
 ►Csc_core::sc_event
 Csc_core::sc_event_and_expr
 Csc_core::sc_event_and_list
 ►Csc_core::sc_event_finder
 Csc_core::sc_event_or_expr
 Csc_core::sc_event_or_list
 Csc_dt::sc_fixed< W, I, Q, O, N >
 Csc_dt::sc_fixed_fast< W, I, Q, O, N >
 Csc_dt::sc_fxcast_switch
 ►Csc_dt::sc_fxnum
 Csc_dt::sc_fxnum_bitref
 ►Csc_dt::sc_fxnum_fast
 Csc_dt::sc_fxnum_fast_bitref
 Csc_dt::sc_fxnum_fast_observer
 Csc_dt::sc_fxnum_fast_subref
 Csc_dt::sc_fxnum_observer
 Csc_dt::sc_fxnum_subref
 Csc_dt::sc_fxtype_params
 Csc_dt::sc_fxval
 Csc_dt::sc_fxval_fast
 Csc_dt::sc_fxval_fast_observer
 Csc_dt::sc_fxval_observer
 Csc_dt::sc_generic_base< T >
 ►Csc_dt::sc_generic_base< sc_concatref >
 Csc_dt::sc_global< T >
 Csc_core::sc_in< T >
 ►Csc_core::sc_in< sc_dt::sc_lv< W > >
 ►Csc_dt::sc_int< W >
 ►Csc_core::sc_interface
 Csc_core::sc_join
 Csc_dt::sc_length_param
 Csc_dt::sc_logic
 Csc_dt::sc_lv< W >
 Csc_core::sc_member_access< Element, Access >
 Csc_core::sc_mempool
 ►Csc_module
 Csc_core::sc_module_name
 Csc_core::sc_mpobject
 ►Csc_core::sc_object
 Csc_core::sc_process_handle
 Csc_dt::sc_proxy< X >
 ►Csc_dt::sc_proxy< sc_bv_base >
 ►Csc_dt::sc_proxy< sc_lv_base >
 ►Csc_dt::sc_proxy_traits< X >
 Csc_dt::sc_proxy_traits< sc_bv_base >
 ►Csc_dt::sc_proxy_traits< sc_lv_base >
 Csc_core::sc_report_handler
 Csc_core::sc_sensitive
 Csc_core::sc_simcontext
 Csc_core::sc_spawn_options
 Csc_dt::sc_subref< X >
 Csc_dt::sc_subref_r< X >
 Csc_core::sc_time
 Csc_core::sc_time_tuple
 ►Csc_core::sc_trace_file
 Csc_core::sc_trace_params
 Csc_dt::sc_ufixed< W, I, Q, O, N >
 Csc_dt::sc_ufixed_fast< W, I, Q, O, N >
 ►Csc_dt::sc_uint< W >
 Csc_core::sc_user
 ►Csc_dt::sc_value_base
 Csc_core::sc_vector< T >
 Csc_core::sc_vector< svp_gicv3_comms::gicv3_comms_target_socket<> >
 Csc_core::sc_vector_assembly< T, MT >
 Csc_core::sc_vpool< T >
 Csc_core::sc_vpool< sc_core::sc_int_sigref >
 Csc_core::sc_vpool< sc_core::sc_signed_sigref >
 Csc_core::sc_vpool< sc_core::sc_uint_sigref >
 Csc_core::sc_vpool< sc_core::sc_unsigned_sigref >
 Csc_core::sc_vpool< sc_dt::sc_concat_bool >
 Csc_core::sc_vpool< sc_dt::sc_concatref >
 Csc_core::sc_vpool< sc_dt::sc_int_bitref >
 Csc_core::sc_vpool< sc_dt::sc_int_subref >
 Csc_core::sc_vpool< sc_dt::sc_signed_bitref >
 Csc_core::sc_vpool< sc_dt::sc_signed_subref >
 Csc_core::sc_vpool< sc_dt::sc_uint_bitref >
 Csc_core::sc_vpool< sc_dt::sc_uint_subref >
 Csc_core::sc_vpool< sc_dt::sc_unsigned >
 Csc_core::sc_vpool< sc_dt::sc_unsigned_bitref >
 Csc_core::sc_vpool< sc_dt::sc_unsigned_subref >
 Csc_dt::sc_without_context
 CScalarMemPipeline
 CGcn3ISA::ScalarOperand< DataType, Const, NumDwords >
 CGcn3ISA::ScalarOperand< DataType, Const, sizeof(DataType)/sizeof(VecElemU32) >
 CStats::ScalarPrint
 CStats::ScalarProxy< Stat >A proxy class to access the stat at a given index in a VectorBase stat
 ►Csc_gem5::ScEvent
 Csc_gem5::ScExportWrapper< IF >
 Csc_dt::scfx_ieee_double
 Csc_dt::scfx_ieee_float
 Csc_dt::scfx_index
 Csc_dt::scfx_mant
 Csc_dt::scfx_mant_ref
 Csc_dt::scfx_params
 Csc_dt::scfx_pow10
 Csc_dt::scfx_rep
 Csc_dt::scfx_rep_node
 Csc_dt::scfx_string
 Csc_gem5::ScHalt
 Csc_gem5::Scheduler
 CScheduler
 CScheduleStage
 ►CSchedulingPolicyInterface class for the wave scheduling policy
 Csc_gem5::ScInterfaceWrapper< IF >
 CSerializable::ScopedCheckpointSection
 CEventQueue::ScopedMigration
 CEventQueue::ScopedRelease
 CScoreboardImplements a simple scoreboard to track which registers are ready
 CScoreboardCheckStage
 Csc_gem5::ScPortWrapper< IF >
 CUFSHostDevice::SCSIReplySCSI reply structure
 CUFSHostDevice::SCSIResumeInfoAfter a SCSI command has been identified, the SCSI resume function will handle it
 ►CStatisticalCorrector::SCThreadHistory
 ►CSCThreadHistory
 ►Cscx_evs_GIC
 ►Cscx_evs_PL330
 CFastModel::ScxEvsCortexA76x1Types
 CFastModel::ScxEvsCortexA76x2Types
 CFastModel::ScxEvsCortexA76x3Types
 CFastModel::ScxEvsCortexA76x4Types
 CFastModel::ScxEvsCortexR52x1Types
 CFastModel::ScxEvsCortexR52x2Types
 CFastModel::ScxEvsCortexR52x3Types
 CFastModel::ScxEvsCortexR52x4Types
 CIniFile::SectionA section
 CCowDiskImage::Sector
 CX86ISA::SegDescriptorLimit
 CLoader::MemoryImage::Segment
 Csc_core::sc_vector_iter< Element, AccessPolicy >::SelectIter< U >
 Csc_core::sc_vector_iter< Element, AccessPolicy >::SelectIter< const U >
 Csc_core::sc_vector_iter< Element, AccessPolicy >::SelectIter< ElementType >
 CArmISA::SelfDebug
 CArmSemihosting::SemiCallSemihosting call information structure
 ►CPacket::SenderStateA virtual base opaque structure used to hold state associated with the packet (e.g., an MSHR), specific to a SimObject that sees the packet
 Csc_gem5::Port::Sensitivity
 ►Csc_gem5::Sensitivity
 CPrefetcher::STeMS::ActiveGenerationTableEntry::SequenceEntrySequence entry data type
 CSequencerRequest
 ►CSerializableBasic support for object serialization
 CVncServer::ServerCutText
 CVncServer::ServerInitMsg
 CSet
 CShowParam< T, Enabled >
 CShowParam< BitUnionType< T > >
 CShowParam< bool >
 CShowParam< T, std::enable_if_t< std::is_base_of< typename RegisterBankBase::RegisterBaseBase, T >::value > >
 CShowParam< T, std::enable_if_t< std::is_same< char, T >::value||std::is_same< unsigned char, T >::value||std::is_same< signed char, T >::value > >
 ►Csignal_slave_base
 CSignalInterruptDummyProtocolType
 CHSAPacketProcessor::SignalState
 CBitfieldBackend::Signed< Storage, first, last >
 ►CSignExtendedPattern
 ►CSimObjectResolverBase class to wrap object resolving functionality
 CSimpleAddressMapSimple address map implementation for the generic protocol
 CSimpleCPUPolicy< Impl >Struct that defines the key classes to be used by the CPU
 CSimpleFreeListFree list for a single class of registers (e.g., integer or floating point)
 CSimpleRenameMapRegister rename map for a single class of registers (e.g., integer or floating point)
 CX86ISA::SMBios::SMBiosTable::SMBiosHeader
 CSMMUAction
 CSMMUCommand
 CSMMUEvent
 CSMMURegs
 CSMMUSemaphore
 CSMMUSignal
 CSMMUTranslRequest
 ►CSMMUv3BaseCache
 CSNHash
 CSnoopFilter::SnoopItemPer cache line item tracking a bitmask of ResponsePorts who have an outstanding request to this line (requested) or already share a cache line with this address (holder)
 CArmISA::SoftwareStep
 CStats::SparseHistDataData structure of sparse histogram
 CStats::SparseHistPrint
 CStats::SparseHistStorTemplatized storage and interface for a sparse histogram stat
 Csc_gem5::special_result
 Cstack_el
 CStackDistCalcThe stack distance calculator is a passive object that merely observes the addresses pass to it
 CDefaultFetch< Impl >::StallsSource of possible stalls
 CDefaultRename< Impl >::StallsSource of possible stalls
 CDefaultDecode< Impl >::StallsSource of possible stalls
 ►CAapcs32::State
 CAapcs64::State
 CTestABI_TcInit::State
 ►CStateBase
 ►CArmSemihosting::AbiBase::StateBase< Arg >
 CGuestABI::StateInitializer< ABI, Enabled >
 CGuestABI::StateInitializer< ABI, typename std::enable_if_t< std::is_constructible< typename ABI::State, const ThreadContext * >::value > >
 ►CStaticInstFlags
 CStats::StatStorTemplatized storage and interface for a simple scalar stat
 CStatTest
 CGcn3ISA::StatusReg
 ►CStats::StorageParams
 CStoreSetImplements a store set predictor for determining if memory instructions are dependent upon each other
 CStoreTrace
 ►CStreamGen
 CStreamTableEntry
 CStringWrap
 CSubBlock
 CEtherSwitch::SwitchTableEntry
 CLoader::Symbol
 CLoader::SymbolTable
 ►CX86Linux::SyscallABI
 ►CSyscallDescThis class provides the wrapper interface for the system call implementations which are defined in the sim/syscall_emul files and bound to the ISAs in the architecture specific code (i.e
 CSyscallDescTable< ABI >
 ►CSyscallDescTable< EmuLinux::SyscallABI32 >
 ►CSyscallDescTable< EmuLinux::SyscallABI64 >
 CSyscallDescTable< PowerISA::SEWorkload::SyscallABI >
 CSyscallDescTable< RiscvISA::RegABI64 >
 CSyscallDescTable< SparcISA::SEWorkload::SyscallABI32 >
 CSyscallDescTable< SparcISA::SEWorkload::SyscallABI64 >
 CSyscallDescTable< SyscallABI >
 CSyscallDescTable< X86ISA::EmuLinux::SyscallABI32 >
 CSyscallDescTable< X86ISA::EmuLinux::SyscallABI64 >
 CSyscallFlagTransTableThis struct is used to build target-OS-dependent tables that map the target's flags to the host's flags
 CSyscallReturnThis class represents the return value from an emulated system call, including any errno setting
 CFaultModel::system_conf
 ►CSystemCounterListenerAbstract class for elements whose events depend on the counting speed of the System Counter
 CBitfieldTypeImpl< Base >::TypeDeducer::T< typename >
 CBitfieldTypeImpl< Base >::TypeDeducer::T< void(C::*)(Type1 &, Type2)>
 ►CTageBranchInfo
 CTAGE::TageBranchInfo
 CTAGEBase::TageEntry
 CTapListener
 ►CQueueEntry::TargetA queue entry is holding packets that will be serviced as soon as resources are available
 CTrace::TarmacContextThis object type is encapsulating the informations needed by a Tarmac record to generate it's own entries
 CUFSHostDevice::taskStartTask start information
 CTBEStorage
 CTBETable< ENTRY >
 ►Ctcp_hdr
 ►Ctcp_opt
 CNet::TcpPtr
 CStats::TempHelper class to construct formula node trees
 CTemperatureThe class stores temperatures in Kelvin and provides helper methods to convert to/from Celsius
 ►Ctemplate DeltaPattern< DeltaSizeBits >
 ►CTest
 CTestABI
 CTestABI_1D
 CTestABI_2D
 CTestABI_Prepare
 CTestABI_TcInit
 CTestClass
 CTestProxy
 CX86Linux64::tgt_fsid
 CRiscvLinux64::tgt_fsid_t
 CRiscvLinux32::tgt_fsid_t
 CLinux::tgt_iovec
 CX86Linux64::tgt_iovec
 CArmFreebsd32::tgt_iovec
 CArmFreebsd64::tgt_iovec
 COperatingSystem::tgt_iovec
 CArmLinux64::tgt_iovec
 CArmLinux32::tgt_iovec
 CArmLinux64::tgt_stat
 CPowerLinux::tgt_stat
 CArmFreebsd64::tgt_stat
 CArmFreebsd32::tgt_stat
 CArmLinux32::tgt_stat
 CRiscvLinux32::tgt_stat
 CLinux::tgt_statStat buffer
 CSolaris::tgt_statStat buffer
 CSparcLinux::tgt_stat
 CLinux::tgt_stat64
 CPowerLinux::tgt_stat64
 CArmFreebsd64::tgt_stat64
 CSparcLinux::tgt_stat64
 CArmLinux64::tgt_stat64
 CX86Linux64::tgt_stat64
 CSparc32Linux::tgt_stat64
 CArmFreebsd32::tgt_stat64
 CArmLinux32::tgt_stat64
 CSolaris::tgt_stat64
 CRiscvLinux64::tgt_stat64
 CRiscvLinux32::tgt_statfs
 CRiscvLinux64::tgt_statfs
 CX86Linux64::tgt_statfs
 CSparc32Linux::tgt_sysinfo
 CSparcLinux::tgt_sysinfo
 CRiscvLinux64::tgt_sysinfo
 CMipsLinux::tgt_sysinfo
 CRiscvLinux32::tgt_sysinfo
 CArmLinux64::tgt_sysinfo
 CArmLinux32::tgt_sysinfo
 CX86Linux64::tgt_sysinfo
 CX86Linux32::tgt_sysinfo
 CSolaris::tgt_timespec
 ►CThermalEntityAn abstract class that represents any thermal entity which is used in the circuital thermal equivalent model
 CSystem::Threads::Thread
 CLinux::thread_info
 CMultiperspectivePerceptron::ThreadDataHistory data is kept for each thread
 CTAGEBase::ThreadHistory
 CSimpleIndirectPredictor::ThreadInfo
 CFreeBSD::ThreadInfo
 CLinux::ThreadInfo
 CSystem::Threads
 CTrace::X86NativeTrace::ThreadState
 CTrace::ArmNativeTrace::ThreadState
 ►CTickEvent
 CTime
 Ctlm_utils::time_ordered_list< PAYLOAD >
 Ctlm_utils::time_ordered_list< std::pair >
 CTimeBuffer< T >
 CTimeBuffer< bool >
 ►CTimeBuffer< Data >
 CTimeBuffer< DecodeStruct >
 ►CTimeBuffer< ElemType >
 CTimeBuffer< FetchStruct >
 CTimeBuffer< IEWStruct >
 CTimeBuffer< IssueStruct >
 ►CTimeBuffer< Minor::BranchData >
 ►CTimeBuffer< Minor::ForwardInstData >
 ►CTimeBuffer< Minor::ForwardLineData >
 CTimeBuffer< RenameStruct >
 CTimeBuffer< TimeStruct >
 CTimeBufStruct< Impl >Struct that defines all backwards communication
 CTimerTable
 CLinux::timespecFor clock_gettime()
 CArmLinux32::timespec
 CArmLinux64::timespec
 CRiscvLinux64::timespec
 CRiscvLinux32::timespec
 CArmFreebsd64::timevalFor gettimeofday()
 CArmLinux32::timevalFor gettimeofday()
 CArmLinux64::timevalFor gettimeofday()
 CLinux::timevalFor gettimeofday()
 CArmFreebsd32::timevalFor gettimeofday()
 COperatingSystem::timevalFor gettimeofday()
 CTimingExprEvalContextObject to gather the visible context for evaluation
 ►CTimingRequestProtocol
 ►CTimingResponseProtocol
 CPowerISA::TlbEntry
 CMipsISA::TlbEntry
 CSparcISA::TlbEntry
 ►CArmISA::TLBIOp
 CSparcISA::TlbMap
 CSparcISA::TlbRange
 CArmISA::TlbTestInterface
 Ctlm::tlm_analysis_triple< T >
 Ctlm::tlm_base_initiator_socket_b< BUSWIDTH, FW_IF, BW_IF >
 ►Ctlm::tlm_base_initiator_socket_b< 32, tlm_fw_transport_if<>, tlm_bw_transport_if<> >
 ►Ctlm::tlm_base_initiator_socket_b< BUSWIDTH, ClockRateControlFwIf, ClockRateControlBwIf >
 ►Ctlm::tlm_base_initiator_socket_b< BUSWIDTH, SignalInterruptFwIf, SignalInterruptBwIf >
 ►Ctlm::tlm_base_initiator_socket_b< BUSWIDTH, tlm_fw_transport_if< my_extended_payload_types >, tlm_bw_transport_if< my_extended_payload_types > >
 ►Ctlm::tlm_base_initiator_socket_b< BUSWIDTH, tlm_fw_transport_if< tlm::tlm_base_protocol_types >, tlm_bw_transport_if< tlm::tlm_base_protocol_types > >
 ►Ctlm::tlm_base_initiator_socket_b< BUSWIDTH, tlm_fw_transport_if< tlm_base_protocol_types >, tlm_bw_transport_if< tlm_base_protocol_types > >
 ►Ctlm::tlm_base_initiator_socket_b< BUSWIDTH, tlm_fw_transport_if< TYPES >, tlm_bw_transport_if< TYPES > >
 Ctlm::tlm_base_protocol_types
 ►Ctlm::tlm_base_socket_if
 Ctlm::tlm_base_target_socket< BUSWIDTH, FW_IF, BW_IF, N, POL >
 ►Ctlm::tlm_base_target_socket< 32, tlm_fw_transport_if< tlm_base_protocol_types >, tlm_bw_transport_if< tlm_base_protocol_types >, 1, sc_core::SC_ONE_OR_MORE_BOUND >
 ►Ctlm::tlm_base_target_socket< 64, ClockRateControlFwIf, ClockRateControlBwIf >
 ►Ctlm::tlm_base_target_socket< 64, SignalInterruptFwIf, SignalInterruptBwIf >
 ►Ctlm::tlm_base_target_socket< BUSWIDTH, tlm_fw_transport_if< my_extended_payload_types >, tlm_bw_transport_if< my_extended_payload_types >, N, POL >
 ►Ctlm::tlm_base_target_socket< BUSWIDTH, tlm_fw_transport_if< tlm::tlm_base_protocol_types >, tlm_bw_transport_if< tlm::tlm_base_protocol_types >, N, POL >
 ►Ctlm::tlm_base_target_socket< BUSWIDTH, tlm_fw_transport_if< tlm_base_protocol_types >, tlm_bw_transport_if< tlm_base_protocol_types >, 1, sc_core::SC_ONE_OR_MORE_BOUND >
 ►Ctlm::tlm_base_target_socket< BUSWIDTH, tlm_fw_transport_if< TYPES >, tlm_bw_transport_if< TYPES >, N, POL >
 Ctlm::tlm_base_target_socket_b< BUSWIDTH, FW_IF, BW_IF >
 Ctlm::tlm_bool< D >
 Ctlm::tlm_dmi
 Ctlm::tlm_endian_context_pool
 ►Ctlm::tlm_extension_base
 ►Ctlm::tlm_generic_payload
 Ctlm::tlm_global_quantum
 ►Ctlm::tlm_mm_interface
 Ctlm::tlm_phase
 Ctlm_utils::tlm_quantumkeeper
 Ctlm::tlm_tag< T >
 Csc_gem5::TlmInitiatorBaseWrapper< BUSWIDTH, FW_IF, BW_IF, N, POL >
 Csc_gem5::TlmInitiatorBaseWrapper< 64 >
 Csc_gem5::TlmInitiatorBaseWrapper< 64, amba_pv::amba_pv_protocol_types >
 Csc_gem5::TlmInitiatorBaseWrapper< BITWIDTH >
 Csc_gem5::TlmTargetBaseWrapper< BUSWIDTH, FW_IF, BW_IF, N, POL >
 Csc_gem5::TlmTargetBaseWrapper< 64 >
 Csc_gem5::TlmTargetBaseWrapper< 64, amba_pv::amba_pv_protocol_types >
 Csc_gem5::TlmTargetBaseWrapper< BITWIDTH >
 CPowerLinux::tmsFor times()
 CArmLinux64::tmsFor times()
 CArmLinux32::tmsFor times()
 CArmFreebsd32::tmsFor times()
 CArmFreebsd64::tmsFor times()
 CLinux::tmsFor times()
 CTokenManager
 CTopology
 CTraceCPU::FixedRetryGen::TraceElementThis struct stores a line in the trace file
 CTraceGen::TraceElementThis struct stores a line in the trace file
 ►CTrace::TarmacTracerRecordV8::TraceEntryV8General data shared by all v8 entries
 CElasticTrace::TraceInfo
 ►CTraceMemEntry
 CTraceRecordClass for recording cache contents
 ►Csc_gem5::TraceValBase
 Csc_gem5::TraceValFxnumBase< T, Base >
 ►Csc_gem5::TraceValFxnumBase<::sc_dt::sc_fxnum, Base >
 ►Csc_gem5::TraceValFxnumBase<::sc_dt::sc_fxnum_fast, Base >
 CMemChecker::TransactionCaptures the lifetimes of read and write operations, and the values they consumed or produced respectively
 CUFSHostDevice::transferDoneInfoTransfer completion info
 CUFSHostDevice::transferInfoDifferent events, and scenarios require different types of information
 CUFSHostDevice::transferStartTransfer start information
 CTrafficGen::TransitionStruct to represent a probabilistic transition during parsing
 ►CBaseTLB::Translation
 CX86ISA::GpuTLB::Translation
 CSMMUTranslationProcess::TranslContext
 CSMMUTranslationProcess::TranslResult
 CAbstractController::TransMapPair
 CTrie< Key, Value >A trie is a tree-based data structure used for data retrieval
 CTrie< Addr, TlbEntry >
 CTrie< Addr, uint32_t >
 CTrie< Addr, X86ISA::TlbEntry >
 CTriggerQueue< T >
 ►Ctrue_type
 CSparcISA::TteTag
 CiGbReg::TxDesc
 CBitfieldTypeImpl< Base >::TypeDeducer
 ►Cudp_hdr
 CNet::UdpPtr
 CUFSHostDevice::UFSHCDSGEntryStruct UFSHCDSGEntry - UFSHCI PRD Entry baseAddr: Lower 32bit physical address DW-0 upperAddr: Upper 32bit physical address DW-1 reserved: Reserved for future use DW-2 size: size of physical segment DW-3
 CPort::UnboundPortException
 CUncoalescedTable
 ►CUncompressedPattern
 CUncontendedMutex
 CUnifiedFreeListFreeList class that simply holds the list of free integer and floating point registers
 CUnifiedRenameMapUnified register rename map for all classes of registers
 Csc_gem5::UniqueNameGen
 ►CRubyPrefetcher::UnitFilterEntry
 ►Cunordered_map
 CBitfieldBackend::Unsigned< Storage, first, last >
 CUFSHostDevice::UPIUMessageUPIU tranfer message
 CUFSHostDevice::UTPTransferCMDDescStruct UTPTransferCMDDesc - UFS Commad Descriptor structure commandUPIU: Command UPIU Frame address responseUPIU: Response UPIU Frame address PRDTable: Physcial Region Descriptor All lengths as defined by JEDEC220
 CUFSHostDevice::UTPTransferReqDescStruct UTPTransferReqDesc - UTRD structure header: UTRD header DW-0 to DW-3 commandDescBaseAddrLo: UCD base address low DW-4 commandDescBaseAddrHi: UCD base address high DW-5 responseUPIULength: response UPIU length DW-6 responseUPIUOffset: response UPIU offset DW-6 PRDTableLength: Physical region descriptor length DW-7 PRDTableOffset: Physical region descriptor offset DW-7
 CUFSHostDevice::UTPUPIUHeaderAll the data structures are defined in the UFS standard This standard be found at the JEDEC website free of charge (login required): http://www.jedec.org/standards-documents/results/jesd220
 CUFSHostDevice::UTPUPIURSPStruct UTPUPIURSP - Response UPIU structure header: UPIU header DW-0 to DW-2 residualTransferCount: Residual transfer count DW-3 reserved: Reserved DW-4 to DW-7 senseDataLen: Sense data length DW-8 U16 senseData: Sense data field DW-8 to DW-12
 CUFSHostDevice::UTPUPIUTaskReqStruct UTPUPIUTaskReq - Task request UPIU structure header - UPIU header structure DW0 to DW-2 inputParam1: Input param 1 DW-3 inputParam2: Input param 2 DW-4 inputParam3: Input param 3 DW-5 reserved: Reserver DW-6 to DW-7
 CSolaris::utsnameInterface struct for uname()
 COperatingSystem::utsnameInterface struct for uname()
 CLinux::utsnameInterface struct for uname()
 CTriggerQueue< T >::ValType
 CGuestABI::value &&(sizeof(Integer) > 8)> >< Integer >
 CValueSamplesA pair of value and its number of samples, used for sampling
 CGuestABI::VarArgs< Types >
 CGuestABI::VarArgsBase< Types >
 ►CGuestABI::VarArgsBase< Types... >
 CGuestABI::VarArgsBase<>
 CGuestABI::VarArgsImpl< ABI, Base, Types >
 ►CGuestABI::VarArgsImpl< ABI, Base, Types... >
 Csc_gem5::VcdTraceScope
 CVecLaneT< VecElem, Const >Vector Lane abstraction Another view of a container
 CVecPredRegContainer< NumBits, Packed >Generic predicate register container
 CVecPredRegContainer< TheISA::VecPredRegSizeBits, TheISA::VecPredRegHasPackedRepr >
 CVecPredRegT< VecElem, NumElems, Packed, Const >Predicate register view
 CVecRegContainer< SIZE >Vector Register Abstraction This generic class is the model in a particularization of MVC, to vector registers
 CVecRegContainer< TheISA::VecRegSizeBytes >
 CVecRegT< VecElem, NumElems, Const >Vector Register Abstraction This generic class is a view in a particularization of MVC, to vector registers
 ►Cstd::vector< T >STL vector class
 Cstd::vector< AbstractController * >
 Cstd::vector< AbstractMemory * >
 Cstd::vector< Access >
 Cstd::vector< AccessMapState >
 Cstd::vector< Action * >
 Cstd::vector< Addr >
 Cstd::vector< AddressMonitor >
 Cstd::vector< AddrRange >
 Cstd::vector< ArmISA::BrkPoint >
 Cstd::vector< ArmISA::PMU::CounterState >
 Cstd::vector< ArmISA::VecPredRegContainer >
 Cstd::vector< ArmISA::VecRegContainer >
 Cstd::vector< ArmISA::WatchPoint >
 Cstd::vector< ArmV8KvmCPU::IntRegInfo >
 Cstd::vector< ArmV8KvmCPU::MiscRegInfo >
 Cstd::vector< AtomicStruct * >
 Cstd::vector< BackingStoreEntry >
 Cstd::vector< Bank >
 Cstd::vector< BankedArray::AccessRecord >
 Cstd::vector< BankType >
 Cstd::vector< BaseCPU * >
 Cstd::vector< BaseGlobalEvent::BarrierEvent * >
 Cstd::vector< BaseInterrupts * >
 Cstd::vector< BasePixelPump::PixelEvent * >
 Cstd::vector< BASER >
 Cstd::vector< BasicExtLink * >
 Cstd::vector< BasicIntLink * >
 Cstd::vector< BloomFilter::Base * >
 Cstd::vector< bool >
 Cstd::vector< BpId >
 Cstd::vector< bw_interface_type * >
 Cstd::vector< CacheBlk >
 Cstd::vector< char * >
 Cstd::vector< char >
 Cstd::vector< Check * >
 Cstd::vector< Chunk >
 Cstd::vector< CircularQueue::iterator >
 Cstd::vector< class HSAPacketProcessor::RQLEntry * >
 Cstd::vector< Clocked * >
 Cstd::vector< ClockRateControlFwIf * >
 Cstd::vector< CoherentXBar::SnoopRespPort * >
 Cstd::vector< CompactorEntry >
 Cstd::vector< CompressionBlk >
 Cstd::vector< Compressor::Base * >
 Cstd::vector< Compressor::FrequentValues::CompData::CompressedValue >
 Cstd::vector< Compressor::FrequentValues::FrequentValuesListener * >
 Cstd::vector< Compressor::FrequentValues::VFTEntry >
 Cstd::vector< ComputeUnit * >
 Cstd::vector< ComputeUnit::DataPort >
 Cstd::vector< ComputeUnit::DTLBPort >
 Cstd::vector< const char * >
 Cstd::vector< const sc_core::sc_event * >
 Cstd::vector< ContextID >
 Cstd::vector< CopyEngine::CopyEngineChannel * >
 Cstd::vector< Counter >
 Cstd::vector< CpuThread * >
 Cstd::vector< CreditLink * >
 Cstd::vector< Cycles >
 Cstd::vector< Debug::Flag * >
 Cstd::vector< DefaultBTB::BTBEntry >
 Cstd::vector< DependencyEntry >
 Cstd::vector< DerivedClockDomain * >
 Cstd::vector< DictionaryEntry >
 Cstd::vector< DISPATCH_STATUS >
 Cstd::vector< DmaDoneEvent * >
 Cstd::vector< DmaDoneEvent >
 Cstd::vector< DmaThread * >
 Cstd::vector< DomainID >
 Cstd::vector< double >
 Cstd::vector< Drainable * >
 Cstd::vector< DRAMInterface::Command >
 Cstd::vector< DRAMInterface::Rank * >
 Cstd::vector< DynamicSensitivity * >
 Cstd::vector< ElasticTrace::TraceInfo * >
 Cstd::vector< EmulatedDriver * >
 Cstd::vector< Entry >
 Cstd::vector< Episode * >
 Cstd::vector< EtherSwitch::Interface * >
 Cstd::vector< FALRUBlk * >
 Cstd::vector< FastModel::CortexA76 * >
 Cstd::vector< FastModel::CortexR52 * >
 Cstd::vector< Fault >
 Cstd::vector< FaultModel::system_conf >
 Cstd::vector< FetchUnit >
 Cstd::vector< FetchUnit::FetchBufDesc >
 Cstd::vector< Fiber * >
 Cstd::vector< flit * >
 Cstd::vector< flitBuffer >
 Cstd::vector< FuncUnit * >
 Cstd::vector< GenericSatCounter< uint8_t > >
 Cstd::vector< GenericTimerFrame * >
 Cstd::vector< GicV2::BankedRegs * >
 Cstd::vector< Gicv2mFrame * >
 Cstd::vector< Gicv3::IntTriggerType >
 Cstd::vector< Gicv3CPUInterface * >
 Cstd::vector< Gicv3Redistributor * >
 Cstd::vector< GPUDynInstPtr >
 Cstd::vector< GpuWavefront * >
 Cstd::vector< hsa_kernel_dispatch_packet_s >
 Cstd::vector< hsa_signal_value_t >
 Cstd::vector< IF * >
 Cstd::vector< Index >
 Cstd::vector< IndexNodeMap >
 Cstd::vector< InstPtr >
 Cstd::vector< InstSeqNum >
 Cstd::vector< int * >
 Cstd::vector< int >
 Cstd::vector< int32_t >
 Cstd::vector< int64_t >
 Cstd::vector< int8_t >
 Cstd::vector< IntRegIndex >
 Cstd::vector< IntSinkPin< X86ISA::I82094AA > * >
 Cstd::vector< IntSinkPin< X86ISA::I8259 > * >
 Cstd::vector< IntSourcePin< X86ISA::Cmos::X86RTC > * >
 Cstd::vector< IntSourcePin< X86ISA::I8042 > * >
 Cstd::vector< IntSourcePin< X86ISA::I8254 > * >
 Cstd::vector< IntSourcePin< X86ISA::I8259 > * >
 Cstd::vector< iris::MemorySpaceId >
 Cstd::vector< iris::MemorySpaceInfo >
 Cstd::vector< iris::MemorySupportedAddressTranslationResult >
 Cstd::vector< iris::ResourceId >
 Cstd::vector< IROUTER >
 Cstd::vector< KvmVM::MemorySlot >
 Cstd::vector< LastWriter * >
 Cstd::vector< LinearEquation >
 Cstd::vector< LinkOrder >
 Cstd::vector< Loader::MemoryImage::Segment >
 Cstd::vector< Loader::ObjectFile * >
 Cstd::vector< Location >
 Cstd::vector< LocProperty >
 Cstd::vector< LQEntry >
 Cstd::vector< LSQUnit >
 Cstd::vector< LSQUnit::SQEntry >
 Cstd::vector< MachInst >
 Cstd::vector< MemDepEntryPtr >
 Cstd::vector< MemPtr >
 Cstd::vector< MessageBuffer * >
 Cstd::vector< Minor::Decode::DecodeThreadInfo >
 Cstd::vector< Minor::Execute::ExecuteThreadInfo >
 Cstd::vector< Minor::Fetch1::Fetch1ThreadInfo >
 Cstd::vector< Minor::Fetch2::Fetch2ThreadInfo >
 Cstd::vector< Minor::FUPipeline * >
 Cstd::vector< Minor::InputBuffer< Minor::ForwardInstData > >
 Cstd::vector< Minor::InputBuffer< Minor::ForwardLineData > >
 Cstd::vector< Minor::Scoreboard >
 Cstd::vector< MinorFU * >
 Cstd::vector< MinorFUTiming * >
 Cstd::vector< MinorOpClass * >
 Cstd::vector< MsgPtr >
 Cstd::vector< MSHR >
 Cstd::vector< MSIXPbaEntry >
 Cstd::vector< MSIXTable >
 Cstd::vector< MultiperspectivePerceptron::FilterEntry >
 Cstd::vector< MultiperspectivePerceptron::HistorySpec * >
 Cstd::vector< MultiperspectivePerceptron::ThreadData * >
 Cstd::vector< MultiSocketSimpleSwitchAT::ConnectionInfo * >
 Cstd::vector< NetDest >
 Cstd::vector< NetworkInterface * >
 Cstd::vector< NetworkInterface::InputPort * >
 Cstd::vector< NetworkInterface::OutputPort * >
 Cstd::vector< NetworkLink * >
 Cstd::vector< NVMInterface::Rank * >
 Cstd::vector< O3ThreadState * >
 Cstd::vector< OpDesc * >
 Cstd::vector< OutVcState >
 Cstd::vector< Packet * >
 Cstd::vector< Packet >
 Cstd::vector< PCEvent * >
 Cstd::vector< PhysRegId >
 Cstd::vector< PhysRegIdPtr >
 Cstd::vector< Pixel >
 Cstd::vector< PollEvent * >
 Cstd::vector< PoolManager * >
 Cstd::vector< PortID >
 Cstd::vector< PowerModel * >
 Cstd::vector< PowerModelState * >
 Cstd::vector< PowerState * >
 Cstd::vector< PrefetchEntry >
 Cstd::vector< Prefetcher::AccessMapPatternMatching::AccessMapEntry >
 Cstd::vector< Prefetcher::Base::PrefetchListener * >
 Cstd::vector< Prefetcher::DeltaCorrelatingPredictionTables::DCPTEntry >
 Cstd::vector< Prefetcher::IndirectMemory::IndirectPatternDetectorEntry >
 Cstd::vector< Prefetcher::IndirectMemory::PrefetchTableEntry >
 Cstd::vector< Prefetcher::IrregularStreamBuffer::AddressMapping >
 Cstd::vector< Prefetcher::IrregularStreamBuffer::AddressMappingEntry >
 Cstd::vector< Prefetcher::IrregularStreamBuffer::TrainingUnitEntry >
 Cstd::vector< Prefetcher::PIF::IndexEntry >
 Cstd::vector< Prefetcher::PIF::PrefetchListenerPC * >
 Cstd::vector< Prefetcher::SBOOE::Sandbox >
 Cstd::vector< Prefetcher::SBOOE::SandboxEntry >
 Cstd::vector< Prefetcher::SignaturePath::PatternEntry >
 Cstd::vector< Prefetcher::SignaturePath::PatternStrideEntry >
 Cstd::vector< Prefetcher::SignaturePath::SignatureEntry >
 Cstd::vector< Prefetcher::SignaturePathV2::GlobalHistoryEntry >
 Cstd::vector< Prefetcher::STeMS::ActiveGenerationTableEntry >
 Cstd::vector< Prefetcher::STeMS::ActiveGenerationTableEntry::SequenceEntry >
 Cstd::vector< Prefetcher::STeMS::RegionMissOrderBufferEntry >
 Cstd::vector< ProbeListener * >
 Cstd::vector< ProbeListenerArgBase< Arg > * >
 Cstd::vector< ProbeListenerArgBase< BaseCache::DataUpdate > * >
 Cstd::vector< ProbeListenerArgBase< bool > * >
 Cstd::vector< ProbeListenerArgBase< DynInstPtr > * >
 Cstd::vector< ProbeListenerArgBase< Packet > * >
 Cstd::vector< ProbeListenerArgBase< RequestPtr > * >
 Cstd::vector< ProbeListenerArgBase< std::pair > * >
 Cstd::vector< ProbeListenerArgBase< std::pair< DynInstPtr, Packet > > * >
 Cstd::vector< ProbeListenerArgBase< std::pair< SimpleThread *, const RefCountingPtr > > * >
 Cstd::vector< ProbeListenerArgBase< Temperature > * >
 Cstd::vector< ProbePoint * >
 Cstd::vector< Process * >
 Cstd::vector< ProtocolTester::GMTokenPort * >
 Cstd::vector< PwrStatus >
 Cstd::vector< QueuedResponsePort * >
 Cstd::vector< RedirectPath * >
 Cstd::vector< RefCountingPtr >
 Cstd::vector< RegId >
 Cstd::vector< Register32 >
 Cstd::vector< Register64 >
 Cstd::vector< RegisterBankTest::Access >
 Cstd::vector< RegisterRaz >
 Cstd::vector< RegPtr >
 Cstd::vector< RegVal >
 Cstd::vector< ReqLayer * >
 Cstd::vector< RequestorInfo >
 Cstd::vector< RequestPort * >
 Cstd::vector< RequestPtr >
 Cstd::vector< RespLayer * >
 Cstd::vector< ResponsePort * >
 Cstd::vector< Result >
 Cstd::vector< ReturnAddrStack >
 Cstd::vector< RiscvISA::TlbEntry >
 Cstd::vector< Router * >
 Cstd::vector< RubyPort::MemResponsePort * >
 Cstd::vector< RubyPort::PioRequestPort * >
 Cstd::vector< RubyPrefetcher::NonUnitFilterEntry >
 Cstd::vector< RubyPrefetcher::UnitFilterEntry >
 Cstd::vector< sc_core::sc_attr_base * >
 Cstd::vector< sc_core::sc_event * >
 Cstd::vector< sc_core::sc_event_finder * >
 Cstd::vector< sc_core::sc_export_base * >
 Cstd::vector< sc_core::sc_fifo_in_if< T > * >
 Cstd::vector< sc_core::sc_fifo_out_if< T > * >
 Cstd::vector< sc_core::sc_interface * >
 Cstd::vector< sc_core::sc_join * >
 Cstd::vector< sc_core::sc_object * >
 Cstd::vector< sc_core::sc_port_base * >
 Cstd::vector< sc_core::sc_signal_in_if< bool > * >
 Cstd::vector< sc_core::sc_signal_in_if< sc_dt::sc_logic > * >
 Cstd::vector< sc_core::sc_signal_in_if< sc_dt::sc_lv< W > > * >
 Cstd::vector< sc_core::sc_signal_in_if< T > * >
 Cstd::vector< sc_core::sc_signal_inout_if< bool > * >
 Cstd::vector< sc_core::sc_signal_inout_if< sc_dt::sc_logic > * >
 Cstd::vector< sc_core::sc_signal_inout_if< sc_dt::sc_lv< W > > * >
 Cstd::vector< sc_core::sc_signal_inout_if< T > * >
 Cstd::vector< sc_core::sc_spawn_options::Reset< const sc_core::sc_in< bool > > >
 Cstd::vector< sc_core::sc_spawn_options::Reset< const sc_core::sc_inout< bool > > >
 Cstd::vector< sc_core::sc_spawn_options::Reset< const sc_core::sc_out< bool > > >
 Cstd::vector< sc_core::sc_spawn_options::Reset< const sc_core::sc_signal_in_if< bool > > >
 Cstd::vector< sc_dt::uint64 >
 Cstd::vector< sc_fifo_in_if< T > * >
 Cstd::vector< sc_fifo_out_if< T > * >
 Cstd::vector< sc_gem5::Port::Binding * >
 Cstd::vector< sc_gem5::Port::Sensitivity * >
 Cstd::vector< sc_gem5::Reset * >
 Cstd::vector< sc_gem5::VcdTraceValBase * >
 Cstd::vector< sc_signal_in_if< bool > * >
 Cstd::vector< sc_signal_in_if< sc_dt::sc_bigint< W > > * >
 Cstd::vector< sc_signal_in_if< sc_dt::sc_biguint< W > > * >
 Cstd::vector< sc_signal_in_if< sc_dt::sc_int< W > > * >
 Cstd::vector< sc_signal_in_if< sc_dt::sc_logic > * >
 Cstd::vector< sc_signal_in_if< sc_dt::sc_uint< W > > * >
 Cstd::vector< sc_signal_inout_if< bool > * >
 Cstd::vector< sc_signal_inout_if< sc_dt::sc_bigint< W > > * >
 Cstd::vector< sc_signal_inout_if< sc_dt::sc_biguint< W > > * >
 Cstd::vector< sc_signal_inout_if< sc_dt::sc_int< W > > * >
 Cstd::vector< sc_signal_inout_if< sc_dt::sc_logic > * >
 Cstd::vector< sc_signal_inout_if< sc_dt::sc_lv< W > > * >
 Cstd::vector< sc_signal_inout_if< sc_dt::sc_uint< W > > * >
 Cstd::vector< sc_signal_inout_if< T > * >
 Cstd::vector< sc_trace_params * >
 Cstd::vector< ScalarRegisterFile * >
 Cstd::vector< ScalarRegU32 >
 Cstd::vector< Scheduler >
 Cstd::vector< SCMI::Communication * >
 Cstd::vector< SectorBlk >
 Cstd::vector< SectorSubBlk * >
 Cstd::vector< SectorSubBlk >
 Cstd::vector< Sequencer * >
 Cstd::vector< Set >
 Cstd::vector< short >
 Cstd::vector< SignalInterruptFwIf * >
 Cstd::vector< SimpleCache::CPUSidePort >
 Cstd::vector< SimpleExecContext * >
 Cstd::vector< SimpleIndirectPredictor::ThreadInfo >
 Cstd::vector< SimpleThread * >
 Cstd::vector< size_type >
 Cstd::vector< SMMUv3DeviceInterface * >
 Cstd::vector< SnoopRespLayer * >
 Cstd::vector< SrcClockDomain * >
 Cstd::vector< SSID >
 Cstd::vector< StaticSensitivity * >
 Cstd::vector< Stats::Counter >
 Cstd::vector< Stats::DistData >
 Cstd::vector< Stats::Formula * >
 Cstd::vector< Stats::Group * >
 Cstd::vector< Stats::Histogram * >
 Cstd::vector< Stats::Info * >
 Cstd::vector< Stats::Scalar * >
 Cstd::vector< std::deque >
 Cstd::vector< std::deque< std::pair< GPUDynInstPtr, SCH_STATUS > > >
 Cstd::vector< std::deque< struct FlashDevice::CallBackEntry > >
 Cstd::vector< std::deque< tlm::tlm_generic_payload * > >
 Cstd::vector< std::list >
 Cstd::vector< std::map< uint32_t, AbstractController * > >
 Cstd::vector< std::pair >
 Cstd::vector< std::pair< int, AtomicOpFunctor * > >
 Cstd::vector< std::pair< std::string, sc_gem5::VcdTraceValBase * > >
 Cstd::vector< std::pair< TCPIface::NodeInfo, int > >
 Cstd::vector< std::pair< Wavefront *, bool > >
 Cstd::vector< std::queue< int > >
 Cstd::vector< std::shared_ptr< InputUnit > >
 Cstd::vector< std::shared_ptr< OutputUnit > >
 Cstd::vector< std::string >
 Cstd::vector< std::unique_ptr< ArmISA::PMU::RegularEvent::RegularProbe > >
 Cstd::vector< std::unique_ptr< ArmSemihosting::FileBase > >
 Cstd::vector< std::unique_ptr< BaseCache::CacheCmdStats > >
 Cstd::vector< std::unique_ptr< BaseMemProbe::PacketListener > >
 Cstd::vector< std::unique_ptr< Compressor::DictionaryCompressor::Pattern > >
 Cstd::vector< std::unique_ptr< CpuLocalTimer::Timer > >
 Cstd::vector< std::unique_ptr< FastModel::ScxEvsCortexR52::CorePins > >
 Cstd::vector< std::unique_ptr< FastModel::SignalReceiver > >
 Cstd::vector< std::unique_ptr< GenericTimer::CoreTimers > >
 Cstd::vector< std::unique_ptr< IntSinkPin > >
 Cstd::vector< std::unique_ptr< IntSourcePin > >
 Cstd::vector< std::unique_ptr< Loader::ObjectFile > >
 Cstd::vector< std::unique_ptr< Network > >
 Cstd::vector< std::unique_ptr< sc_gem5::TlmInitiatorBaseWrapper > >
 Cstd::vector< std::unique_ptr< sc_gem5::TlmTargetBaseWrapper > >
 Cstd::vector< std::vector< AbstractCacheEntry * > >
 Cstd::vector< std::vector< Addr > >
 Cstd::vector< std::vector< bool > >
 Cstd::vector< std::vector< double > >
 Cstd::vector< std::vector< int > >
 Cstd::vector< std::vector< MessageBuffer * > >
 Cstd::vector< std::vector< NetDest > >
 Cstd::vector< std::vector< Register32 > >
 Cstd::vector< std::vector< RegVal > >
 Cstd::vector< std::vector< ReplaceableEntry * > >
 Cstd::vector< std::vector< ReplData > >
 Cstd::vector< std::vector< short int > >
 Cstd::vector< std::vector< SimpleIndirectPredictor::IPredEntry > >
 Cstd::vector< std::vector< Stats::Histogram * > >
 Cstd::vector< std::vector< std::array< bool, 2 > > >
 Cstd::vector< std::vector< std::string > >
 Cstd::vector< std::vector< std::vector< Addr > > >
 Cstd::vector< std::vector< std::vector< bool > > >
 Cstd::vector< std::vector< std::vector< Stats::Histogram * > > >
 Cstd::vector< std::vector< uint32_t > >
 Cstd::vector< std::vector< unsigned int > >
 Cstd::vector< std::vector< unsigned short int > >
 Cstd::vector< std::vector< Wavefront * > >
 Cstd::vector< struct ArmISA::ISA::MiscRegLUTEntry >
 Cstd::vector< struct FlashDevice::PageMapEntry >
 Cstd::vector< struct vring_used_elem >
 Cstd::vector< SuperBlk >
 Cstd::vector< Switch * >
 Cstd::vector< Symbol >
 Cstd::vector< System * >
 Cstd::vector< System::Threads::Thread >
 Cstd::vector< SystemCounterListener * >
 Cstd::vector< T * >
 Cstd::vector< TAGEBase::ThreadHistory >
 Cstd::vector< TheISA::ISA * >
 Cstd::vector< TheISA::PCState >
 Cstd::vector< TheISA::VecPredRegContainer >
 Cstd::vector< TheISA::VecRegContainer >
 Cstd::vector< ThermalCapacitor * >
 Cstd::vector< ThermalDomain * >
 Cstd::vector< ThermalEntity * >
 Cstd::vector< ThermalNode * >
 Cstd::vector< ThermalReference * >
 Cstd::vector< ThermalResistor * >
 Cstd::vector< ThreadContext * >
 Cstd::vector< ThreadID >
 Cstd::vector< Tick >
 Cstd::vector< TimingExpr * >
 Cstd::vector< TLBCoalescer::CpuSidePort * >
 Cstd::vector< TLBCoalescer::MemSidePort * >
 Cstd::vector< tlm::tlm_bw_transport_if< tlm::tlm_base_protocol_types > * >
 ►Cstd::vector< tlm::tlm_extension_base * >
 Cstd::vector< tlm::tlm_fw_transport_if< tlm::tlm_base_protocol_types > * >
 Cstd::vector< tlm::tlm_generic_payload * >
 Cstd::vector< tlm::tlm_master_if< REQ, RSP > * >
 Cstd::vector< tlm::tlm_slave_if< REQ, RSP > * >
 Cstd::vector< tlm::tlm_transport_if< REQ, RSP > * >
 Cstd::vector< tlm_fw_transport_if< my_extended_payload_types > * >
 Cstd::vector< tlm_fw_transport_if< tlm::tlm_base_protocol_types > * >
 Cstd::vector< tlm_fw_transport_if< tlm_base_protocol_types > * >
 Cstd::vector< tlm_fw_transport_if< TYPES > * >
 Cstd::vector< tlm_fw_transport_if<> * >
 Cstd::vector< tlm_nonblocking_get_if< T > * >
 Cstd::vector< tlm_nonblocking_peek_if< T > * >
 Cstd::vector< tlm_nonblocking_put_if< T > * >
 Cstd::vector< tlm_utils::callback_binder_bw< tlm::tlm_base_protocol_types > * >
 Cstd::vector< tlm_utils::callback_binder_fw< tlm::tlm_base_protocol_types > * >
 Cstd::vector< tlm_utils::instance_specific_extensions_per_accessor * >
 ►Cstd::vector< tlm_utils::ispex_base * >
 Cstd::vector< tlm_utils::simple_target_socket_b::fw_process::process_handle_class * >
 Cstd::vector< tlm_utils::simple_target_socket_tagged_b::fw_process::process_handle_class * >
 Cstd::vector< TokenManager * >
 Cstd::vector< TraceCPU::ElasticDataGen::GraphNode * >
 Cstd::vector< TraceRecord * >
 Cstd::vector< UFSHostDevice::UFSSCSIDevice * >
 Cstd::vector< uint32_t >
 Cstd::vector< uint64_t >
 Cstd::vector< uint8_t >
 Cstd::vector< unsigned >
 Cstd::vector< unsigned int >
 Cstd::vector< unsigned int short >
 Cstd::vector< unsigned short int >
 Cstd::vector< value_type >
 Cstd::vector< VecRegContainer >
 Cstd::vector< vector< Entry > >
 Cstd::vector< VectorRegisterFile * >
 Cstd::vector< VirtDescriptor >
 Cstd::vector< VirtDescriptor::Index >
 Cstd::vector< VirtQueue * >
 Cstd::vector< VirtualChannel >
 Cstd::vector< VirtualReg >
 Cstd::vector< VNET_type >
 Cstd::vector< void * >
 Cstd::vector< WaitClass >
 Cstd::vector< Wavefront * >
 Cstd::vector< WFBarrier >
 Cstd::vector< WriteQueueEntry >
 Cstd::vector< X86ISA::ACPI::SysDescTable * >
 Cstd::vector< X86ISA::E820Entry * >
 Cstd::vector< X86ISA::GpuTLB::CpuSidePort * >
 Cstd::vector< X86ISA::GpuTLB::MemSidePort * >
 Cstd::vector< X86ISA::IntelMP::BaseConfigEntry * >
 Cstd::vector< X86ISA::IntelMP::ExtConfigEntry * >
 Cstd::vector< X86ISA::SMBios::SMBiosStructure * >
 Cstd::vector< X86ISA::TlbEntry >
 CArmISA::VectorCatch
 CStats::VectorPrint
 CStats::VectorProxy< Stat >
 CVirtDescriptorVirtIO descriptor (chain) wrapper
 CVirtQueue::VirtRing< T >VirtIO ring buffer wrapper
 CVirtQueue::VirtRing< struct vring_used_elem >
 CVirtQueue::VirtRing< VirtDescriptor::Index >
 CVirtualChannel
 CSinic::Device::VirtualReg
 CVMA
 ►CVncKeyboardA device that expects to receive input from the vnc server should derrive (through mulitple inheritence if necessary from VncKeyboard or VncMouse and call setKeyboard() or setMouse() respectively on the vnc server
 ►CVncMouse
 CArmISA::VReg128-bit NEON vector register
 Cvring
 Cvring_avail
 Cvring_desc
 Cvring_used
 Cvring_used_elem
 CX86ISA::I386Process::VSyscallPage
 CX86ISA::X86_64Process::VSyscallPage
 CWaitClass
 CWaiterStateWaiterState defines internal state of a waiter thread
 CX86ISA::Walker::WalkerState
 CRiscvISA::Walker::WalkerState
 CArmISA::TableWalker::WalkerState
 CArmISA::WatchPoint
 CWFBarrierWF barrier slots
 CWholeTranslationStateThis class captures the state of an address translation
 CTimeBuffer< T >::wire
 Csc_dt::word_list
 Csc_dt::word_short
 Csc_gem5::WriteChecker< WRITER_POLICY >
 Csc_gem5::WriteChecker< sc_core::SC_MANY_WRITERS >
 Csc_gem5::WriteChecker< sc_core::SC_ONE_WRITER >
 CMemChecker::WriteClusterCaptures sets of writes where all writes are overlapping with at least one other write
 CWriteMask
 CUFSHostDevice::writeToDiskBurstDisk transfer burst information
 ►CX
 CX86PseudoInstABI
Generated on Tue Mar 23 2021 19:42:09 for gem5 by doxygen 1.8.17