Here is a list of all class members with links to the classes they belong to:

- r -

• r : ArmISA::RemoteGDB::AArch32GdbRegCache , ArmISA::RemoteGDB::AArch64GdbRegCache , ContextDescriptor , MathExpr::Node , MipsISA::RemoteGDB::MipsGdbRegCache , PowerISA::RemoteGDB::PowerGdbRegCache , RiscvISA::RemoteGDB::RiscvGdbRegCache , sc_gem5::ProcessObjRetFuncWrapper< T, R > , SparcISA::RemoteGDB::SPARC64GdbRegCache , SparcISA::RemoteGDB::SPARCGdbRegCache , Stats::BinaryNode< Op > , X86ISA::RemoteGDB::AMD64GdbRegCache , X86ISA::RemoteGDB::X86GdbRegCache
• r10 : Trace::X86NativeTrace::ThreadState , X86ISA::RemoteGDB::AMD64GdbRegCache::M5_ATTR_PACKED
• r11 : Trace::X86NativeTrace::ThreadState , X86ISA::RemoteGDB::AMD64GdbRegCache::M5_ATTR_PACKED
• r12 : Trace::X86NativeTrace::ThreadState , X86ISA::RemoteGDB::AMD64GdbRegCache::M5_ATTR_PACKED
• R128 : Gcn3ISA::InFmt_MIMG
• r13 : Trace::X86NativeTrace::ThreadState , X86ISA::RemoteGDB::AMD64GdbRegCache::M5_ATTR_PACKED
• r14 : Trace::X86NativeTrace::ThreadState , X86ISA::RemoteGDB::AMD64GdbRegCache::M5_ATTR_PACKED
• r15 : Trace::X86NativeTrace::ThreadState , X86ISA::RemoteGDB::AMD64GdbRegCache::M5_ATTR_PACKED
• r8 : Trace::X86NativeTrace::ThreadState , X86ISA::RemoteGDB::AMD64GdbRegCache::M5_ATTR_PACKED
• r9 : Trace::X86NativeTrace::ThreadState , X86ISA::RemoteGDB::AMD64GdbRegCache::M5_ATTR_PACKED
• radv : iGbReg::Regs
• radvEvent : IGbE
• radvProcess() : IGbE
• raise() : ArmInterruptPin , ArmPPI , ArmSPI , IntSinkPinBase , IntSourcePinBase
• raiseInterrupt() : Ap2ScpDoorbell , ArmISA::PMU , MhuDoorbell , SCMI::Platform , Scp2ApDoorbell , Scp
• raiseInterruptPin() : Clint , FastModel::ScxEvsCortexR52< Types >::CorePins , FastModel::ScxEvsCortexR52< Types > , X86ISA::I82094AA , X86ISA::I8259
• raiseInterrupts() : Pl011
• raiseOnDevice() : IntSinkPin< Device > , IntSinkPinBase
• rand() : QTIsaac< ALPHA >
• randa : QTIsaac< ALPHA >::randctx
• randAddressMap : AddressManager
• randb : QTIsaac< ALPHA >::randctx
• randc : QTIsaac< ALPHA >::randctx
• randcnt : QTIsaac< ALPHA >::randctx
• randctx() : QTIsaac< ALPHA >::randctx
• randinit() : QTIsaac< ALPHA >
• randmem : QTIsaac< ALPHA >::randctx
• random : Linux
• Random() : Random
• random() : Random
• Random() : ReplacementPolicy::Random
• random : SMMUv3BaseCache
• RandomGen() : RandomGen
• randomPick() : RandomStreamGen
• randomPriority() : MinorCPU
• RandomReplData() : ReplacementPolicy::Random::RandomReplData
• RandomStreamGen() : RandomStreamGen
• randrsl : QTIsaac< ALPHA >::randctx
• range : AbstractMemory , BackingStoreEntry , LdsState , MemBackdoor , PciBar , sc_core::sc_in< sc_dt::sc_bigint< W > > , sc_core::sc_in< sc_dt::sc_biguint< W > > , sc_core::sc_in< sc_dt::sc_int< W > > , sc_core::sc_in< sc_dt::sc_uint< W > > , sc_core::sc_inout< sc_dt::sc_bigint< W > > , sc_core::sc_inout< sc_dt::sc_biguint< W > > , sc_core::sc_inout< sc_dt::sc_int< W > > , sc_core::sc_inout< sc_dt::sc_uint< W > > , sc_dt::sc_fxnum , sc_dt::sc_fxnum_fast , sc_dt::sc_int_base , sc_dt::sc_proxy< X > , sc_dt::sc_signed , sc_dt::sc_uint_base , sc_dt::sc_unsigned , SMMUCommand , SparcISA::TlbEntry
• range_t : PCEventQueue
• RangeAddrMapper() : RangeAddrMapper
• rangeCheck() : BackingStore
• rangeList : X86ISA::IntelMP::CompatAddrSpaceMod
• RangeMap : AddrRangeMap< V, max_cache_size > , SparcISA::TlbMap
• rangeMRU : ArmISA::TLB
• ranges : Bridge::BridgeResponsePort , Network::AddrMapNode , SerialLink::SerialLinkResponsePort
• rank : DistIface
• Rank() : DRAMInterface::Rank
• rank : DRAMInterface::Rank , DRAMInterface::RankStats , MemPacket
• Rank() : NVMInterface::Rank
• rank : NVMInterface::Rank , TCPIface::NodeInfo
• rankBits : DramGen , HybridGen , NvmGen
• rankBitsDram : HybridGen
• rankBitsNvm : HybridGen
• rankDelay() : MemInterface
• rankParam() : DistIface
• ranks : Compressor::Multi::MultiStats , DRAMInterface , NVMInterface
• ranksPerChannel : MemInterface
• RankStats() : DRAMInterface::RankStats
• rankToRankDelay() : MemInterface
• rao() : ArmISA::ISA::MiscRegLUTEntry , ArmISA::ISA::MiscRegLUTEntryInitializer , RegisterRaoTest
• RaoSize : RegisterRaoTest
• RAS : BPredUnit
• RASIncorrect : BPredUnit::BPredUnitStats
• RASIndex : BPredUnit::PredictorHistory
• RASTarget : BPredUnit::PredictorHistory
• RASUsed : BPredUnit::BPredUnitStats
• rate : DefaultFetch< Impl >::FetchStatGroup
• Rate() : Stats::Units::Rate< T1, T2 >
• RateGen : Intel8254Timer
• Ratio() : Stats::Units::Ratio
• ratioOccsTaskId : BaseTags::BaseTagStats
• raw : ItsCommand::CommandEntry
• raw_ptr() : VecRegContainer< SIZE >
• rawData() : Gcn3ISA::ScalarOperand< DataType, Const, NumDwords >
• rawDataPtr() : Gcn3ISA::ScalarOperand< DataType, Const, NumDwords >
• RawDiskImage() : RawDiskImage
• rawDist : Wavefront
• RawImage() : Loader::RawImage
• rawInt : Pl011 , PL031 , Sp804::Timer
• rawIntTimer : CpuLocalTimer::Timer
• rawIntWatchdog : CpuLocalTimer::Timer
• RawISR : PL031 , Sp804::Timer
• RawIterator : sc_core::sc_vector_iter< Element, AccessPolicy >
• rawResetWatchdog : CpuLocalTimer::Timer
• rax : Trace::X86NativeTrace::ThreadState , X86ISA::CpuidResult , X86ISA::RemoteGDB::AMD64GdbRegCache::M5_ATTR_PACKED
• raz() : ArmISA::ISA::MiscRegLUTEntry , ArmISA::ISA::MiscRegLUTEntryInitializer , RegisterRazTest
• RazSize : RegisterRazTest
• rbp : Trace::X86NativeTrace::ThreadState , X86ISA::RemoteGDB::AMD64GdbRegCache::M5_ATTR_PACKED
• rbr : Uart8250::Registers
• rbrThr : Uart8250::Registers
• rbrThrDll : Uart8250::Registers
• rbx : Trace::X86NativeTrace::ThreadState , X86ISA::CpuidResult , X86ISA::RemoteGDB::AMD64GdbRegCache::M5_ATTR_PACKED
• rcSet : PowerISA::FloatOp , PowerISA::IntOp
• rctl : iGbReg::Regs
• rcx : Trace::X86NativeTrace::ThreadState , X86ISA::CpuidResult , X86ISA::RemoteGDB::AMD64GdbRegCache::M5_ATTR_PACKED
• rd1 : testbench
• RD_base : Gicv3Redistributor
• rdAccesses : X86ISA::TLB::TlbStats
• rdAllowedAt : MemInterface::Bank
• rdba : iGbReg::Regs
• rdBase : Gicv3Its
• rdGmReqsInPipe : Wavefront
• rdh : iGbReg::Regs
• rdi : Trace::X86NativeTrace::ThreadState , X86ISA::RemoteGDB::AMD64GdbRegCache::M5_ATTR_PACKED
• rdIdx() : AQLRingBuffer
• rdIdxPtr() : AQLRingBuffer
• rdlen : iGbReg::Regs
• rdLmReqsInPipe : Wavefront
• rdMisses : X86ISA::TLB::TlbStats
• rdPerTurnAround : MemCtrl::CtrlStats
• rdQLenPdf : MemCtrl::CtrlStats
• rdt : iGbReg::Regs
• rdToWrDlySameBG : DRAMInterface
• rdtr : iGbReg::Regs
• rdtrEvent : IGbE
• rdtrProcess() : IGbE
• rdx : Trace::X86NativeTrace::ThreadState , X86ISA::CpuidResult , X86ISA::RemoteGDB::AMD64GdbRegCache::M5_ATTR_PACKED
• rdy() : WaitClass
• rdyListEmpty : ScheduleStage::ScheduleStageStats
• rdyListNotEmpty : ScheduleStage::ScheduleStageStats
• read() : A9SCU , Access , AmbaFake , ArmSemihosting::File , ArmSemihosting::FileBase , ArmSemihosting::FileFeatures , ArmSemihosting::InPlaceArg , BadDevice , BaseRemoteGDB
• Read : BaseTLB
• read() : CircleBuf< T > , Clint , CopyEngine::CopyEngineChannel , CopyEngine , CowDiskImage , CpuLocalTimer , CpuLocalTimer::Timer , DiskImage , DumbTOD , EnergyCtrl , FastModel::GIC , Fifo< T > , FullO3CPU< Impl > , FVPBasePwrCtrl , Gcn3ISA::Operand , Gcn3ISA::ScalarOperand< DataType, Const, NumDwords > , Gcn3ISA::VecOperand< DataType, Const, NumDwords > , GenericPciHost , GenericTimerFrame , GenericTimerMem , GenericWatchdog , GicV2 , Gicv2m , Gicv3 , Gicv3Distributor , Gicv3Its , Gicv3Redistributor , GPUCommandProcessor , HDLcd , HSAPacketProcessor , I2CBus , I2CDevice , IdeController , IGbE , Intel8254Timer::Counter , Iob , IsaFake , LdsChunk , LSQ< Impl > , LSQUnit< Impl > , MaltaCChip , MaltaIO , MemPacket , MHU , MmDisk , MmioVirtIO , MuxingKvmGic , NoMaliGpu , NSGigE , PciVirtIO , PerfKvmCounter , PioDevice , PipeFDEntry , Pl011 , PL031 , Pl050 , Pl111 , Plic , PortProxy , ProtoInputStream
• READ : QoS::MemCtrl
• read() : RawDiskImage , RealViewCtrl::Device , RealViewCtrl , RealViewOsc , RealViewTemperatureSensor , RegisterBank< BankByteOrder > , RegisterBank< BankByteOrder >::Register< Data, RegByteOrder > , RegisterBank< BankByteOrder >::RegisterBase , RegisterBank< BankByteOrder >::RegisterBuf , RegisterBank< BankByteOrder >::RegisterRoFill
• Read : RegisterBankTest
• read : RiscvISA::Walker::WalkerState , sc_core::sc_fifo< T > , sc_core::sc_fifo_blocking_in_if< T > , sc_core::sc_fifo_in< T > , sc_core::sc_in< T > , sc_core::sc_in< bool > , sc_core::sc_in< sc_dt::sc_bigint< W > > , sc_core::sc_in< sc_dt::sc_biguint< W > > , sc_core::sc_in< sc_dt::sc_int< W > > , sc_core::sc_in< sc_dt::sc_logic > , sc_core::sc_in< sc_dt::sc_uint< W > > , sc_core::sc_inout< T > , sc_core::sc_inout< bool > , sc_core::sc_inout< sc_dt::sc_bigint< W > > , sc_core::sc_inout< sc_dt::sc_biguint< W > > , sc_core::sc_inout< sc_dt::sc_int< W > > , sc_core::sc_inout< sc_dt::sc_logic > , sc_core::sc_inout< sc_dt::sc_uint< W > > , sc_core::sc_signal< sc_dt::sc_bigint< W > > , sc_core::sc_signal< sc_dt::sc_biguint< W > > , sc_core::sc_signal< sc_dt::sc_int< W > > , sc_core::sc_signal< sc_dt::sc_uint< W > > , sc_core::sc_signal_in_if< T > , sc_core::sc_signal_in_if< bool > , sc_core::sc_signal_in_if< sc_dt::sc_bigint< W > > , sc_core::sc_signal_in_if< sc_dt::sc_biguint< W > > , sc_core::sc_signal_in_if< sc_dt::sc_int< W > > , sc_core::sc_signal_in_if< sc_dt::sc_logic > , sc_core::sc_signal_in_if< sc_dt::sc_uint< W > > , sc_dt::sc_fxnum_fast_observer , sc_dt::sc_fxnum_observer , sc_dt::sc_fxval_fast_observer , sc_dt::sc_fxval_observer , sc_gem5::ScSignalBaseT< T, WRITER_POLICY > , ScalarRegisterFile , SimpleDisk , SimpleUart , Sinic::Device , Sinic::Regs::Info , Sp804 , Sp804::Timer , Sp805 , Terminal , TesterDma , tlm::circular_buffer< T > , Trace::NativeTrace , TraceCPU::ElasticDataGen::InputStream , TraceCPU::FixedRetryGen::InputStream , TraceGen::InputStream , Uart8250 , Uart8250::Registers::BankedRegister , Uart8250::Registers::RWSwitchedRegister , UFSHostDevice , VectorRegisterFile , VGic , VirtDescriptor , VirtIO9PDiod , VirtIO9PProxy , VirtIO9PSocket , VirtIOBlock , VirtQueue::VirtRing< T > , VncServer , X86ISA::Cmos , X86ISA::I8042 , X86ISA::I82094AA , X86ISA::I8237 , X86ISA::I8254 , X86ISA::I8259 , X86ISA::Interrupts , X86ISA::LongModePTE , X86ISA::Speaker , X86ISA::Walker::WalkerState
• read1() : VncServer
• read32() : MHU
• read_acv : RiscvISA::TLB::TlbStats
• read_byte : Intel8254Timer::Counter
• read_cb : DRAMsim3
• read_data() : tlm::circular_buffer< T >
• read_dispatch_id : _amd_queue_s
• read_dispatch_id_field_base_byte_offset : _amd_queue_s
• read_event() : tlm::tlm_fifo< T >
• read_part() : sc_core::sc_int_part_if , sc_core::sc_signal< sc_dt::sc_bigint< W > > , sc_core::sc_signal< sc_dt::sc_biguint< W > > , sc_core::sc_signal< sc_dt::sc_int< W > > , sc_core::sc_signal< sc_dt::sc_uint< W > > , sc_core::sc_signed_part_if , sc_core::sc_uint_part_if , sc_core::sc_unsigned_part_if
• read_pointer_address : kfd_ioctl_create_queue_args
• Readable : MemBackdoor
• readable() : MemBackdoor
• ReadableBit : CacheBlk
• readAccess : FlashDevice::FlashDeviceStats
• readAccesses : ArmISA::TLB::TlbStats , RiscvISA::TLB::TlbStats
• readAddrDist : CommMonitor::MonitorStats
• readAddrMask : CommMonitor::MonitorStats
• readAll() : VirtIO9PProxy
• readArchCCReg() : FullO3CPU< Impl >
• readArchFloatReg() : FullO3CPU< Impl >
• readArchIntReg() : FullO3CPU< Impl >
• readArchVecElem() : FullO3CPU< Impl >
• readArchVecLane() : FullO3CPU< Impl >
• readArchVecPredReg() : FullO3CPU< Impl >
• readArchVecReg() : FullO3CPU< Impl >
• readBandwidthHist : CommMonitor::MonitorStats
• readBankedMiscReg() : Gicv3CPUInterface
• readBlob() : BackingStore , PortProxy , TestProxy
• readBlobPhys() : PortProxy
• readBufferSize : MemCtrl , MemInterface , QoS::MemSinkCtrl
• readBurstLengthHist : CommMonitor::MonitorStats
• readBursts : DRAMInterface::DRAMStats , MemCtrl::CtrlStats , NVMInterface::NVMStats
• readBW : BaseTrafficGen::StatGroup
• readByte() : SubBlock
• readBytes : CommMonitor::MonitorStats
• readCallback() : GPUCoalescer , Sequencer , UFSHostDevice , UFSHostDevice::UFSSCSIDevice
• readCCReg() : CheckerThreadContext< TC > , FullO3CPU< Impl > , Iris::ThreadContext , O3ThreadContext< Impl > , PhysRegFile , SimpleThread , ThreadContext
• readCCRegFlat() : CheckerThreadContext< TC > , FastModel::CortexA76TC , FastModel::CortexR52TC , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext
• readCCRegOperand() : BaseO3DynInst< Impl > , CheckerCPU , ExecContext , Minor::ExecContext , SimpleExecContext
• readClaim() : Plic
• ReadCleanReq : MemCmd
• readCommand() : IdeDisk , ItsCommand
• readComplete() : DRAMSim2 , DRAMsim3
• readCompleted : UFSHostDevice::UFSSCSIDevice
• readCompleteEvent : CopyEngine::CopyEngineChannel
• readCompressedTrace() : RubySystem
• readConfig() : IdeController , PciDevice , VirtIO9PBase , VirtIOBlock , VirtIOConsole , VirtIODeviceBase
• readConfigBlob() : VirtIODeviceBase
• readConstVal() : Gcn3ISA::GPUISA , GPUExecContext
• readControl() : GenericWatchdog , IdeDisk , SMMUv3
• ReadControllerRamBase : X86ISA::I8042
• readCopyBytes() : CopyEngine::CopyEngineChannel
• readCopyBytesComplete() : CopyEngine::CopyEngineChannel
• readCounter() : Intel8254Timer , X86ISA::I8254
• readCpu() : BaseGicRegisters , GicV2 , KvmKernelGicV2
• readCtrl() : VGic
• readData() : MC146818 , SerialDevice , SerialNullDevice , Terminal
• readDataOut() : X86ISA::I8042
• readDataTimed() : ArmISA::Stage2MMU
• readDataUntimed() : ArmISA::Stage2MMU
• readDevice() : UFSHostDevice
• readDeviceTable() : ItsProcess
• readDisk() : IdeDisk
• readDispIdOffset : GPUCommandProcessor::ReadDispIdOffsetDmaEvent
• ReadDispIdOffsetDmaEvent() : GPUCommandProcessor::ReadDispIdOffsetDmaEvent
• readDistributor() : BaseGicRegisters , GicV2 , KvmKernelGicV2
• readDone() : UFSHostDevice
• readDoneEvent : UFSHostDevice
• readEnergy : DRAMInterface::RankStats
• readEntries : DRAMInterface::Rank
• readEntryLPI() : Gicv3Redistributor
• reader() : RegisterBank< BankByteOrder >::Register< Data, RegByteOrder >
• readEvent : Pl111
• ReadExReq : MemCmd
• ReadExResp : MemCmd
• readFillStart() : SparcProcess
• readFlash() : UFSHostDevice::UFSSCSIDevice
• readFloatReg() : CheckerThreadContext< TC > , FullO3CPU< Impl > , Iris::ThreadContext , O3ThreadContext< Impl > , PhysRegFile , SimpleThread , ThreadContext
• readFloatRegFlat() : CheckerThreadContext< TC > , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext
• readFloatRegOperandBits() : BaseO3DynInst< Impl > , CheckerCPU , ExecContext , Minor::ExecContext , SimpleExecContext
• readFramebuffer() : Pl111
• readFreeEntries() : DefaultRename< Impl >
• readFSReg() : SparcISA::ISA
• ReadFunc : RegisterBank< BankByteOrder >::Register< Data, RegByteOrder >
• readFuncExeInst() : CheckerThreadContext< TC > , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext , ThreadState
• readGarbage() : UFSHostDevice
• readGarbageEventQueue : UFSHostDevice
• readHeader() : VirtQueue::VirtRing< T >
• readHeadInst() : ROB< Impl >
• readHits : ArmISA::TLB::TlbStats , RiscvISA::TLB::TlbStats
• readId() : AmbaDevice
• readIE() : RiscvISA::Interrupts
• readIir() : Uart8250
• readIndex : HSAQueueDescriptor
• ReadInputPort : X86ISA::I8042
• readIntReg() : CheckerThreadContext< TC > , FastModel::CortexR52TC , FullO3CPU< Impl > , Iris::ThreadContext , O3ThreadContext< Impl > , PhysRegFile , SimpleThread , ThreadContext
• readIntRegFlat() : CheckerThreadContext< TC > , FastModel::CortexA76TC , FastModel::CortexR52TC , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext
• readIntRegOperand() : BaseO3DynInst< Impl > , CheckerCPU , ExecContext , Minor::ExecContext , SimpleExecContext
• readIob() : Iob
• readIP() : RiscvISA::Interrupts
• readIrqCollectionTable() : ItsProcess
• readIrqTranslationTable() : ItsProcess
• readIRR : X86ISA::I8259
• readJBus() : Iob
• readLastActivate() : CheckerThreadContext< TC > , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext , ThreadState
• readLastSuspend() : CheckerThreadContext< TC > , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext , ThreadState
• readLatency : FlashDevice::FlashDeviceStats , FlashDevice
• readLatencyHist : CommMonitor::MonitorStats
• readLength() : SCMI::AgentChannel
• readLengthEvent : SCMI::AgentChannel
• readLinearHist : StackDistProbe::StackDistProbeStats
• readLogHist : StackDistProbe::StackDistProbeStats
• readMem() : AtomicSimpleCPU , BaseSimpleCPU , CheckerCPU , ExecContext
• ReadMem() : Shader
• readMem() : SimpleExecContext
• readMemAccPredicate() : BaseDynInst< Impl > , CheckerCPU , ExecContext , Minor::ExecContext , Minor::MinorDynInst , SimpleExecContext , SimpleThread
• readMemNoEffect() : Trace::TarmacParserRecord
• readMemory() : AbstractNVM , FlashDevice
• readMessage() : SCMI::AgentChannel
• readMessageEvent : SCMI::AgentChannel
• readMiscReg() : ArmISA::BaseISADevice , ArmISA::DummyISADevice , ArmISA::ISA , ArmISA::PMU , BaseO3DynInst< Impl > , CheckerCPU , CheckerThreadContext< TC > , ExecContext , FullO3CPU< Impl > , Gcn3ISA::GPUISA , GenericTimer , GenericTimerISA , Gicv3CPUInterface , GPUExecContext , Iris::ThreadContext , Minor::ExecContext , MipsISA::ISA , O3ThreadContext< Impl > , PowerISA::ISA , RiscvISA::ISA , SimpleExecContext , SimpleThread , SparcISA::ISA , ThreadContext , X86ISA::ISA
• readMiscRegInt() : ArmISA::PMU
• readMiscRegNoEffect() : ArmISA::ISA , CheckerCPU , CheckerThreadContext< TC > , FastModel::CortexR52TC , FullO3CPU< Impl > , Iris::ThreadContext , Minor::ExecContext , MipsISA::ISA , O3ThreadContext< Impl > , PowerISA::ISA , RiscvISA::ISA , SimpleThread , SparcISA::ISA , ThreadContext , X86ISA::ISA
• readMiscRegOperand() : BaseO3DynInst< Impl > , CheckerCPU , ExecContext , Minor::ExecContext , SimpleExecContext
• readMisses : ArmISA::TLB::TlbStats , RiscvISA::TLB::TlbStats
• readMSIP() : Clint
• readNegConstReg() : Gcn3ISA::GPUISA
• readNextWindow() : TraceCPU::ElasticDataGen
• readObservations : MemChecker::ByteTracker
• ReadOnly : EmulationPageTable , kfd_memory_exception_failure
• readonly : RawDiskImage , RegisterBank< BankByteOrder >::Register< Data, RegByteOrder > , X86ISA::LongModePTE
• readonlyMemInsts : ComputeUnit::ComputeUnitStats
• readonlyReads : ComputeUnit::ComputeUnitStats
• readonlyWrites : ComputeUnit::ComputeUnitStats
• ReadOutputPort : X86ISA::I8042
• readPC() : ArmISA::ArmStaticInst
• readPendingNum : UFSHostDevice
• readPercent : HybridGen , StochasticGen
• readPktSize : MemCtrl::CtrlStats
• readPorts : RubyTester
• readPosConstReg() : Gcn3ISA::GPUISA
• readPredicate() : BaseDynInst< Impl > , CheckerCPU , ExecContext , Minor::ExecContext , Minor::MinorDynInst , SimpleExecContext , SimpleThread
• readPredTaken() : BaseDynInst< Impl >
• readPredTarg() : BaseDynInst< Impl >
• readPtr : FetchUnit::FetchBufDesc
• readQueue : MemCtrl , QoS::MemSinkCtrl
• readQueueFull() : MemCtrl , QoS::MemSinkCtrl
• readQueueSizes : QoS::MemCtrl
• readRbr() : Uart8250
• readReadyEvent : NVMInterface
• readReadyQueue : NVMInterface
• readRefresh() : GenericWatchdog
• readReg() : HDLcd , NoMaliGpu , O3ThreadContext< Impl > , X86ISA::I82094AA , X86ISA::Interrupts
• readRegister() : X86ISA::Cmos
• readRegRaw() : NoMaliGpu
• ReadReq : MemCmd
• readReqDelay : SimpleMemDelay
• readReqs : MemCtrl::CtrlStats
• ReadResp : MemCmd
• readRespDelay : SimpleMemDelay
• ReadRespWithInvalidate : MemCmd
• readRowHitRate : DRAMInterface::DRAMStats
• readRowHits : DRAMInterface::DRAMStats
• reads() : ArmISA::ISA::MiscRegLUTEntryInitializer , ROB< Impl >::ROBStats
• readScalar() : Gcn3ISA::VecOperand< DataType, Const, NumDwords >
• readsEXEC() : GPUDynInst , GPUStaticInst
• readsExecMask() : GPUDynInst
• readsFlatScratch() : GPUDynInst
• ReadSharedReq : MemCmd
• readsMode() : GPUDynInst , GPUStaticInst
• readSpecialVal() : Gcn3ISA::ScalarOperand< DataType, Const, NumDwords >
• readsPerWrite : Wavefront::WavefrontStats
• readSpillStart() : SparcProcess
• readSrc() : Gcn3ISA::VecOperand< DataType, Const, NumDwords >
• readsSCC() : GPUDynInst , GPUStaticInst
• readStallSignals() : DefaultDecode< Impl > , DefaultRename< Impl >
• readStatus() : SCMI::AgentChannel
• readStCondFailures() : BaseDynInst< Impl > , CheckerCPU , CheckerThreadContext< TC > , ExecContext , Iris::ThreadContext , Minor::ExecContext , O3ThreadContext< Impl > , SimpleExecContext , SimpleThread , ThreadContext
• readsThisTime : MemCtrl
• readString() : ArmSemihosting , PortProxy , X86ISA::SMBios::SMBiosStructure
• readsVCC() : GPUDynInst , GPUStaticInst
• readsWaitingToIssue() : NVMInterface
• readTailInst() : ROB< Impl >
• ReadTestInputs : X86ISA::I8042
• readToWriteDelay() : MemInterface
• readTrans : CommMonitor::MonitorStats
• readTransHist : CommMonitor::MonitorStats
• readVCpu() : VGic
• readVec16BitLaneOperand() : BaseO3DynInst< Impl > , CheckerCPU , ExecContext , Minor::ExecContext , SimpleExecContext
• readVec16BitLaneReg() : CheckerThreadContext< TC > , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext
• readVec32BitLaneOperand() : BaseO3DynInst< Impl > , CheckerCPU , ExecContext , Minor::ExecContext , SimpleExecContext
• readVec32BitLaneReg() : CheckerThreadContext< TC > , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext
• readVec64BitLaneOperand() : BaseO3DynInst< Impl > , CheckerCPU , ExecContext , Minor::ExecContext , SimpleExecContext
• readVec64BitLaneReg() : CheckerThreadContext< TC > , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext
• readVec8BitLaneOperand() : BaseO3DynInst< Impl > , CheckerCPU , ExecContext , Minor::ExecContext , SimpleExecContext
• readVec8BitLaneReg() : CheckerThreadContext< TC > , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext
• readVecElem() : CheckerThreadContext< TC > , FullO3CPU< Impl > , Iris::ThreadContext , O3ThreadContext< Impl > , PhysRegFile , SimpleThread , ThreadContext
• readVecElemFlat() : CheckerThreadContext< TC > , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext
• readVecElemOperand() : BaseO3DynInst< Impl > , CheckerCPU , ExecContext , Minor::ExecContext , SimpleExecContext
• readVecLane() : FullO3CPU< Impl > , PhysRegFile , SimpleThread
• readVecLaneFlat() : O3ThreadContext< Impl > , SimpleThread
• readVecLaneOperand() : SimpleExecContext
• readVecPredReg() : CheckerThreadContext< TC > , FullO3CPU< Impl > , Iris::ThreadContext , O3ThreadContext< Impl > , PhysRegFile , SimpleThread , ThreadContext
• readVecPredRegFlat() : CheckerThreadContext< TC > , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext
• readVecPredRegOperand() : BaseO3DynInst< Impl > , CheckerCPU , ExecContext , Minor::ExecContext , SimpleExecContext
• readVecReg() : CheckerThreadContext< TC > , FastModel::CortexR52TC , FullO3CPU< Impl > , Iris::ThreadContext , O3ThreadContext< Impl > , PhysRegFile , SimpleThread , ThreadContext
• readVecRegFlat() : CheckerThreadContext< TC > , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext
• readVecRegOperand() : BaseO3DynInst< Impl > , CheckerCPU , ExecContext , Minor::ExecContext , SimpleExecContext
• readWithMask() : RegisterBank< BankByteOrder >
• readWord() : PixelConverter
• readWriteable() : ScalarRegisterFile , VectorRegisterFile
• ReadWriteVal : Intel8254Timer
• Ready : RiscvISA::Walker::WalkerState
• ready() : sc_gem5::Process , sc_gem5::Scheduler , ScoreboardCheckStage , test , testbench
• Ready : X86ISA::Walker::WalkerState
• readyEvent : sc_gem5::Scheduler
• readyInst() : ScheduleToExecute
• ReadyInstQueue : InstructionQueue< Impl >
• readyInsts : InstructionQueue< Impl >
• readyIt : InstructionQueue< Impl >
• readyIter : MSHR , WriteQueueEntry
• readyList : Queue< Entry > , TraceCPU::ElasticDataGen
• readyListMethods : sc_gem5::Scheduler
• readyListThreads : sc_gem5::Scheduler
• ReadyPriority : sc_gem5::Scheduler
• readyRegs : BaseDynInst< Impl >
• readySrcIdx() : BaseDynInst< Impl >::Regs
• readyTime : MemPacket , QueueEntry , QueueEntry::Target
• readyToCkpt() : DistIface
• readyToCommit() : BaseDynInst< Impl >
• readyToExit() : DistIface
• readyToIssue() : BaseDynInst< Impl >
• readyWFs() : ScoreboardCheckToSchedule
• real : SparcISA::TlbRange
• RealView() : RealView
• RealViewCtrl() : RealViewCtrl
• RealViewOsc() : RealViewOsc
• RealViewTemperatureSensor() : RealViewTemperatureSensor
• reanalyzeAllMessages() : MessageBuffer
• reanalyzeList() : MessageBuffer
• reanalyzeMessages() : MessageBuffer
• reason : Minor::BranchData
• Reason : Minor::BranchData
• reason : RiscvISA::IllegalInstFault
• received() : ExpectedMap< RespType, DataType >::ExpectedState< Type > , ExpectedMap< RespType, DataType >
• receiveData() : ExpectedMap< RespType, DataType >
• receivedDataType() : ExpectedMap< RespType, DataType >
• receiveDeviceInterrupt() : Iob
• receivedRespType() : ExpectedMap< RespType, DataType >
• receivedType() : ExpectedMap< RespType, DataType >::ExpectedState< Type >
• receiveJBusInterrupt() : Iob
• receiver : BasicSignal
• receiveResp() : ExpectedMap< RespType, DataType >
• receiveWriteCompleteAck() : PendingWriteInst
• RECEIVING_ADDR : I2CBus
• RECEIVING_DATA : I2CBus
• RECENCY() : MultiperspectivePerceptron::RECENCY
• recency_stack : MultiperspectivePerceptron::ThreadData
• RECENCYPOS() : MultiperspectivePerceptron::RECENCYPOS
• recencypos_mask : MultiperspectivePerceptron
• recent : DecodeCache::AddrMap< Value, CacheChunkShift >
• reconstructionEntries : Prefetcher::STeMS
• reconstructSequence() : Prefetcher::STeMS
• Record : ElasticTrace , TraceCPU::ElasticDataGen
• record_mask : MultiperspectivePerceptron
• recordAccess() : FALRU::CacheTracking
• recordArm() : Workload
• recordCacheContents() : CacheMemory
• recordCacheTrace() : AbstractController
• recordExecTick() : ElasticTrace
• recordIndirect() : IndirectPredictor , SimpleIndirectPredictor
• recordMissLatency() : GPUCoalescer , Sequencer
• recordPCChange() : CheckerCPU
• recordProducer() : InstructionQueue< Impl >
• recordQuiesce() : Workload
• recordRequestType() : CacheMemory , DirectoryMemory , DMASequencer , Sequencer
• recordResult() : BaseDynInst< Impl >
• RecordResult : BaseDynInst< Impl >
• recordTarget() : IndirectPredictor , SimpleIndirectPredictor
• recordToCommTick() : ElasticTrace
• recordTurnaroundStats() : QoS::MemCtrl
• RecordType : ElasticTrace , TraceCPU::ElasticDataGen
• RecoverInst : BaseDynInst< Impl >
• recoveryPage : UFSHostDevice::UFSSCSIDevice
• recreateable() : OutputFile< StreamType > , OutputStream
• recv() : BaseRemoteGDB , PS2Device , PS2Keyboard , PS2Mouse , PS2TouchKit
• recvAtomic() : AbstractController , AddrMapper::MapperResponsePort , AddrMapper , AtomicResponseProtocol , BaseCache::CpuSidePort , BaseCache , Bridge::BridgeResponsePort , Cache , CoherentXBar::CoherentXBarResponsePort , CommMonitor::MonitorResponsePort , CommMonitor , ComputeUnit::DataPort , ComputeUnit::DTLBPort , ComputeUnit::ITLBPort , ComputeUnit::LDSPort , ComputeUnit::SQCPort , DRAMSim2::MemoryPort , DRAMSim2 , DRAMsim3::MemoryPort , DRAMsim3 , GPUCoalescer::GMTokenPort , LdsState::CuSidePort , MemCheckerMonitor::MonitorResponsePort , MemCheckerMonitor , MemCtrl::MemoryPort , MemCtrl , MemDelay::ResponsePort , NoncoherentCache , NoncoherentXBar::NoncoherentXBarResponsePort , PioPort< Device > , QoS::MemSinkCtrl::MemoryPort , QoS::MemSinkCtrl , RubyPort::MemResponsePort , RubyPort::PioResponsePort , sc_gem5::Gem5ToTlmBridge< BITWIDTH >::BridgeResponsePort , sc_gem5::Gem5ToTlmBridge< BITWIDTH > , SerialLink::SerialLinkResponsePort , SimpleCache::CPUSidePort , SimpleMemobj::CPUSidePort , SimpleMemory::MemoryPort , SimpleMemory , SimpleTimingPort , SMMUATSDevicePort , SMMUControlPort , SMMUDevicePort , SMMUv3 , SMMUv3DeviceInterface , StubSlavePort , TLBCoalescer::CpuSidePort , TLBCoalescer::MemSidePort , X86ISA::GpuTLB::CpuSidePort , X86ISA::GpuTLB::MemSidePort , X86ISA::IntResponsePort< Device >
• recvAtomicBackdoor() : AtomicResponseProtocol , CoherentXBar::CoherentXBarResponsePort , CoherentXBar , MemCtrl::MemoryPort , MemCtrl , NoncoherentXBar::NoncoherentXBarResponsePort , NoncoherentXBar , ResponsePort , sc_gem5::Gem5ToTlmBridge< BITWIDTH >::BridgeResponsePort , sc_gem5::Gem5ToTlmBridge< BITWIDTH > , SimpleMemory::MemoryPort , SimpleMemory
• recvAtomicSnoop() : AddrMapper::MapperRequestPort , AddrMapper , AtomicRequestProtocol , AtomicSimpleCPU::AtomicCPUDPort , BaseCache::MemSidePort , BaseCache , BaseTrafficGen::TrafficGenPort , Cache , CoherentXBar::CoherentXBarRequestPort , CoherentXBar , CommMonitor::MonitorRequestPort , CommMonitor , MemCheckerMonitor::MonitorRequestPort , MemCheckerMonitor , MemDelay::RequestPort , MemTest::CpuPort , NoncoherentCache , RequestPort
• recvCommand() : CopyEngine::CopyEngineChannel
• recvCutText() : VncServer
• recvDone : DistIface::RecvScheduler , EtherInt
• recvFunctional() : AddrMapper::MapperResponsePort , AddrMapper , BaseCache::CpuSidePort , Bridge::BridgeResponsePort , CoherentXBar::CoherentXBarResponsePort , CoherentXBar , CommMonitor::MonitorResponsePort , CommMonitor , ComputeUnit::DataPort , ComputeUnit::DTLBPort , ComputeUnit::ITLBPort , ComputeUnit::LDSPort , ComputeUnit::SQCPort , DRAMSim2::MemoryPort , DRAMSim2 , DRAMsim3::MemoryPort , DRAMsim3 , FunctionalResponseProtocol , GPUCoalescer::GMTokenPort , LdsState::CuSidePort , MemCheckerMonitor::MonitorResponsePort , MemCheckerMonitor , MemCtrl::MemoryPort , MemCtrl , MemDelay::ResponsePort , NoncoherentXBar::NoncoherentXBarResponsePort , NoncoherentXBar , QoS::MemSinkCtrl::MemoryPort , QoS::MemSinkCtrl , RubyPort::MemResponsePort , RubyPort::PioResponsePort , sc_gem5::Gem5ToTlmBridge< BITWIDTH >::BridgeResponsePort , sc_gem5::Gem5ToTlmBridge< BITWIDTH > , SerialLink::SerialLinkResponsePort , SimpleCache::CPUSidePort , SimpleMemobj::CPUSidePort , SimpleMemory::MemoryPort , SimpleMemory , SimpleTimingPort , SMMUATSDevicePort , SMMUDevicePort , StubSlavePort , TLBCoalescer::CpuSidePort , TLBCoalescer::MemSidePort , X86ISA::GpuTLB::CpuSidePort , X86ISA::GpuTLB::MemSidePort
• recvFunctionalSnoop() : AddrMapper::MapperRequestPort , AddrMapper , AtomicSimpleCPU::AtomicCPUDPort , BaseCache::MemSidePort , BaseTrafficGen::TrafficGenPort , CoherentXBar::CoherentXBarRequestPort , CoherentXBar , CommMonitor::MonitorRequestPort , CommMonitor , FunctionalRequestProtocol , LSQ< Impl >::DcachePort , MemCheckerMonitor::MonitorRequestPort , MemCheckerMonitor , MemDelay::RequestPort , MemTest::CpuPort , Minor::LSQ::DcachePort , PortProxy , RequestPort , sc_gem5::Gem5ToTlmBridge< BITWIDTH > , StubSlavePort , TimingSimpleCPU::DcachePort , TraceCPU::DcachePort
• recvHeader() : DistIface , TCPIface
• recvKeyboardInput() : VncServer
• recvMessage() : X86ISA::Interrupts
• recvPacket() : DistEtherLink::LocalIface , DistIface , EtherInt , EtherLink::Interface , EtherSwitch::Interface , EtherTapInt , IGbEInt , NSGigE , NSGigEInt , RiscvISA::Walker::WalkerState , Sinic::Device , Sinic::Interface , TCPIface , X86ISA::Walker::WalkerState
• recvPointerInput() : VncServer
• recvRangeChange() : AddrMapper::MapperRequestPort , AddrMapper , BaseXBar , CoherentXBar::CoherentXBarRequestPort , CommMonitor::MonitorRequestPort , CommMonitor , ComputeUnit::DataPort , ComputeUnit::DTLBPort , ComputeUnit::ITLBPort , ComputeUnit::LDSPort , ComputeUnit::SQCPort , HMCController , LdsState::CuSidePort , MemCheckerMonitor::MonitorRequestPort , MemCheckerMonitor , MemDelay::RequestPort , NoncoherentXBar::NoncoherentXBarRequestPort , RequestPort , RubyPort::MemRequestPort , RubyPort::PioRequestPort , sc_gem5::TlmToGem5Bridge< BITWIDTH >::BridgeRequestPort , sc_gem5::TlmToGem5Bridge< BITWIDTH > , SimpleCache::MemSidePort , SimpleMemobj::MemSidePort , TLBCoalescer::CpuSidePort , TLBCoalescer::MemSidePort , X86ISA::GpuTLB::CpuSidePort , X86ISA::GpuTLB::MemSidePort
• recvReal() : EtherTapBase , EtherTapStub
• recvReqRetry() : AbstractController::MemoryPort , AddrMapper::MapperRequestPort , AddrMapper , AtomicSimpleCPU::AtomicCPUPort , BaseKvmCPU::KVMCpuPort , BaseTrafficGen , BaseTrafficGen::TrafficGenPort , Bridge::BridgeRequestPort , CoherentXBar::CoherentXBarRequestPort , CoherentXBar , CoherentXBar::SnoopRespPort , CommMonitor::MonitorRequestPort , CommMonitor , ComputeUnit::DataPort , ComputeUnit::DTLBPort , ComputeUnit::GMTokenPort , ComputeUnit::ITLBPort , ComputeUnit::LDSPort , ComputeUnit::ScalarDataPort , ComputeUnit::ScalarDTLBPort , ComputeUnit::SQCPort , DefaultFetch< Impl >::IcachePort , DefaultFetch< Impl > , DmaPort , GarnetSyntheticTraffic::CpuPort , Gicv3Its::DataPort , Gicv3Its , LSQ< Impl >::DcachePort , LSQ< Impl > , MemCheckerMonitor::MonitorRequestPort , MemCheckerMonitor , MemTest::CpuPort , Minor::Fetch1::IcachePort , Minor::Fetch1 , Minor::LSQ::DcachePort , Minor::LSQ , NoncoherentXBar::NoncoherentXBarRequestPort , NoncoherentXBar , ProtocolTester::GMTokenPort , ProtocolTester::SeqPort , QueuedRequestPort , RiscvISA::Walker , RiscvISA::Walker::WalkerPort , RubyDirectedTester::CpuPort , RubyTester::CpuPort , sc_gem5::TlmToGem5Bridge< BITWIDTH >::BridgeRequestPort , sc_gem5::TlmToGem5Bridge< BITWIDTH > , SerialLink::SerialLinkRequestPort , SimpleCache::MemSidePort , SimpleMemobj::MemSidePort , SMMURequestPort , SMMUTableWalkPort , SMMUv3 , System::SystemPort , TimingRequestProtocol , TimingSimpleCPU::DcachePort , TimingSimpleCPU::IcachePort , TLBCoalescer::CpuSidePort , TLBCoalescer::MemSidePort , TraceCPU::DcachePort , TraceCPU::IcachePort , X86ISA::GpuTLB::CpuSidePort , X86ISA::GpuTLB::MemSidePort , X86ISA::Walker , X86ISA::Walker::WalkerPort
• recvResponse() : X86ISA::I82094AA
• recvRespRetry() : AddrMapper::MapperResponsePort , AddrMapper , Bridge::BridgeResponsePort , CommMonitor::MonitorResponsePort , CommMonitor , DRAMSim2::MemoryPort , DRAMSim2 , DRAMsim3::MemoryPort , DRAMsim3 , LdsState::CuSidePort , MemCheckerMonitor::MonitorResponsePort , MemCheckerMonitor , QueuedResponsePort , sc_gem5::Gem5ToTlmBridge< BITWIDTH >::BridgeResponsePort , sc_gem5::Gem5ToTlmBridge< BITWIDTH > , SerialLink::SerialLinkResponsePort , SimpleCache::CPUSidePort , SimpleMemobj::CPUSidePort , SimpleMemory::MemoryPort , SimpleMemory , StubSlavePort , TimingResponseProtocol , TLBCoalescer::CpuSidePort , TLBCoalescer::MemSidePort , TokenResponsePort , X86ISA::GpuTLB::CpuSidePort
• recvRetry() : BaseXBar::Layer< SrcType, DstType > , LdsState::CuSidePort , LSQUnit< Impl > , MemTest
• recvRetrySnoopResp() : CommMonitor::MonitorRequestPort , CommMonitor , QueuedRequestPort , RequestPort , TimingRequestProtocol
• recvScheduler : DistIface
• RecvScheduler() : DistIface::RecvScheduler
• recvSimulated() : EtherTapBase
• recvTCP() : TCPIface
• recvThread : DistIface
• recvThreadFunc() : DistIface
• recvThreadsNum : DistIface
• recvTick : EtherSwitch::Interface::PortFifoEntry , SMMUTranslationProcess
• recvTime : QueueEntry::Target
• recvTimingReq() : AddrMapper::MapperResponsePort , AddrMapper , BaseCache::CpuSidePort , BaseCache , Bridge::BridgeResponsePort , Cache , CoherentXBar::CoherentXBarResponsePort , CoherentXBar , CommMonitor::MonitorResponsePort , CommMonitor , DRAMSim2::MemoryPort , DRAMSim2 , DRAMsim3::MemoryPort , DRAMsim3 , GPUCoalescer::GMTokenPort , HMCController , LdsState::CuSidePort , MemCheckerMonitor::MonitorResponsePort , MemCheckerMonitor , MemCtrl::MemoryPort , MemCtrl , MemDelay::ResponsePort , NoncoherentCache , NoncoherentXBar::NoncoherentXBarResponsePort , NoncoherentXBar , QoS::MemSinkCtrl::MemoryPort , QoS::MemSinkCtrl , RubyPort::MemResponsePort , RubyPort::PioResponsePort , sc_gem5::Gem5ToTlmBridge< BITWIDTH >::BridgeResponsePort , sc_gem5::Gem5ToTlmBridge< BITWIDTH > , SerialLink::SerialLinkResponsePort , SimpleCache::CPUSidePort , SimpleMemobj::CPUSidePort , SimpleMemory::MemoryPort , SimpleMemory , SimpleTimingPort , SMMUATSDevicePort , SMMUDevicePort , SMMUv3 , SMMUv3DeviceInterface , StubSlavePort , TimingResponseProtocol , TLBCoalescer::CpuSidePort , X86ISA::GpuTLB::CpuSidePort
• recvTimingResp() : AbstractController::MemoryPort , AbstractController , AddrMapper::MapperRequestPort , AddrMapper , AtomicSimpleCPU::AtomicCPUPort , BaseCache::MemSidePort , BaseCache , BaseKvmCPU::KVMCpuPort , BaseTrafficGen , BaseTrafficGen::TrafficGenPort , Bridge::BridgeRequestPort , CoherentXBar::CoherentXBarRequestPort , CoherentXBar , CoherentXBar::SnoopRespPort , CommMonitor::MonitorRequestPort , CommMonitor , ComputeUnit::DataPort , ComputeUnit::DTLBPort , ComputeUnit::GMTokenPort , ComputeUnit::ITLBPort , ComputeUnit::LDSPort , ComputeUnit::ScalarDataPort , ComputeUnit::ScalarDTLBPort , ComputeUnit::SQCPort , DefaultFetch< Impl >::IcachePort , DmaPort , GarnetSyntheticTraffic::CpuPort , Gicv3Its::DataPort , Gicv3Its , LSQ< Impl >::DcachePort , LSQ< Impl >::LSQRequest , LSQ< Impl > , LSQ< Impl >::SingleDataRequest , LSQ< Impl >::SplitDataRequest , LSQUnit< Impl > , MemCheckerMonitor::MonitorRequestPort , MemCheckerMonitor , MemDelay::RequestPort , MemTest::CpuPort , Minor::Fetch1::IcachePort , Minor::Fetch1 , Minor::LSQ::DcachePort , Minor::LSQ , NoncoherentCache , NoncoherentXBar::NoncoherentXBarRequestPort , NoncoherentXBar , ProtocolTester::GMTokenPort , ProtocolTester::SeqPort , RiscvISA::Walker , RiscvISA::Walker::WalkerPort , RubyDirectedTester::CpuPort , RubyPort::MemRequestPort , RubyPort::PioRequestPort , RubyPort , RubyTester::CpuPort , sc_gem5::TlmToGem5Bridge< BITWIDTH >::BridgeRequestPort , sc_gem5::TlmToGem5Bridge< BITWIDTH > , SerialLink::SerialLinkRequestPort , SimpleCache::MemSidePort , SimpleMemobj::MemSidePort , SMMUATSMemoryPort , SMMURequestPort , SMMUTableWalkPort , SMMUv3 , System::SystemPort , TimingRequestProtocol , TimingSimpleCPU::DcachePort , TimingSimpleCPU::IcachePort , TLBCoalescer::MemSidePort , TraceCPU::DcachePort , TraceCPU::IcachePort , X86ISA::GpuTLB::MemSidePort , X86ISA::IntRequestPort< Device > , X86ISA::Walker , X86ISA::Walker::WalkerPort
• recvTimingSnoopReq() : AddrMapper::MapperRequestPort , AddrMapper , BaseCache::MemSidePort , BaseCache , BaseTrafficGen::TrafficGenPort , Cache , CoherentXBar::CoherentXBarRequestPort , CoherentXBar , CommMonitor::MonitorRequestPort , CommMonitor , LSQ< Impl >::DcachePort , LSQ< Impl > , MemCheckerMonitor::MonitorRequestPort , MemCheckerMonitor , MemDelay::RequestPort , MemTest::CpuPort , Minor::LSQ::DcachePort , Minor::LSQ , NoncoherentCache , RequestPort , TimingRequestProtocol , TimingSimpleCPU::DcachePort , TraceCPU::DcachePort , TraceCPU::IcachePort
• recvTimingSnoopResp() : AddrMapper::MapperResponsePort , AddrMapper , BaseCache::CpuSidePort , BaseCache , Cache , CoherentXBar::CoherentXBarResponsePort , CoherentXBar , CommMonitor::MonitorResponsePort , CommMonitor , MemCheckerMonitor::MonitorResponsePort , MemCheckerMonitor , MemDelay::ResponsePort , NoncoherentCache , ResponsePort , sc_gem5::Gem5ToTlmBridge< BITWIDTH >::BridgeResponsePort , sc_gem5::Gem5ToTlmBridge< BITWIDTH > , StubSlavePort , TimingResponseProtocol
• recvTMsg() : VirtIO9PBase , VirtIO9PProxy
• recvTokens() : TokenManager , TokenRequestPort
• recvTouchKit() : PS2TouchKit
• recycle() : MessageBuffer , WireBuffer
• red : BmpWriter::BmpPixel32 , Pixel , PngWriter::PngPixel24 , rgb_t
• red_select : HDLcd
• Red_Select : HDLcd
• RedirectPath() : RedirectPath
• redirectPaths : System
• redirectRegVHE() : ArmISA::ISA
• redirTable : X86ISA::I82094AA
• redist : FastModel::ScxEvsCortexA76< Types >
• redistRange : Gicv3
• redistributor : Gicv3CPUInterface
• redistributors : FastModel::GIC , Gicv3
• redistSize : Gicv3
• redmax : VncInput::PixelFormat
• redshift : VncInput::PixelFormat
• REF_DRAIN : DRAMInterface
• REF_IDLE : DRAMInterface
• REF_PD_EXIT : DRAMInterface
• REF_PRE : DRAMInterface
• REF_RUN : DRAMInterface
• REF_SREF_EXIT : DRAMInterface
• REF_START : DRAMInterface
• refcount : HardBreakpoint
• refCount : ReplacementPolicy::LFU::LFUReplData , sc_gem5::Process
• RefCounted() : RefCounted
• refCounter : LdsState
• RefCountingPtr() : RefCountingPtr< T >
• reference : CircularQueue< T >::iterator , CircularQueue< T > , sc_core::sc_vector_iter< Element, AccessPolicy > , System::Threads::const_iterator
• referenced : IniFile::Entry , IniFile::Section
• referenceData : MemTest
• references : ThermalModel
• refresh() : GenericWatchdog , PerfKvmCounter
• refreshDueAt : DRAMInterface::Rank
• refreshEnergy : DRAMInterface::RankStats
• refreshEvent : DRAMInterface::Rank
• refreshFrame : GenericWatchdog
• refreshNext : CopyEngine::CopyEngineChannel
• RefreshOffset : GenericWatchdog
• refreshState : DRAMInterface::Rank
• RefreshState : DRAMInterface
• Reg() : CopyEngineReg::Reg< T >
• reg() : EtherBus
• Reg() : iGbReg::Regs::Reg< T >
• reg : RegisterBufTest , RegisterLBufTest , sc_gem5::Scheduler , TimingExprReadIntReg , TypedRegisterTest , X86ISA::EmulEnv
• reg0 : ArmISA::Mult3 , RegisterBankTest
• reg1 : ArmISA::Mult3 , RegisterBankTest
• reg2 : ArmISA::Mult3 , RegisterBankTest
• reg3 : ArmISA::Mult4
• REG_D : Trace::TarmacBaseRecord
• REG_MISC : Trace::TarmacBaseRecord
• REG_P : Trace::TarmacBaseRecord
• reg_pmceid0 : ArmISA::PMU
• reg_pmceid1 : ArmISA::PMU
• reg_pmcnten : ArmISA::PMU
• reg_pmcr : ArmISA::PMU
• reg_pmcr_conf : ArmISA::PMU
• reg_pmcr_wr_mask : ArmISA::PMU
• reg_pminten : ArmISA::PMU
• reg_pmovsr : ArmISA::PMU
• reg_pmselr : ArmISA::PMU
• REG_Q : Trace::TarmacBaseRecord
• REG_R : Trace::TarmacBaseRecord
• REG_S : Trace::TarmacBaseRecord
• REG_X : Trace::TarmacBaseRecord
• REG_Z : Trace::TarmacBaseRecord
• regBE : TypedRegisterTest
• regBusy() : RegisterFile
• regCache : MipsISA::RemoteGDB , PowerISA::RemoteGDB , RiscvISA::RemoteGDB
• regCache32 : ArmISA::RemoteGDB , SparcISA::RemoteGDB , X86ISA::RemoteGDB
• regCache64 : ArmISA::RemoteGDB , SparcISA::RemoteGDB , X86ISA::RemoteGDB
• regCachePtr : BaseRemoteGDB
• regClass : RegId , Trace::TarmacTracerRecord::TraceRegEntry
• regClassStrings : RegId
• regControllerCapabilities : UFSHostDevice
• regControllerDEVID : UFSHostDevice
• regControllerEnable : UFSHostDevice
• regControllerPRODID : UFSHostDevice
• regControllerStatus : UFSHostDevice
• regData32() : Sinic::Device
• regData64() : Sinic::Device
• regData8() : Sinic::Device
• regDep : TraceCPU::ElasticDataGen::GraphNode
• RegDepList : TraceCPU::ElasticDataGen::GraphNode
• regdListMap : HWScheduler
• regdQList : HSAPacketProcessor
• RegElement : Trace::TarmacBaseRecord::RegEntry
• regenerateAddr() : BaseIndexingPolicy , SetAssociative , SkewedAssociative
• regenerateBlkAddr() : BaseCache , BaseSetAssoc , BaseTags , FALRU , SectorTags
• RegEntry() : Trace::TarmacBaseRecord::RegEntry
• regEtraceListeners() : ElasticTrace
• regEtraceListenersEvent : ElasticTrace
• regEventStreamId : Iris::ThreadContext
• regFile : FullO3CPU< Impl > , ScalarRegisterFile , UnifiedFreeList , UnifiedRenameMap , VectorRegisterFile
• RegId() : RegId
• RegIdArrayPtr : StaticInst
• regIdx() : Gcn3ISA::ScalarOperand< DataType, Const, NumDwords > , RegId , RegisterFile::RegisterEvent
• RegImmImmOp() : RegImmImmOp
• RegImmOp() : RegImmOp
• RegImmRegOp() : RegImmRegOp
• RegImmRegShiftOp() : RegImmRegShiftOp
• RegIndexVector : ArmKvmCPU , BaseArmKvmCPU
• regInterfaceCallback() : SerialDevice
• regInterruptEnable : UFSHostDevice
• regInterruptStatus : UFSHostDevice
• regionSize() : DynPoolManager , PoolManager , SimplePoolManager
• Register() : RegisterBank< BankByteOrder >::Register< Data, RegByteOrder > , Uart8250 , X86ISA::I8237
• Register16 : RegisterBank< BankByteOrder >
• Register16BE : RegisterBank< BankByteOrder >
• Register16LE : RegisterBank< BankByteOrder >
• Register32 : Clint , Plic , RegisterBank< BankByteOrder >
• Register32BE : RegisterBank< BankByteOrder >
• Register32LE : RegisterBank< BankByteOrder >
• Register64 : RegisterBank< BankByteOrder >
• Register64BE : RegisterBank< BankByteOrder >
• Register64LE : RegisterBank< BankByteOrder >
• Register8 : RegisterBank< BankByteOrder > , Uart8250
• Register8BE : RegisterBank< BankByteOrder >
• Register8LE : RegisterBank< BankByteOrder >
• register_b_transport() : tlm_utils::multi_passthrough_target_socket< MODULE, BUSWIDTH, TYPES, N, POL > , tlm_utils::passthrough_target_socket_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::passthrough_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::simple_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >
• register_extension() : tlm::tlm_extension_base
• register_get_direct_mem_ptr() : tlm_utils::multi_passthrough_target_socket< MODULE, BUSWIDTH, TYPES, N, POL > , tlm_utils::passthrough_target_socket_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::passthrough_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::simple_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >
• register_id() : sc_core::sc_report
• register_invalidate_direct_mem_ptr() : tlm_utils::multi_passthrough_initiator_socket< MODULE, BUSWIDTH, TYPES, N, POL > , tlm_utils::simple_initiator_socket_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::simple_initiator_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >
• register_nb_transport_bw() : tlm_utils::multi_passthrough_initiator_socket< MODULE, BUSWIDTH, TYPES, N, POL > , tlm_utils::simple_initiator_socket_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::simple_initiator_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >
• register_nb_transport_fw() : tlm_utils::multi_passthrough_target_socket< MODULE, BUSWIDTH, TYPES, N, POL > , tlm_utils::passthrough_target_socket_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::passthrough_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::simple_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >
• register_port() : sc_core::sc_fifo< T > , sc_core::sc_interface , sc_core::sc_signal< sc_dt::sc_bigint< W > > , sc_core::sc_signal< sc_dt::sc_biguint< W > > , sc_core::sc_signal< sc_dt::sc_int< W > > , sc_core::sc_signal< sc_dt::sc_uint< W > > , sc_core::sc_signal_resolved , sc_core::sc_signal_rv< W > , sc_gem5::ScSignalBaseT< T, WRITER_POLICY > , tlm_utils::callback_binder_fw< TYPES >
• register_private_extension() : tlm_utils::ispex_base
• register_transport_dbg() : tlm_utils::multi_passthrough_target_socket< MODULE, BUSWIDTH, TYPES, N, POL > , tlm_utils::passthrough_target_socket_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::passthrough_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::simple_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >
• registerAbstractController() : RubySystem
• RegisterBank() : RegisterBank< BankByteOrder >
• RegisterBankTest() : RegisterBankTest
• RegisterBase() : RegisterBank< BankByteOrder >::RegisterBase
• RegisterBuf() : RegisterBank< BankByteOrder >::RegisterBuf
• RegisterBufTest() : RegisterBufTest
• registerCU() : Shader
• registerDequeueCallback() : MessageBuffer
• registerDevice() : PciHost , RealViewCtrl
• registerDrainable() : DrainManager
• registered : EmbeddedPyBind
• registerEvent() : ArmISA::PMU
• RegisterEvent() : RegisterFile::RegisterEvent
• RegisterFile() : RegisterFile
• RegisterFileStats() : RegisterFile::RegisterFileStats
• registerHandler() : ExternalMaster , ExternalSlave
• registerKickCallback() : VirtIODeviceBase
• RegisterLBuf() : RegisterBank< BankByteOrder >::RegisterLBuf< BufBytes >
• RegisterLBufTest() : RegisterLBufTest
• registerListener() : SystemCounter
• registerMachineID() : RubySystem
• registerManager : ComputeUnit
• RegisterManager() : RegisterManager
• registerNetwork() : RubySystem
• registerNewQueue() : HWScheduler
• RegisterOffset : HDLcd
• registerPowerProducer() : SubSystem
• registerQueue() : VirtIODeviceBase
• RegisterRao() : RegisterBank< BankByteOrder >::RegisterRao
• RegisterRaoTest() : RegisterRaoTest
• RegisterRaz() : RegisterBank< BankByteOrder >::RegisterRaz
• RegisterRazTest() : RegisterRazTest
• registerReads : RegisterFile::RegisterFileStats
• registerRequestorIDs() : RubySystem
• RegisterRoFill() : RegisterBank< BankByteOrder >::RegisterRoFill
• registers : Clint
• Registers : EnergyCtrl
• registers : Plic , Uart8250
• Registers() : Uart8250::Registers
• registerSrcClockDom() : VoltageDomain
• registerThreadContext() : System
• registerThreadContexts() : BaseCPU
• registerTraceFile() : sc_gem5::Scheduler
• registerWithClockDomain() : ClockDomain
• registerWrites : RegisterFile::RegisterFileStats
• regm : X86ISA::EmulEnv
• RegMiscRegImmOp() : RegMiscRegImmOp
• RegMiscRegImmOp64() : RegMiscRegImmOp64
• regMode : ArmISA::SrsOp
• regName : SparcISA::PrivReg , SparcISA::WrPrivImm , Trace::TarmacTracerRecord::TraceRegEntry
• RegNone() : RegNone
• RegOp() : RegOp , X86ISA::RegOp
• RegOpBase() : X86ISA::RegOpBase
• RegOpImm() : X86ISA::RegOpImm
• regPort() : sc_gem5::Port
• regPortNeeded : sc_gem5::Port
• regProbeListeners() : ArmISA::PMU , BaseMemProbe , Compressor::FrequentValues , ElasticTrace , Prefetcher::Base , SimObject , SimpleTrace , SimPoint
• regProbePoints() : ArmISA::TLB , AtomicSimpleCPU , BaseCache , BaseCPU , BPredUnit , CommMonitor , DefaultCommit< Impl > , DefaultFetch< Impl > , DefaultIEW< Impl > , DefaultRename< Impl > , FullO3CPU< Impl > , PowerModel , SimObject
• RegPtr : Trace::TarmacTracer , Trace::TarmacTracerRecord
• regQueue : Trace::TarmacTracer
• regRecord : Trace::TarmacParserRecord
• RegRegImmImmOp() : RegRegImmImmOp
• RegRegImmImmOp64() : RegRegImmImmOp64
• RegRegImmOp() : RegRegImmOp
• RegRegOp() : RegRegOp
• RegRegRegImmOp() : RegRegRegImmOp
• RegRegRegImmOp64() : RegRegRegImmOp64
• RegRegRegOp() : RegRegRegOp
• RegRegRegRegOp() : RegRegRegRegOp
• regRel : Trace::TarmacTracerRecord::TraceRegEntry
• regs : BaseDynInst< Impl >
• Regs() : BaseDynInst< Impl >::Regs
• regs : CopyEngine , FVPBasePwrCtrl , IGbE , NSGigE , Sinic::Device , SMMUv3 , X86ISA::Cmos , X86ISA::I8237 , X86ISA::Interrupts
• regScoreboard : InstructionQueue< Impl >
• regScoreBoard : Scoreboard
• regSel : X86ISA::I82094AA
• RegSize : RegisterBufTest , RegisterLBufTest , TypedRegisterTest
• regsMap : SMMUv3
• RegsPerWindow : SparcISA::ISA
• regsReady : MemDepUnit< MemDepPred, Impl >::MemDepEntry , MemDepUnit< MemDepPred, Impl >
• regsReset() : NSGigE
• regStats() : AbstractController , AbstractMemory::MemStats , AddressProfiler , BaseCache::CacheStats , BaseCPU , BaseTags::BaseTagStats , BaseXBar , CheckerThreadContext< TC > , CoherentXBar , Compressor::Base::BaseStats , Compressor::BaseDictionaryCompressor::DictionaryStats , Compressor::Multi::MultiStats , DRAMInterface::DRAMStats , DRAMInterface::RankStats , GarnetNetwork , HTMSequencer , Iris::ThreadContext , MathExprPowerModel , MemCtrl::CtrlStats , MinorCPU , NVMInterface::NVMStats , PowerDomain::PowerDomainStats , PowerState::PowerStateStats , Profiler , QoS::MemCtrl::MemCtrlStats , QoS::Policy , Router , RubySystem , sc_gem5::Kernel , SectorTags::SectorTagsStats , SimpleNetwork , SnoopFilter , Stats::Group , Switch , System , ThreadContext , Throttle , Ticked , TickedObject
• regStatsFromParent() : BaseCache::CacheCmdStats
• regtoh() : RegisterBank< BankByteOrder >::Register< Data, RegByteOrder >
• RegType : Trace::TarmacBaseRecord
• regUFSVersion : UFSHostDevice
• regUICCommand : UFSHostDevice
• regUICCommandArg1 : UFSHostDevice
• regUICCommandArg2 : UFSHostDevice
• regUICCommandArg3 : UFSHostDevice
• regUICErrorCodeDataLinkLayer : UFSHostDevice
• regUICErrorCodeDME : UFSHostDevice
• regUICErrorCodeNetworkLayer : UFSHostDevice
• regUICErrorCodePHYAdapterLayer : UFSHostDevice
• regUICErrorCodeTransportLayer : UFSHostDevice
• RegularProbe() : ArmISA::PMU::RegularEvent::RegularProbe
• regUTPTaskREQDoorbell : UFSHostDevice
• regUTPTaskREQListBaseH : UFSHostDevice
• regUTPTaskREQListBaseL : UFSHostDevice
• regUTPTaskREQListClear : UFSHostDevice
• regUTPTaskREQListRunStop : UFSHostDevice
• regUTPTransferREQDoorbell : UFSHostDevice
• regUTPTransferREQINTAGGControl : UFSHostDevice
• regUTPTransferREQListBaseH : UFSHostDevice
• regUTPTransferREQListBaseL : UFSHostDevice
• regUTPTransferREQListClear : UFSHostDevice
• regUTPTransferREQListRunStop : UFSHostDevice
• regVal : X86ISA::ISA
• regValid : Trace::TarmacTracerRecord::TraceRegEntry
• regWidth : Trace::TarmacTracerRecordV8::TraceRegEntryV8
• reinit() : ItsProcess , SMMUProcess
• reinsertToSchList() : ScheduleStage
• relativeTick : BasePixelPump::PixelEvent
• release() : Event , Linux::utsname , LSQ< Impl >::LSQRequest , OperatingSystem::utsname , Process
• RELEASE : Request
• release() : sc_core::sc_mempool , SimpleATInitiator1::SimplePool , SimpleATInitiator2::SimplePool , SimpleMemory , Solaris::utsname , tlm::tlm_generic_payload , TraceCPU::ElasticDataGen::HardwareResource , WFBarrier
• release_carrier() : tlm_utils::instance_specific_extension_accessor
• release_extension() : tlm::tlm_generic_payload
• release_fence_scope : hsa_packet_header_s
• release_fn : tlm_utils::instance_specific_extension_container
• releaseBarrier() : ComputeUnit , Wavefront
• releaseDate : X86ISA::SMBios::BiosInformation
• releaseEvent : BaseXBar::Layer< SrcType, DstType > , SimpleMemory
• releaseImpl() : Event , PyEvent , sc_gem5::Scheduler::TimeSlot
• releaseLayer() : BaseXBar::Layer< SrcType, DstType >
• releaseLoc() : AddressManager::AtomicStruct
• releaseLocation() : AddressManager
• releaseSpace() : LdsState
• releaseStoreBuffer() : TraceCPU::ElasticDataGen::HardwareResource
• releaseTimeSlot() : sc_gem5::Scheduler
• releaseWFsFromBarrier() : ComputeUnit
• reloadRegMap() : SparcISA::ISA
• relocatable() : Loader::ElfObject , Loader::ObjectFile
• relocate : Loader::ElfObject , OutputFile< StreamType > , OutputStream
• remaining : sc_core::sc_join
• remainingReg : X86ISA::I8237::Channel
• remainingSpace() : Minor::Queue< ElemType, ReportTraits, BubbleTraits >
• remap() : EmulationPageTable , FlashDevice , MultiLevelPageTable< EntryTypes > , VMA
• remapAddr() : AddrMapper , RangeAddrMapper
• remappedRanges : RangeAddrMapper
• remapRegion() : MemState
• RemoteGDB() : ArmISA::RemoteGDB , MipsISA::RemoteGDB , PowerISA::RemoteGDB , RiscvISA::RemoteGDB , SparcISA::RemoteGDB , X86ISA::RemoteGDB
• remoteIRR : X86ISA::I82094AA , X86ISA::Interrupts
• remove : BreakPCEvent , CheckerThreadContext< TC > , DependencyGraph< DynInstPtr > , EventQueue , Iris::ThreadContext , NetDest , O3ThreadContext< Impl > , OutputDirectory , PacketFifo , PCEvent , PCEventQueue , PCEventScope , PollQueue , RiscvISA::TLB , sc_core::sc_attr_cltn , sc_dt::scfx_string , Set , SimpleThread , System , Trie< Key, Value >
• remove_all() : sc_core::sc_attr_cltn
• remove_all_attributes() : sc_core::sc_object , sc_gem5::Object
• remove_attribute() : sc_core::sc_object , sc_gem5::Object
• remove_it() : sc_dt::scfx_mant_ref
• remove_traces() : sc_core::sc_in< sc_dt::sc_bigint< W > > , sc_core::sc_in< sc_dt::sc_biguint< W > > , sc_core::sc_in< sc_dt::sc_int< W > > , sc_core::sc_in< sc_dt::sc_uint< W > > , sc_core::sc_inout< sc_dt::sc_bigint< W > > , sc_core::sc_inout< sc_dt::sc_biguint< W > > , sc_core::sc_inout< sc_dt::sc_int< W > > , sc_core::sc_inout< sc_dt::sc_uint< W > >
• removeDepOnInst() : TraceCPU::ElasticDataGen::GraphNode
• removeEntryFromSlot() : TBEStorage
• removeFromHistory() : DefaultRename< Impl >
• removeFrontInst() : FullO3CPU< Impl >
• removeHardBreak() : BaseRemoteGDB
• removeInLSQ() : BaseDynInst< Impl >
• removeInstsNotInROB() : FullO3CPU< Impl >
• removeInstsThisCycle : FullO3CPU< Impl >
• removeInstsUntil() : FullO3CPU< Impl >
• removeIntlvBits() : AddrRange
• removeItem() : Event
• removeList : FullO3CPU< Impl >
• removeListener() : ProbeManager , ProbePoint , ProbePointArg< Arg >
• removeNetDest() : NetDest
• removeQCntxt() : HWScheduler
• removeRegDep() : TraceCPU::ElasticDataGen::GraphNode
• removeRegDepMapEntry() : ElasticTrace
• removeRobDep() : TraceCPU::ElasticDataGen::GraphNode
• removeSet() : Set
• removeSoftBreak() : BaseRemoteGDB
• removeThread() : FullO3CPU< Impl >
• rename() : CxxConfigManager , DefaultDecode< Impl >::Stalls , DefaultRename< Impl > , FullO3CPU< Impl >
• Rename : SimpleCPUPolicy< Impl >
• rename() : SimpleRenameMap , UnifiedRenameMap
• renameBlock : TimeBufStruct< Impl >
• renamedDestIdx() : BaseDynInst< Impl >::Regs
• renameDestReg() : BaseDynInst< Impl >
• renameDestRegs() : DefaultRename< Impl >
• renamedInsts : DefaultRename< Impl >::RenameStats
• renamedOperands : DefaultRename< Impl >::RenameStats
• renamedSrcIdx() : BaseDynInst< Impl >::Regs
• RenameHistory() : DefaultRename< Impl >::RenameHistory
• RenameIdx : FullO3CPU< Impl >
• RenameInfo : SimpleRenameMap
• renameInfo : TimeBufStruct< Impl >
• RenameInfo : UnifiedRenameMap
• renameInsts() : DefaultRename< Impl >
• RenameMap : DefaultCommit< Impl >
• renameMap : DefaultCommit< Impl >
• RenameMap : DefaultIEW< Impl > , DefaultRename< Impl >
• renameMap : DefaultRename< Impl > , FullO3CPU< Impl >
• RenameMap : SimpleCPUPolicy< Impl >
• renameQueue : DefaultCommit< Impl > , DefaultIEW< Impl > , DefaultRename< Impl > , FullO3CPU< Impl >
• renameSrcReg() : BaseDynInst< Impl >
• renameSrcRegs() : DefaultRename< Impl >
• RenameStats() : DefaultRename< Impl >::RenameStats
• RenameStatus : DefaultRename< Impl >
• renameStatus : DefaultRename< Impl >
• RenameStruct : DefaultCommit< Impl > , DefaultIEW< Impl > , DefaultRename< Impl > , FullO3CPU< Impl > , SimpleCPUPolicy< Impl >
• renameToDecodeDelay : DefaultDecode< Impl >
• renameToFetchDelay : DefaultFetch< Impl >
• renameToIEWDelay : DefaultIEW< Impl >
• renameToROBDelay : DefaultCommit< Impl >
• renameUnblock : TimeBufStruct< Impl >
• renameWidth : DefaultCommit< Impl > , DefaultRename< Impl >
• Renaming() : CxxConfigManager::Renaming
• renamings : CxxConfigManager
• renderFrame() : BasePixelPump
• renderLine() : BasePixelPump
• renderPixels() : BasePixelPump
• REP_BYTES : Compressor::FPC
• RepBytes() : Compressor::FPC::RepBytes
• repeat : GlobalSimLoopExitEvent , GlobalSyncEvent , LocalSimLoopExitEvent , Stats::StatEvent
• RepeatedQwords() : Compressor::RepeatedQwords
• RepeatedValuePattern() : Compressor::DictionaryCompressor< T >::RepeatedValuePattern< RepT >
• repeatEvent() : CPUProgressEvent
• replace() : Flags< T > , System::Threads
• ReplaceableEntry() : ReplaceableEntry
• replaceExpansions : BaseCache
• replaceHead() : EventQueue
• replacement_data : CacheMemory
• replacementData : ReplaceableEntry
• replacementPolicy : AssociativeSet< Entry > , BaseSetAssoc , Prefetcher::Stride::PCTableInfo , SectorTags , SMMUv3BaseCache
• replacements : BaseCache::CacheStats
• replaceThreadContext() : BaseRemoteGDB , System
• replaceUpgrades() : MSHR::TargetList
• replay() : MemDepUnit< MemDepPred, Impl >
• replayMemInst() : DefaultIEW< Impl > , InstructionQueue< Impl >
• ReplData : CacheMemory
• replicate : ArmISA::MicroNeonMixLaneOp64 , ArmISA::VldSingleOp64 , ArmISA::VstSingleOp64
• replicatePage() : Process
• report() : sc_core::sc_report_handler
• report_error() : sc_core::sc_port_base
• reportData() : Minor::BranchData , Minor::Fetch1::FetchRequest , Minor::ForwardInstData , Minor::ForwardLineData , Minor::LSQ::LSQRequest , Minor::MinorDynInst , Minor::QueuedInst , Minor::ReportIF , Minor::ReportTraitsAdaptor< ElemType > , Minor::ReportTraitsPtrAdaptor< PtrType >
• reportEmpty() : sc_core::sc_vector_base
• reportLeft : Minor::MinorBuffer< ElemType, ReportTraits, BubbleTraits >
• ReportMsgInfo() : sc_gem5::ReportMsgInfo
• reportRight : Minor::MinorBuffer< ElemType, ReportTraits, BubbleTraits >
• ReportSevInfo() : sc_gem5::ReportSevInfo
• reportUnbound() : Port
• repr : Trace::TarmacParserRecord::ParserRegEntry
• req : ArmISA::Stage2LookUp , ArmISA::Stage2MMU::Stage2Translation , ArmISA::TableWalker::WalkerState , DefaultFetch< Impl >::FinishTranslationEvent , LSQUnit< Impl >::LSQEntry , Packet , RiscvISA::Walker::WalkerState , X86ISA::Walker::WalkerState
• req_name : RequestorInfo
• req_rsp : tlm::tlm_transport_channel< REQ, RSP, REQ_CHANNEL, RSP_CHANNEL >
• req_tick_latency : ComputeUnit
• reqCnt : X86ISA::GpuTLB::TranslationState
• reqFlags : DmaReadFifo , ElasticTrace::TraceInfo
• reqIPI() : MaltaCChip
• ReqLayer() : BaseXBar::ReqLayer
• reqLayers : CoherentXBar , NoncoherentXBar
• reqLookupResult : SnoopFilter
• ReqLookupResult() : SnoopFilter::ReqLookupResult
• ReqMade : BaseDynInst< Impl >
• ReqPacketQueue() : ReqPacketQueue
• reqPos : UFSHostDevice::SCSIResumeInfo , UFSHostDevice::transferDoneInfo
• reqQueue : MemDelay , QueuedRequestPort , RubyPort::MemRequestPort , RubyPort::PioRequestPort , SMMUATSMemoryPort , X86ISA::IntRequestPort< Device >
• reqQueueFull() : Bridge::BridgeRequestPort , SerialLink::SerialLinkRequestPort
• reqQueueLimit : Bridge::BridgeRequestPort , SerialLink::SerialLinkRequestPort
• reqToVerify : BaseDynInst< Impl >
• ReqType : DistHeaderPkt , DistIface
• request() : LSQ< Impl >::LSQRequest , LSQ< Impl >::LSQSenderState , LSQUnit< Impl >::LSQEntry , Minor::Fetch1::FetchRequest , Minor::LSQ::LSQRequest
• Request() : Request
• request : SMMUTranslationProcess
• request_fifo : tlm::tlm_req_rsp_channel< REQ, RSP, REQ_CHANNEL, RSP_CHANNEL >
• request_out_datain : UFSHostDevice
• request_ports : RubyPort
• request_update() : sc_core::sc_prim_channel
• requestCkpt() : DistIface::Sync , DistIface::SyncNode , DistIface::SyncSwitch
• requestCompleted : PrefetchEntry
• requestCount : AddressManager::AtomicStruct
• REQUESTED : ArmISA::TableWalker
• requested : SnoopFilter::SnoopItem
• requestEventScheduled() : MemCtrl
• requestExit() : DistIface::Sync , DistIface::SyncNode , DistIface::SyncSwitch
• requestFbUpdate() : VncServer
• requestHandler() : UFSHostDevice
• RequestIn : UFSHostDevice::SCSIResumeInfo
• requestInterrupt() : X86ISA::I8259 , X86ISA::Interrupts
• requestIssued : PrefetchEntry
• RequestIssuing : Minor::Fetch1::FetchRequest , Minor::LSQ::LSQRequest
• requestLatency : QoS::MemSinkCtrl
• RequestNeedsRetry : Minor::LSQ::LSQRequest
• RequestorHistory : QoS::PropFairPolicy
• requestorId : ArmISA::Stage2MMU , ArmISA::TableWalker , BaseDynInst< Impl > , BaseGen , BaseTrafficGen , CheckerCPU , ComputeUnit , DirectedGenerator , DmaPort , GarnetSyntheticTraffic , Gicv3Its , MemPacket , MemTest , Packet , Prefetcher::Base::PrefetchInfo , Prefetcher::Base , ProtocolTester , Request , RiscvISA::Walker , RubyTester , SMMUv3 , TraceCPU::ElasticDataGen , TraceCPU::FixedRetryGen , X86ISA::Walker
• requestOrigin : ArmISA::TableWalker::TableWalkerStats
• RequestorInfo() : RequestorInfo
• requestorReadAccesses : MemCtrl::CtrlStats
• requestorReadAvgLat : MemCtrl::CtrlStats
• requestorReadBytes : MemCtrl::CtrlStats
• requestorReadRate : MemCtrl::CtrlStats
• requestorReadTotalLat : MemCtrl::CtrlStats
• requestors : QoS::MemCtrl , System
• requestorToNetwork : RubySystem
• requestorWriteAccesses : MemCtrl::CtrlStats
• requestorWriteAvgLat : MemCtrl::CtrlStats
• requestorWriteBytes : MemCtrl::CtrlStats
• requestorWriteRate : MemCtrl::CtrlStats
• requestorWriteTotalLat : MemCtrl::CtrlStats
• requestOut : UFSHostDevice::transferDoneInfo
• requestPort : MemDelay
• RequestPort() : MemDelay::RequestPort , RequestPort , ResponsePort
• requestPort : SMMUv3
• requestPortSem : SMMUv3
• requestPortWidth : SMMUv3
• RequestQueue() : VirtIOBlock::RequestQueue
• requestReg : X86ISA::I8237
• requests : Minor::Fetch1 , Minor::LSQ
• requestSize() : DmaReadFifo::DmaDoneEvent
• requestStopSync() : DistIface::Sync , DistIface::SyncNode , DistIface::SyncSwitch
• RequestTable : DMASequencer
• RequestThread() : SimpleBusAT< NR_OF_INITIATORS, NR_OF_TARGETS >
• requestTimes : QoS::MemCtrl
• RequestType : VirtIOBlock
• requestUpdate() : sc_gem5::Channel , sc_gem5::Scheduler
• requeue() : FutexMap
• res : Minor::LSQ::LSQRequest , WholeTranslationState
• res0() : ArmISA::ISA::MiscRegLUTEntry , ArmISA::ISA::MiscRegLUTEntryInitializer , Gicv3CPUInterface
• res0_0 : Gicv3CPUInterface
• res0_1 : Gicv3CPUInterface , Gicv3Distributor
• res0_2 : Gicv3CPUInterface , Gicv3Distributor
• res0_3 : Gicv3CPUInterface
• res1() : ArmISA::ISA::MiscRegLUTEntry , ArmISA::ISA::MiscRegLUTEntryInitializer , Gicv3CPUInterface , Gicv3Redistributor , Linux::pcb_struct
• res2 : Linux::pcb_struct
• res_error_head : SparcISA::ISA
• res_error_tail : SparcISA::ISA
• reschedule() : BaseGlobalEvent , EventManager , EventQueue , MemDepUnit< MemDepPred, Impl >
• rescheduledLoads : LSQUnit< Impl >::LSQUnitStats
• rescheduleMemInst() : DefaultIEW< Impl > , InstructionQueue< Impl >
• reserve() : BankedArray , Minor::InputBuffer< ElemType, ReportTraits, BubbleTraits > , Minor::Queue< ElemType, ReportTraits, BubbleTraits > , Minor::Reservable , PacketFifo
• reserveBuf() : FetchUnit::FetchBufDesc
• reserved : AMDKernelCode
• Reserved : ArmISA::TableWalker::L1Descriptor
• reserved : Clint::ClintRegisters , CpuLocalTimer::Timer , FXSave
• RESERVED : Gcn3ISA::StatusReg
• reserved : hsa_packet_header_s
• Reserved : Iob
• reserved : Net::ip6_opt_routing_type2 , PacketFifo , PciIoBar , PciMemBar , Plic::PlicRegisters , PXCAP , TBEStorage , UFSHostDevice::UFSHCDSGEntry , UFSHostDevice::UTPUPIURSP , UFSHostDevice::UTPUPIUTaskReq , VirtIOBlock::BlkRequest , X86ISA::PageFault
• reserved0 : _hsa_agent_dispatch_packet_s , _hsa_barrier_and_packet_s , _hsa_barrier_or_packet_s , _hsa_dispatch_packet_s
• Reserved0 : EventBase
• reserved0 : hsa_agent_dispatch_packet_s , hsa_barrier_and_packet_s , hsa_barrier_or_packet_s , hsa_kernel_dispatch_packet_s , hsa_queue_s , IdeController::Channel::BMIRegs , SCMI::Message
• reserved1 : _amd_queue_s , _hsa_barrier_and_packet_s , _hsa_barrier_or_packet_s , _hsa_dispatch_packet_s , _hsa_queue_s , amd_signal_s , BmpWriter::FileHeader , CopyEngineReg::DmaDesc , hsa_agent_dispatch_packet_s , hsa_barrier_and_packet_s , hsa_barrier_or_packet_s , hsa_kernel_dispatch_packet_s , hsa_queue_s , IdeController::Channel::BMIRegs , SCMI::Message
• reserved2 : _amd_queue_s , _hsa_agent_dispatch_packet_s , _hsa_barrier_and_packet_s , _hsa_barrier_or_packet_s , amd_signal_s , BmpWriter::FileHeader , CopyEngineReg::DmaDesc , hsa_agent_dispatch_packet_s , hsa_barrier_and_packet_s , hsa_barrier_or_packet_s , hsa_kernel_dispatch_packet_s
• reserved3 : _amd_queue_s , amd_signal_s
• reserved4 : _amd_queue_s
• RESERVED_1 : Gcn3ISA::StatusReg
• reserved_15_12 : HDLcd
• reserved_2_0 : HDLcd
• reserved_30_5 : HDLcd
• reserved_31_1 : HDLcd
• reserved_31_12 : HDLcd
• reserved_31_24 : HDLcd
• reserved_31_5 : HDLcd
• reserved_7_5 : HDLcd
• reserved_sgpr_count : AMDKernelCode
• reserved_sgpr_first : AMDKernelCode
• reserved_vgpr_count : AMDKernelCode
• reserved_vgpr_first : AMDKernelCode
• reservedBuf() : FetchUnit::FetchBufDesc
• ReservedGrain : ArmISA::TableWalker
• reservedLines() : FetchUnit::FetchBufDesc
• reservedPCs : FetchUnit::FetchBufDesc
• reservedScalarRegs : Wavefront
• reservedSpace() : Minor::Queue< ElemType, ReportTraits, BubbleTraits >
• reservedSpaceRecord : DynPoolManager
• reservedVectorRegs : Wavefront
• reserveGmResource() : Wavefront
• reserveLmResource() : Wavefront
• reserveResources() : ScheduleStage , Wavefront
• reserveSpace() : LdsState
• reset() : ActivityRecorder , ArmISA::Decoder , ArmISA::HTMCheckpoint , ArmISA::ISA::MiscRegLUTEntry , BaseHTMCheckpoint , DefaultBTB , DependencyGraph< DynInstPtr > , DmaReadFifo::DmaDoneEvent , GenericSatCounter< T > , Gicv3 , IdeController::Channel::BMIRegs , IdeDisk , IGbE::DescCache< T >
• Reset : Iob
• reset() : MemChecker , MipsISA::Decoder , MockInfo , NoMaliGpu , PipeStageIFace , PowerISA::Decoder , ProtoInputStream , ReplacementPolicy::Base , ReplacementPolicy::BIP , ReplacementPolicy::BRRIP , ReplacementPolicy::FIFO , ReplacementPolicy::LFU , ReplacementPolicy::LRU , ReplacementPolicy::MRU , ReplacementPolicy::Random , ReplacementPolicy::SecondChance , ReplacementPolicy::TreePLRU , ReplacementPolicy::WeightedLRU , ReturnAddrStack , RiscvISA::Decoder
• Reset() : RiscvISA::Reset
• reset() : sc_core::sc_process_handle , sc_core::sc_simcontext
• Reset() : sc_core::sc_spawn_options::Reset< T >
• reset() : sc_core::sc_vpool< T > , sc_gem5::Process
• Reset() : sc_gem5::Reset
• reset() : ScheduleToExecute , ScoreboardCheckToSchedule , Sinic::Device , SparcISA::Decoder , Stats::AvgSampleStor , Stats::AvgStor , Stats::DataWrapVec< Derived, InfoProxyType > , Stats::DistBase< Derived, Stor > , Stats::DistProxy< Stat > , Stats::DistStor , Stats::Formula , Stats::HistStor , Stats::Info , Stats::InfoAccess , Stats::InfoProxy< Stat, Base > , Stats::ProxyInfo , Stats::SampleStor , Stats::ScalarBase< Derived, Stor > , Stats::SparseHistBase< Derived, Stor > , Stats::SparseHistStor , Stats::StatEvent , Stats::StatStor , Stats::ValueBase< Derived > , Stats::Vector2dBase< Derived, Stor > , test , testbench , tlm::tlm_generic_payload , tlm_utils::peq_with_cb_and_phase< OWNER, TYPES >::delta_list , tlm_utils::time_ordered_list< PAYLOAD > , tlm_utils::tlm_quantumkeeper , TraceCPU::ElasticDataGen::InputStream , TraceCPU::FixedRetryGen::InputStream , TraceGen::InputStream , UFSHostDevice::SCSIReply , VecPredRegContainer< NumBits, Packed > , VecPredRegT< VecElem, NumElems, Packed, Const > , VirtIODeviceBase , VirtQueue , VirtQueue::VirtRing< T > , WFBarrier , WriteAllocator , X86ISA::Decoder , X86ISA::ExtMachInst , X86ISA::LongModePTE
• reset_event() : sc_core::sc_process_handle
• reset_loop() : test
• reset_signal_is() : sc_core::sc_module , sc_core::sc_spawn_options
• resetAddr() : ArmSystem
• resetBarrier() : ComputeUnit
• resetClock() : Clocked
• ResetCtl : RealViewCtrl
• resetDelay() : WriteAllocator
• resetDictionary() : Compressor::BaseDelta< BaseType, DeltaSizeBits > , Compressor::DictionaryCompressor< T >
• resetEnabled : Sp805
• resetEntireStatusVector() : GPUDynInst
• resetEntries() : DefaultIEW< Impl > , InstructionQueue< Impl > , ROB< Impl >
• resetEvent() : sc_gem5::Process
• resetEventCounts() : ArmISA::PMU
• resetFlags() : MSHR::TargetList
• resetHppi() : Gicv3CPUInterface
• resetHtmStartsStops() : DefaultCommit< Impl > , LSQ< Impl > , LSQUnit< Impl >
• resetLastStopped() : Ticked
• resetOwner() : MemState
• resetRegion() : DynPoolManager , PoolManager
• resetRegisterPool() : ComputeUnit
• resets : sc_gem5::Port , sc_gem5::Process
• resetScores() : Prefetcher::BOP
• resetSigVals() : HSAPacketProcessor::SignalState
• resetStage() : DefaultDecode< Impl > , DefaultFetch< Impl > , DefaultRename< Impl >
• resetState() : InstructionQueue< Impl > , LSQUnit< Impl > , ROB< Impl >
• ResetState : X86ISA::Decoder
• resetStats() : AbstractController , BaseSimpleCPU , CrossbarSwitch , DRAMInterface::DRAMStats , DRAMInterface::Rank , DRAMInterface::RankStats , DRAMsim3 , DRAMsim3Wrapper , GarnetNetwork , GPUCoalescer , InputUnit , NetworkLink , Root::RootStats , Router , RubySystem , Sequencer , Sinic::Device , Stats::Group , Switch , SwitchAllocator
• resetStatusVector() : GPUDynInst
• resetUctr() : MPP_TAGE , TAGE_SC_L_TAGE_8KB , TAGEBase
• resetValue : ArmISA::PMU::CounterState
• resetVect() : RiscvISA::FsWorkload
• residualTransferCount : UFSHostDevice::UTPUPIURSP
• resistors : ThermalModel
• resize() : DependencyGraph< DynInstPtr > , FrameBuffer , Minor::ForwardInstData , NetDest , sc_dt::scfx_rep , sc_dt::scfx_string , SubBlock , tlm::circular_buffer< T > , tlm_utils::instance_specific_extension_container
• resize_extensions() : tlm::tlm_generic_payload , tlm_utils::instance_specific_extensions_per_accessor
• resize_to() : sc_dt::scfx_mant , sc_dt::scfx_rep
• resizeRegFiles() : Wavefront
• resolution() : BaseKvmTimer , PS2Mouse
• resolve() : OutputDirectory
• resolveFile() : TrafficGen
• resolveFlatSegment() : GPUDynInst
• resolveSimObject() : CxxConfigManager::SimObjectResolver , PybindSimObjectResolver , SimObjectResolver
• resolveStat() : Stats::Group
• ResourceIds : Iris::ThreadContext
• ResourceMap : Iris::ThreadContext
• resp_tick_latency : ComputeUnit
• RespLayer() : BaseXBar::RespLayer
• respLayers : CoherentXBar , NoncoherentXBar
• RESPONDER_FLAGS : Packet
• RESPONDER_HAD_WRITABLE : Packet
• responderBind() : ResponsePort
• responderHadWritable() : Packet
• responderUnbind() : ResponsePort
• respondEvent() : DRAMInterface , MemCtrl
• respondEventScheduled() : MemCtrl
• respondsTo() : AbstractController
• response : MemCmd::CommandInfo
• RESPONSE_DELAY : SimpleATTarget1 , SimpleATTarget2
• response_fifo : tlm::tlm_req_rsp_channel< REQ, RSP, REQ_CHANNEL, RSP_CHANNEL >
• response_ports : RubyPort
• responseCommand() : MemCmd
• responseEvent : StubSlavePort
• responseInProgress : sc_gem5::TlmToGem5Bridge< BITWIDTH >
• responseLatency : BaseCache , BaseXBar , QoS::MemSinkCtrl
• responseLimit : GarnetSyntheticTraffic
• responsePacket : StubSlavePort
• responsePort : MemDelay
• ResponsePort() : MemDelay::ResponsePort , RequestPort , ResponsePort
• responseQueue : DRAMSim2 , DRAMsim3
• responseStartAddr : UFSHostDevice::transferDoneInfo
• ResponseThread() : SimpleBusAT< NR_OF_INITIATORS, NR_OF_TARGETS >
• responseUPIU : UFSHostDevice::UTPTransferCMDDesc
• responseUPIULength : UFSHostDevice::UTPTransferReqDesc
• responseUPIUOffset : UFSHostDevice::UTPTransferReqDesc
• RespPacketQueue() : RespPacketQueue
• respQueue : MemCtrl , MemDelay , QueuedResponsePort , SMMUATSDevicePort , SMMUDevicePort , TokenResponsePort
• respQueueFull() : Bridge::BridgeResponsePort , SerialLink::SerialLinkResponsePort
• respQueueLimit : Bridge::BridgeResponsePort , SerialLink::SerialLinkResponsePort
• restartClock() : IGbE
• restartCounter() : Sp804::Timer , Sp805
• restartFromBranch : FetchUnit::FetchBufDesc
• restartScheduler() : MemCtrl
• restartStateMachine() : CopyEngine::CopyEngineChannel
• restartTimerCounter() : CpuLocalTimer::Timer
• restartWatchdogCounter() : CpuLocalTimer::Timer
• restore() : ArmISA::HTMCheckpoint , BaseHTMCheckpoint , ReturnAddrStack
• restoreFileOffsets() : FDArray
• restrictAllocation : LoopPredictor
• result : ArmISA::MemoryAtomicPair64 , ArmISA::MemoryDImmEx64 , ArmISA::MemoryEx64 , ArmISA::MemoryExDImm , ArmISA::MemoryExImm , CheckerCPU , InstResult , Stats::AvgStor , Stats::BinaryNode< Op > , Stats::ConstNode< T > , Stats::ConstVectorNode< T > , Stats::Formula , Stats::FormulaInfoProxy< Stat > , Stats::FormulaNode , Stats::FunctorProxy< T, Enabled > , Stats::FunctorProxy< T, typename std::enable_if_t< std::is_constructible< std::function< Result()>, const T & >::value > > , Stats::MethodProxy< T, V > , Stats::Node , Stats::ScalarBase< Derived, Stor > , Stats::ScalarInfo , Stats::ScalarInfoProxy< Stat > , Stats::ScalarProxy< Stat > , Stats::ScalarProxyNode< Stat > , Stats::ScalarStatNode , Stats::StatStor , Stats::SumNode< Op > , Stats::UnaryNode< Op > , Stats::ValueBase< Derived > , Stats::ValueProxy< T > , Stats::VectorBase< Derived, Stor > , Stats::VectorInfo , Stats::VectorInfoProxy< Stat > , Stats::VectorProxy< Stat > , Stats::VectorStatNode
• result2 : ArmISA::MemoryAtomicPair64
• result_type : std::hash< ChannelAddr >
• resultAvailable : TimingExprEvalContext
• resultInt() : sc_gem5::ScMainFiber
• ResultReady : BaseDynInst< Impl >
• results : TimingExprEvalContext
• resultSize() : BaseDynInst< Impl >
• resultStr() : sc_gem5::ScMainFiber
• ResultType : InstResult
• resume() : BasePixelPump::PixelEvent , DrainManager
• Resume : Iob
• resume() : sc_core::sc_process_handle , sc_gem5::Process , sc_gem5::Scheduler , System::Threads::Thread
• resumeEvent : System::Threads::Thread
• resumeFill() : DmaReadFifo
• resumeFillBypass() : DmaReadFifo
• resumeFillTiming() : DmaReadFifo
• resumeRecvTicks() : DistIface::RecvScheduler
• resumeSerialize : DefaultRename< Impl >
• resumeTransaction() : SMMUTranslationProcess
• resumeUnblocking : DefaultRename< Impl >
• resyncMatch() : PL031
• ret : RegisterBankTest::Access
• retAddr : Aapcs32::State
• retChannel : m5::Coroutine< Arg, Ret >::CallerType
• RetChannel : m5::Coroutine< Arg, Ret >
• retData16 : IsaFake
• retData32 : IsaFake
• retData64 : IsaFake
• retData8 : IsaFake
• RetErrno : ArmSemihosting
• retError() : ArmSemihosting
• retireHead() : ROB< Impl >
• retireResponse() : Minor::LSQ::LSQRequest , Minor::LSQ::SingleDataRequest , Minor::LSQ::SpecialDataRequest , Minor::LSQ::SplitDataRequest
• retOK() : ArmSemihosting
• retransmit() : EtherTapBase
• retries : ComputeUnit::DataPort , ComputeUnit::DTLBPort , ComputeUnit::ITLBPort , ComputeUnit::LDSPort , ComputeUnit::ScalarDataPort , ComputeUnit::ScalarDTLBPort , ComputeUnit::SQCPort , TLBCoalescer::MemSidePort , X86ISA::GpuTLB::MemSidePort
• RETRY : BaseXBar::Layer< SrcType, DstType >
• retry : Gicv3Its
• Retry : LSQ< Impl >::LSQRequest
• retry() : PacketQueue , RiscvISA::Walker::WalkerState , SyscallReturn , X86ISA::Walker::WalkerState
• retryFlag : SyscallReturn
• retrying : RiscvISA::Walker::WalkerState , X86ISA::Walker::WalkerState
• retryItem : SnoopFilter::ReqLookupResult
• retryList : RubyPort
• retryMemInsts : InstructionQueue< Impl >
• retryPkt : BaseTrafficGen , DefaultFetch< Impl > , GarnetSyntheticTraffic , LSQUnit< Impl > , MemTest , TraceCPU::ElasticDataGen , TraceCPU::FixedRetryGen
• retryPktTick : BaseTrafficGen
• retryRdReq : MemCtrl , QoS::MemSinkCtrl
• retryReq() : BaseTrafficGen , Bridge::BridgeResponsePort , DRAMSim2 , DRAMsim3 , SerialLink::SerialLinkResponsePort , SimpleMemory
• retryRequest : Minor::LSQ
• retryResp : DRAMSim2 , DRAMsim3 , LdsState , SimpleMemory
• retryRespEvent : TimingSimpleCPU::TimingCPUPort
• retryStalledReq() : Bridge::BridgeResponsePort , SerialLink::SerialLinkResponsePort
• retryTicks : BaseTrafficGen::StatGroup
• retryTid : DefaultFetch< Impl >
• retryWaiting() : BaseXBar::Layer< SrcType, DstType >
• retryWrReq : MemCtrl , QoS::MemSinkCtrl
• return_address : _hsa_agent_dispatch_packet_s , hsa_agent_dispatch_packet_s
• ReturnAddrStack() : ReturnAddrStack
• returnCycle : Minor::Scoreboard
• returnedLoads : ScalarMemPipeline
• returnedStores : ScalarMemPipeline
• returnFromFuncIn() : ArmISA::SkipFunc , SkipFuncBase
• returnInto() : SyscallDesc , SyscallDescABI< ABI >
• returnQueue : LdsState
• returnQueuePush() : LdsState
• returnValue() : SyscallReturn
• retval : SimpleAddressMap
• rev() : AtagRev
• reverse() : sc_dt::sc_proxy< X > , sc_dt::sc_signed , sc_dt::sc_unsigned
• reversed() : sc_dt::sc_subref_r< X >
• revision : X86ISA::ACPI::RSDP , X86ISA::ACPI::SysDescTable
• revokeThreadContext() : Process
• rex : X86ISA::ExtMachInst
• rf : RegisterFile::RegisterEvent
• rfAccessStalls : ScheduleStage::ScheduleStageStats
• RFBUSY : ScheduleStage
• rfcr : dp_regs
• rfctl : iGbReg::Regs
• rfdr : dp_regs
• RfeOp() : ArmISA::RfeOp
• RFREADY : ScheduleStage
• rfrq : GenericTimerFrame
• rgb565_be : PixelConverter
• rgb565_le : PixelConverter
• rgba8888_be : PixelConverter
• rgba8888_le : PixelConverter
• Right : Prefetcher::BOP
• right : TimingExprBin
• rightButton : PS2Mouse
• ring : VirtQueue::VirtRing< T > , vring_avail , vring_used
• ring_base_address : kfd_ioctl_create_queue_args , kfd_ioctl_update_queue_args
• ring_size : kfd_ioctl_create_queue_args , kfd_ioctl_update_queue_args
• ringBuffer : PerfKvmCounter
• ringNumPages : PerfKvmCounter
• rip : Trace::X86NativeTrace::ThreadState , X86ISA::RemoteGDB::AMD64GdbRegCache::M5_ATTR_PACKED
• RiscvFault() : RiscvISA::RiscvFault
• RiscvMacroInst() : RiscvISA::RiscvMacroInst
• RiscvMicroInst() : RiscvISA::RiscvMicroInst
• RiscvProcess() : RiscvProcess
• RiscvProcess32() : RiscvProcess32
• RiscvProcess64() : RiscvProcess64
• RiscvRTC() : RiscvRTC
• rl_idx : HSAPacketProcessor::dma_series_ctx
• rlim_cur : ArmFreebsd32::rlimit , ArmFreebsd64::rlimit , ArmLinux32::rlimit , ArmLinux64::rlimit , Linux::rlimit , OperatingSystem::rlimit , RiscvLinux32::rlimit
• rlim_max : ArmFreebsd32::rlimit , ArmFreebsd64::rlimit , ArmLinux32::rlimit , ArmLinux64::rlimit , Linux::rlimit , OperatingSystem::rlimit , RiscvLinux32::rlimit
• rlim_t : Solaris
• rlimit_resources : ArmFreebsd64 , ArmLinux64
• rlpml : iGbReg::Regs
• rlsi : Uart8250
• RM : Gicv3CPUInterface
• rmob : Prefetcher::STeMS
• rngstep() : QTIsaac< ALPHA >
• rob : DefaultCommit< Impl >
• ROB : DefaultCommit< Impl > , DefaultRename< Impl >
• rob : FullO3CPU< Impl >
• ROB() : ROB< Impl > , SimpleCPUPolicy< Impl >
• robDep : TraceCPU::ElasticDataGen::GraphNode
• robDepList : ElasticTrace::TraceInfo
• RobDepList : TraceCPU::ElasticDataGen::GraphNode
• robEntries : DefaultRename< Impl >::FreeEntries
• RobEntry : BaseDynInst< Impl >
• ROBFullEvents : DefaultRename< Impl >::RenameStats
• robInfoFromIEW : DefaultCommit< Impl >
• robNum : TraceCPU::ElasticDataGen::GraphNode
• robPolicy : ROB< Impl >
• ROBSquashing : DefaultCommit< Impl > , ROB< Impl >
• robSquashing : TimeBufStruct< Impl >::commitComm
• ROBStats() : ROB< Impl >::ROBStats
• robStatus : ROB< Impl >
• rom : NSGigE
• romSize : X86ISA::SMBios::BiosInformation
• root : MathExpr , Root
• Root() : Root
• root : Stats::Formula
• rootdev() : AtagCore
• RootStats() : Root::RootStats
• ror() : ArmISA::Crypto
• rot : ArmISA::SveComplexIdxOp , ArmISA::SveComplexOp
• rotate : ArmISA::PredImmOp
• rotate_counter() : HMCController
• rotated_carry : ArmISA::PredImmOp
• rotated_imm : ArmISA::PredImmOp
• rotateValue() : PowerISA::IntRotateOp
• rotC : ArmISA::DataImmOp
• round : Prefetcher::BOP , sc_dt::scfx_rep
• rounding_flag() : sc_dt::sc_fxval , sc_dt::sc_fxval_fast , sc_dt::scfx_rep
• roundMax : Prefetcher::BOP
• roundRobin() : DefaultCommit< Impl > , DefaultFetch< Impl >
• roundRobinPriority() : MinorCPU
• roundTripTime : GPUDynInst
• route() : Gicv3Distributor
• route_compute() : Router
• RouteInfo() : RouteInfo
• Router() : Router
• routerID() : NetworkInterface::OutputPort
• routers : FaultModel
• routeTo : BaseXBar
• routeToHyp() : ArmISA::ArmFault , ArmISA::DataAbort , ArmISA::FastInterrupt , ArmISA::HardwareBreakpoint , ArmISA::HypervisorCall , ArmISA::IllegalInstSetStateFault , ArmISA::Interrupt , ArmISA::PCAlignmentFault , ArmISA::PrefetchAbort , ArmISA::SoftwareBreakpoint , ArmISA::SoftwareStepFault , ArmISA::SPAlignmentFault , ArmISA::SupervisorCall , ArmISA::SupervisorTrap , ArmISA::SystemError , ArmISA::UndefinedInstruction , ArmISA::Watchpoint
• routeToMonitor() : ArmISA::ArmFault , ArmISA::ArmFaultVals< T > , ArmISA::DataAbort , ArmISA::FastInterrupt , ArmISA::HypervisorCall , ArmISA::Interrupt , ArmISA::PrefetchAbort , ArmISA::SystemError
• routingUnit : Router
• RoutingUnit() : RoutingUnit
• row : MemPacket
• ROW_MASK : Gcn3ISA::InFmt_VOP_DPP
• rowAccesses : MemInterface::Bank
• rowBufferSize : MemInterface
• rows : VirtIOConsole::Config
• rowsPerBank : MemInterface
• rpb_cc : Linux::pcb_struct
• rpb_fen : Linux::pcb_struct
• rpb_ksp : Linux::pcb_struct
• rpb_psn : Linux::pcb_struct
• rpb_ptbr : Linux::pcb_struct
• rpb_unique : Linux::pcb_struct
• rpb_usp : Linux::pcb_struct
• rpct : GenericTimerFrame
• rqIdx : HSAPacketProcessor::QueueProcessEvent
• RQLEntry() : HSAPacketProcessor::RQLEntry
• rr_counter : HMCController
• rrEntries : Prefetcher::BOP
• rrLeft : Prefetcher::BOP
• rrotate() : sc_dt::sc_proxy< X >
• rrpv : ReplacementPolicy::BRRIP::BRRIPReplData
• rrRight : Prefetcher::BOP
• RRRR : Compressor::FPCD
• RRSchedulingPolicy() : RRSchedulingPolicy
• RRWay : Prefetcher::BOP
• rs : MC146818
• RSDP() : X86ISA::ACPI::RSDP
• rsdp : X86ISA::FsWorkload
• rsdt : X86ISA::ACPI::RSDP
• RSDT() : X86ISA::ACPI::RSDT
• rsh_scfx_rep : sc_dt::scfx_rep
• rshift : sc_dt::sc_fxnum , sc_dt::sc_fxnum_fast , sc_dt::sc_fxval , sc_dt::sc_fxval_fast , sc_dt::scfx_rep
• rsi : Trace::X86NativeTrace::ThreadState , X86ISA::RemoteGDB::AMD64GdbRegCache::M5_ATTR_PACKED
• rsp : tlm::tlm_transport_to_master< REQ, RSP > , Trace::X86NativeTrace::ThreadState , X86ISA::RemoteGDB::AMD64GdbRegCache::M5_ATTR_PACKED
• rsrpd : iGbReg::Regs
• RSS : Gicv3CPUInterface
• rss_hash : iGbReg::RxDesc
• rss_type : iGbReg::RxDesc
• rt : ArmISA::HTMCheckpoint
• rtc : MaltaIO
• RTC() : MaltaIO::RTC
• rtc : RiscvRTC
• RTC() : RiscvRTC::RTC
• rtc : X86ISA::Cmos
• RTCEvent() : MC146818::RTCEvent
• RTCTickEvent() : MC146818::RTCTickEvent
• rtralt() : Net::IpOpt
• rtType2 : Net::ip6_opt_hdr
• rtType2Addr() : Net::Ip6Opt
• rtType2SegLft() : Net::Ip6Opt
• rtType2Type() : Net::Ip6Opt
• rtTypeExt() : Net::Ip6Hdr
• ru_idrss : ArmFreebsd32::rusage , ArmFreebsd64::rusage , ArmLinux32::rusage , ArmLinux64::rusage , Linux::rusage , OperatingSystem::rusage
• ru_inblock : ArmFreebsd32::rusage , ArmFreebsd64::rusage , ArmLinux32::rusage , ArmLinux64::rusage , Linux::rusage , OperatingSystem::rusage
• ru_isrss : ArmFreebsd32::rusage , ArmFreebsd64::rusage , ArmLinux32::rusage , ArmLinux64::rusage , Linux::rusage , OperatingSystem::rusage
• ru_ixrss : ArmFreebsd32::rusage , ArmFreebsd64::rusage , ArmLinux32::rusage , ArmLinux64::rusage , Linux::rusage , OperatingSystem::rusage
• ru_majflt : ArmFreebsd32::rusage , ArmFreebsd64::rusage , ArmLinux32::rusage , ArmLinux64::rusage , Linux::rusage , OperatingSystem::rusage
• ru_maxrss : ArmFreebsd32::rusage , ArmFreebsd64::rusage , ArmLinux32::rusage , ArmLinux64::rusage , Linux::rusage , OperatingSystem::rusage
• ru_minflt : ArmFreebsd32::rusage , ArmFreebsd64::rusage , ArmLinux32::rusage , ArmLinux64::rusage , Linux::rusage , OperatingSystem::rusage
• ru_msgrcv : ArmFreebsd32::rusage , ArmFreebsd64::rusage , ArmLinux32::rusage , ArmLinux64::rusage , Linux::rusage , OperatingSystem::rusage
• ru_msgsnd : ArmFreebsd32::rusage , ArmFreebsd64::rusage , ArmLinux32::rusage , ArmLinux64::rusage , Linux::rusage , OperatingSystem::rusage
• ru_nivcsw : ArmFreebsd32::rusage , ArmFreebsd64::rusage , ArmLinux32::rusage , ArmLinux64::rusage , Linux::rusage , OperatingSystem::rusage
• ru_nsignals : ArmFreebsd32::rusage , ArmFreebsd64::rusage , ArmLinux32::rusage , ArmLinux64::rusage , Linux::rusage , OperatingSystem::rusage
• ru_nswap : ArmFreebsd32::rusage , ArmFreebsd64::rusage , ArmLinux32::rusage , ArmLinux64::rusage , Linux::rusage , OperatingSystem::rusage
• ru_nvcsw : ArmFreebsd32::rusage , ArmFreebsd64::rusage , ArmLinux32::rusage , ArmLinux64::rusage , Linux::rusage , OperatingSystem::rusage
• ru_oublock : ArmFreebsd32::rusage , ArmFreebsd64::rusage , ArmLinux32::rusage , ArmLinux64::rusage , Linux::rusage , OperatingSystem::rusage
• ru_stime : ArmFreebsd32::rusage , ArmFreebsd64::rusage , ArmLinux32::rusage , ArmLinux64::rusage , Linux::rusage , OperatingSystem::rusage
• ru_utime : ArmFreebsd32::rusage , ArmFreebsd64::rusage , ArmLinux32::rusage , ArmLinux64::rusage , Linux::rusage , OperatingSystem::rusage
• ruby_eviction_callback() : RubyPort
• ruby_hit_callback() : RubyPort
• RubyDirectedTester() : RubyDirectedTester
• RubyDummyPort() : RubyDummyPort
• rubyHtmCallback() : HTMSequencer
• rubyNetworkLatency : Shader::ShaderStats
• RubyPort() : RubyPort
• RubyPortProxy() : RubyPortProxy
• RubyPrefetcher() : RubyPrefetcher
• rubyPrefetcherStats : RubyPrefetcher
• RubyPrefetcherStats() : RubyPrefetcher::RubyPrefetcherStats
• rubyProfilerStats : Profiler
• RubyRequest() : RubyRequest
• RubySystem() : RubySystem
• RubyTester() : RubyTester
• rubyType : CoalescedRequest
• run() : CoreDecouplingLTInitiator , DistIface::Sync , DistIface::SyncNode , DistIface::SyncSwitch , Fiber , ItsProcess , sc_gem5::Process , sc_gem5::PythonInitFunc , sc_gem5::PythonReadyFunc , sc_gem5::ScEvent , SimpleATInitiator1 , SimpleATInitiator2 , SimpleLTInitiator1 , SimpleLTInitiator1_dmi , SimpleLTInitiator2 , SimpleLTInitiator2_dmi , SimpleLTInitiator3 , SimpleLTInitiator3_dmi , SimpleLTInitiator_ext , SMMUProcess , StatTest , tlm::tlm_slave_to_transport< REQ, RSP >
• runCycles : DefaultDecode< Impl >::DecodeStats , DefaultRename< Impl >::RenameStats
• runDelta() : sc_gem5::Scheduler
• runNext() : sc_gem5::Scheduler
• Running : BaseKvmCPU , BaseSimpleCPU , DefaultCommit< Impl > , DefaultDecode< Impl > , DefaultFetch< Impl > , DefaultIEW< Impl > , DefaultRename< Impl > , FullO3CPU< Impl >
• running : Intel8254Timer::Counter
• Running : ROB< Impl >
• running : Ticked
• RunningMMIOPending : BaseKvmCPU
• RunningService : BaseKvmCPU
• RunningServiceCompletion : BaseKvmCPU
• runNow() : sc_gem5::Scheduler
• runOnce : sc_gem5::Scheduler
• runProcess() : Gicv3Its , SMMUv3
• runProcessAtomic() : Gicv3Its , SMMUv3
• runProcessTiming() : Gicv3Its , SMMUv3
• runReady() : sc_gem5::Scheduler
• runtime_loader_kernel_symbol : AMDKernelCode
• runTimer : BaseKvmCPU
• runToTime : sc_gem5::Scheduler
• runUpdate() : sc_gem5::Scheduler
• rv32() : RiscvISA::PCState
• rvct : GenericTimerFrame
• rvec : Stats::VectorDistInfo , Stats::VectorInfoProxy< Stat >
• rvoff : GenericTimerFrame
• rw() : ArmISA::TableWalker::LongDescriptor , Intel8254Timer
• rwTable() : ArmISA::TableWalker::LongDescriptor , ArmISA::TableWalker::WalkerState
• rwvt : GenericTimerFrame
• rxActive : Sinic::Device
• rxAdvance : NSGigE
• rxBandwidth : EtherDevice::EtherDeviceStats
• rxBeginCopy : Sinic::Device
• rxbuf : Terminal
• rxbusy : Pl050
• rxBusy : Sinic::Device
• rxBusyCount : Sinic::Device
• rxBytes : EtherDevice::EtherDeviceStats
• rxcfg : dp_regs
• rxCopy : Sinic::Device
• rxCopyDone : Sinic::Device
• rxcsum : iGbReg::Regs
• RxData : Sinic::Device , Sinic::Device::VirtualReg
• rxdctl : iGbReg::Regs
• rxDelay : NSGigE
• rxDesc32 : NSGigE
• rxDesc64 : NSGigE
• rxDescCache : IGbE
• RxDescCache : IGbE , IGbE::RxDescCache
• rxDescCnt : NSGigE
• rxDescRead : NSGigE
• rxDescRefr : NSGigE
• rxDescWrite : NSGigE
• rxDirtyCount : Sinic::Device
• rxDmaAddr : NSGigE , Sinic::Device
• rxDmaData : NSGigE , Sinic::Device
• rxDmaDone() : Sinic::Device
• rxDmaEvent : Sinic::Device
• rxDmaFree : NSGigE
• rxDmaLen : NSGigE , Sinic::Device
• rxDmaPacket : IGbE
• rxDmaReadDone() : NSGigE
• rxDmaReadEvent : NSGigE
• rxDmaState : NSGigE
• rxDmaWriteDone() : NSGigE
• rxDmaWriteEvent : NSGigE
• rxDone() : DistEtherLink::RxLink
• RxDone : Sinic::Device , Sinic::Device::VirtualReg
• rxDoneData : Sinic::Device::VirtualReg
• rxdp : dp_regs
• rxdp_hi : dp_regs
• rxDump() : NSGigE , Sinic::Device
• rxEmpty : Sinic::Device
• rxEnable : NSGigE , Sinic::Base
• rxFifo : IGbE , NSGigE , Sinic::Device
• rxFifoBlock : NSGigE , Sinic::Device
• RxFifoHigh : Sinic::Device
• RxFifoLow : Sinic::Device
• rxFifoPtr : Sinic::Device
• RxFifoSize : Sinic::Device
• rxFilter() : NSGigE , Sinic::Device
• rxFilterEnable : NSGigE
• rxFragPtr : NSGigE
• rxFragWrite : NSGigE
• rxfull : Pl050
• rxHalt : NSGigE
• rxIdle : NSGigE , Sinic::Device
• rxIndex : Sinic::Device::VirtualReg
• rxint : EtherLink::Link
• rxint_enable : Pl050
• rxIntrEvent : Uart8250
• rxIpChecksums : EtherDevice::EtherDeviceStats
• rxKick() : NSGigE , Sinic::Device
• rxKickEvent : NSGigE
• rxKickTick : NSGigE , Sinic::Device
• rxLink : DistEtherLink
• RxLink() : DistEtherLink::RxLink
• rxList : Sinic::Device
• rxLow : Sinic::Device
• rxMappedCount : Sinic::Device
• RxMaxCopy : Sinic::Device
• RxMaxIntr : Sinic::Device
• rxPacket : NSGigE
• rxPacketBufPtr : NSGigE
• rxPacketBytes : Sinic::Device::VirtualReg
• rxPacketOffset : Sinic::Device::VirtualReg
• rxPacketRate : EtherDevice::EtherDeviceStats
• rxPackets : EtherDevice::EtherDeviceStats
• rxparity : Pl050
• rxPktBytes : NSGigE
• rxReset() : NSGigE
• rxState : NSGigE
• RxState : NSGigE
• rxState : Sinic::Device
• RxState : Sinic::Device
• rxStateMachine() : IGbE
• RxStatus : Sinic::Device
• rxTcpChecksums : EtherDevice::EtherDeviceStats
• rxTick : IGbE
• rxUdpChecksums : EtherDevice::EtherDeviceStats
• rxUnique : Sinic::Device , Sinic::Device::VirtualReg
• RxWait : Sinic::Device
• rxWriteDelay : IGbE
• rxXferLen : NSGigE