gem5
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arch
power
faults.hh
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/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* Copyright (c) 2009 The University of Edinburgh
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ARCH_POWER_FAULTS_HH__
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#define __ARCH_POWER_FAULTS_HH__
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#include "
sim/faults.hh
"
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namespace
gem5
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{
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namespace
PowerISA
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{
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class
PowerFault
:
public
FaultBase
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{
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protected
:
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FaultName
_name
;
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PowerFault
(
FaultName
name
)
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:
_name
(
name
)
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{
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}
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FaultName
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name
()
const
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{
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return
_name
;
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}
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};
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class
UnimplementedOpcodeFault
:
public
PowerFault
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{
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public
:
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UnimplementedOpcodeFault
()
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:
PowerFault
(
"Unimplemented Opcode"
)
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{
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}
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void
invoke
(
ThreadContext
*tc,
const
StaticInstPtr
&inst =
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nullStaticInstPtr
)
override
;
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};
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class
MachineCheckFault
:
public
PowerFault
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{
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public
:
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MachineCheckFault
()
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:
PowerFault
(
"Machine Check"
)
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{
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}
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};
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class
AlignmentFault
:
public
PowerFault
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{
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private
:
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Addr
vaddr
;
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public
:
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AlignmentFault
(
Addr
va
)
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:
PowerFault
(
"Alignment"
),
vaddr
(
va
)
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{
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}
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void
invoke
(
ThreadContext
*tc,
const
StaticInstPtr
&inst =
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nullStaticInstPtr
)
override
;
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};
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class
TrapFault
:
public
PowerFault
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{
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public
:
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TrapFault
()
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:
PowerFault
(
"Trap"
)
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{
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}
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void
invoke
(
ThreadContext
*tc,
const
StaticInstPtr
&inst =
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nullStaticInstPtr
)
override
;
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};
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}
// namespace PowerISA
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}
// namespace gem5
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#endif
// __ARCH_POWER_FAULTS_HH__
gem5::FaultBase
Definition
faults.hh:59
gem5::PowerISA::AlignmentFault
Definition
faults.hh:83
gem5::PowerISA::AlignmentFault::AlignmentFault
AlignmentFault(Addr va)
Definition
faults.hh:87
gem5::PowerISA::AlignmentFault::vaddr
Addr vaddr
Definition
faults.hh:85
gem5::PowerISA::AlignmentFault::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition
faults.cc:52
gem5::PowerISA::MachineCheckFault
Definition
faults.hh:73
gem5::PowerISA::MachineCheckFault::MachineCheckFault
MachineCheckFault()
Definition
faults.hh:75
gem5::PowerISA::PowerFault
Definition
faults.hh:42
gem5::PowerISA::PowerFault::PowerFault
PowerFault(FaultName name)
Definition
faults.hh:46
gem5::PowerISA::PowerFault::_name
FaultName _name
Definition
faults.hh:44
gem5::PowerISA::PowerFault::name
FaultName name() const
Definition
faults.hh:52
gem5::PowerISA::TrapFault
Definition
faults.hh:98
gem5::PowerISA::TrapFault::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition
faults.cc:61
gem5::PowerISA::TrapFault::TrapFault
TrapFault()
Definition
faults.hh:100
gem5::PowerISA::UnimplementedOpcodeFault
Definition
faults.hh:60
gem5::PowerISA::UnimplementedOpcodeFault::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition
faults.cc:43
gem5::PowerISA::UnimplementedOpcodeFault::UnimplementedOpcodeFault
UnimplementedOpcodeFault()
Definition
faults.hh:62
gem5::RefCountingPtr< StaticInst >
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition
guest_abi.test.cc:41
gem5::ArmISA::va
Bitfield< 8 > va
Definition
misc_types.hh:356
gem5
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition
binary32.hh:36
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition
types.hh:147
gem5::FaultName
const char * FaultName
Definition
faults.hh:55
gem5::nullStaticInstPtr
const StaticInstPtr nullStaticInstPtr
Statically allocated null StaticInstPtr.
Definition
null_static_inst.cc:36
faults.hh
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