gem5  v22.1.0.0
faults.cc
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28 
29 #include "arch/power/faults.hh"
30 
31 #include <csignal>
32 
33 #include "cpu/base.hh"
34 #include "cpu/thread_context.hh"
35 
36 namespace gem5
37 {
38 
39 namespace PowerISA
40 {
41 
42 void
44 {
45  panic_if(tc->getSystemPtr()->trapToGdb(SIGILL, tc->contextId()),
46  "Unimplemented opcode encountered at virtual address %#x\n",
47  tc->pcState().instAddr());
48 }
49 
50 void
52 {
53  panic_if(!tc->getSystemPtr()->trapToGdb(SIGBUS, tc->contextId()),
54  "Alignment fault when accessing virtual address %#x\n", vaddr);
55 }
56 
57 void
59 {
60  panic_if(tc->getSystemPtr()->trapToGdb(SIGTRAP, tc->contextId()),
61  "Trap encountered at virtual address %#x\n",
62  tc->pcState().instAddr());
63 }
64 
65 } // namespace PowerISA
66 
67 } // namespace gem5
Addr instAddr() const
Returns the memory address of the instruction this PC points to.
Definition: pcstate.hh:107
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:51
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:58
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:43
bool trapToGdb(int signal, ContextID ctx_id) const
Definition: system.cc:394
ThreadContext is the external interface to all thread state for anything outside of the CPU.
virtual const PCStateBase & pcState() const =0
virtual System * getSystemPtr()=0
virtual ContextID contextId() const =0
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:204
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....

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