gem5 v24.0.0.0
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faults.cc
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1/*
2 * Copyright (c) 2021 IBM Corporation
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include "arch/power/faults.hh"
30
31#include <csignal>
32
33#include "cpu/base.hh"
34#include "cpu/thread_context.hh"
35
36namespace gem5
37{
38
39namespace PowerISA
40{
41
42void
44{
45 if (! tc->getSystemPtr()->trapToGdb(GDBSignal::ILL, tc->contextId()) ) {
46 panic("Unimplemented opcode encountered at virtual address %#x\n",
47 tc->pcState().instAddr());
48 }
49}
50
51void
53{
54 if (! tc->getSystemPtr()->trapToGdb(GDBSignal::BUS, tc->contextId()) ) {
55 panic("Alignment fault when accessing virtual address %#x\n",
56 vaddr);
57 }
58}
59
60void
62{
63 if (! tc->getSystemPtr()->trapToGdb(GDBSignal::TRAP, tc->contextId()) ) {
64 panic("Trap encountered at virtual address %#x\n",
65 tc->pcState().instAddr());
66 }
67}
68
69} // namespace PowerISA
70
71} // namespace gem5
Addr instAddr() const
Returns the memory address of the instruction this PC points to.
Definition pcstate.hh:108
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition faults.cc:52
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition faults.cc:61
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition faults.cc:43
bool trapToGdb(GDBSignal signal, ContextID ctx_id) const
Definition system.cc:394
ThreadContext is the external interface to all thread state for anything outside of the CPU.
virtual System * getSystemPtr()=0
virtual const PCStateBase & pcState() const =0
virtual ContextID contextId() const =0
#define panic(...)
This implements a cprintf based panic() function.
Definition logging.hh:188
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36

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