| _drainManager | gem5::Drainable | private |
| _drainState | gem5::Drainable | mutableprivate |
| _driver | gem5::GPUCommandProcessor | private |
| _name | gem5::Named | private |
| _objNameResolver | gem5::SimObject | privatestatic |
| _params | gem5::SimObject | protected |
| _shader | gem5::GPUCommandProcessor | private |
| addStat(statistics::Info *info) | gem5::statistics::Group | |
| addStatGroup(const char *name, Group *block) | gem5::statistics::Group | |
| AgentCmd enum name | gem5::GPUCommandProcessor | |
| attachDriver(GPUComputeDriver *driver) | gem5::GPUCommandProcessor | |
| cacheBlockSize() const | gem5::DmaDevice | inline |
| clockDomain | gem5::Clocked | private |
| Clocked(ClockDomain &clk_domain) | gem5::Clocked | inlineprotected |
| Clocked(Clocked &)=delete | gem5::Clocked | protected |
| clockEdge(Cycles cycles=Cycles(0)) const | gem5::Clocked | inline |
| ClockedObject(const ClockedObjectParams &p) | gem5::ClockedObject | |
| clockPeriod() const | gem5::Clocked | inline |
| clockPeriodUpdated() | gem5::Clocked | inlineprotectedvirtual |
| curCycle() const | gem5::Clocked | inline |
| currentSection() | gem5::Serializable | static |
| cycle | gem5::Clocked | mutableprivate |
| cyclesToTicks(Cycles c) const | gem5::Clocked | inline |
| deschedule(Event &event) | gem5::EventManager | inline |
| deschedule(Event *event) | gem5::EventManager | inline |
| dispatcher | gem5::GPUCommandProcessor | private |
| dispatchKernelObject(AMDKernelCode *akc, void *raw_pkt, uint32_t queue_id, Addr host_pkt_addr) | gem5::GPUCommandProcessor | |
| dispatchPkt(HSAQueueEntry *task) | gem5::GPUCommandProcessor | |
| dispatchStartTime | gem5::GPUCommandProcessor | private |
| DmaDevice(const Params &p) | gem5::DmaDevice | |
| DmaFnPtr typedef | gem5::GPUCommandProcessor | private |
| dmaPending() const | gem5::DmaDevice | inline |
| dmaPort | gem5::DmaDevice | protected |
| dmaRead(Addr addr, int size, Event *event, uint8_t *data, uint32_t sid, uint32_t ssid, Tick delay=0) | gem5::DmaDevice | inline |
| dmaRead(Addr addr, int size, Event *event, uint8_t *data, Tick delay=0) | gem5::DmaDevice | inline |
| dmaReadVirt(Addr host_addr, unsigned size, DmaCallback *cb, void *data, Tick delay=0) | gem5::DmaVirtDevice | |
| dmaVirt(DmaFnPtr dmaFn, Addr host_addr, unsigned size, DmaCallback *cb, void *data, Tick delay=0) | gem5::DmaVirtDevice | |
| DmaVirtDevice(const Params &p) | gem5::DmaVirtDevice | inline |
| dmaWrite(Addr addr, int size, Event *event, uint8_t *data, uint32_t sid, uint32_t ssid, Tick delay=0) | gem5::DmaDevice | inline |
| dmaWrite(Addr addr, int size, Event *event, uint8_t *data, Tick delay=0) | gem5::DmaDevice | inline |
| dmaWriteVirt(Addr host_addr, unsigned size, DmaCallback *b, void *data, Tick delay=0) | gem5::DmaVirtDevice | |
| dmDrain() | gem5::Drainable | private |
| dmDrainResume() | gem5::Drainable | private |
| drain() override | gem5::SimObject | inlinevirtual |
| Drainable() | gem5::Drainable | protected |
| drainResume() | gem5::Drainable | inlineprotectedvirtual |
| drainState() const | gem5::Drainable | inline |
| driver() | gem5::GPUCommandProcessor | |
| dynamic_task_id | gem5::GPUCommandProcessor | private |
| EventManager(EventManager &em) | gem5::EventManager | inline |
| EventManager(EventManager *em) | gem5::EventManager | inline |
| EventManager(EventQueue *eq) | gem5::EventManager | inline |
| eventq | gem5::EventManager | protected |
| eventQueue() const | gem5::EventManager | inline |
| find(const char *name) | gem5::SimObject | static |
| frequency() const | gem5::Clocked | inline |
| functionalReadHsaSignal(Addr signal_handle) | gem5::GPUCommandProcessor | |
| generateCheckpointOut(const std::string &cpt_dir, std::ofstream &outstream) | gem5::Serializable | static |
| getAddrRanges() const override | gem5::GPUCommandProcessor | virtual |
| getHsaSignalEventAddr(Addr signal_handle) | gem5::GPUCommandProcessor | inline |
| getHsaSignalMailboxAddr(Addr signal_handle) | gem5::GPUCommandProcessor | inline |
| getHsaSignalValueAddr(Addr signal_handle) | gem5::GPUCommandProcessor | inline |
| getPort(const std::string &if_name, PortID idx=InvalidPortID) override | gem5::DmaDevice | virtual |
| getProbeManager() | gem5::SimObject | |
| getSimObjectResolver() | gem5::SimObject | static |
| getStatGroups() const | gem5::statistics::Group | |
| getStats() const | gem5::statistics::Group | |
| GPUCommandProcessor()=delete | gem5::GPUCommandProcessor | |
| GPUCommandProcessor(const Params &p) | gem5::GPUCommandProcessor | |
| gpuDevice | gem5::GPUCommandProcessor | private |
| Group()=delete | gem5::statistics::Group | |
| Group(const Group &)=delete | gem5::statistics::Group | |
| Group(Group *parent, const char *name=nullptr) | gem5::statistics::Group | |
| hsaPacketProc() | gem5::GPUCommandProcessor | |
| hsaPP | gem5::GPUCommandProcessor | private |
| HsaSignalCallbackFunction typedef | gem5::GPUCommandProcessor | |
| init() override | gem5::DmaDevice | virtual |
| initABI(HSAQueueEntry *task) | gem5::GPUCommandProcessor | private |
| initState() | gem5::SimObject | virtual |
| loadState(CheckpointIn &cp) | gem5::SimObject | virtual |
| memInvalidate() | gem5::SimObject | inlinevirtual |
| memWriteback() | gem5::SimObject | inlinevirtual |
| mergedParent | gem5::statistics::Group | private |
| mergedStatGroups | gem5::statistics::Group | private |
| mergeStatGroup(Group *block) | gem5::statistics::Group | |
| MQDDmaEvent(HSAQueueEntry *task) | gem5::GPUCommandProcessor | inlineprivate |
| name() const | gem5::Named | inlinevirtual |
| Named(const std::string &name_) | gem5::Named | inline |
| nextCycle() const | gem5::Clocked | inline |
| non_blit_kernel_id | gem5::GPUCommandProcessor | private |
| Nop enum value | gem5::GPUCommandProcessor | |
| notifyFork() | gem5::Drainable | inlinevirtual |
| gem5::operator=(const Group &)=delete | gem5::statistics::Group | |
| gem5::Clocked::operator=(Clocked &)=delete | gem5::Clocked | protected |
| Params typedef | gem5::GPUCommandProcessor | |
| params() const | gem5::SimObject | inline |
| path | gem5::Serializable | privatestatic |
| PioDevice(const Params &p) | gem5::PioDevice | |
| pioPort | gem5::PioDevice | protected |
| powerState | gem5::ClockedObject | |
| preDumpStats() | gem5::statistics::Group | virtual |
| probeManager | gem5::SimObject | private |
| read(PacketPtr pkt) override | gem5::GPUCommandProcessor | inlinevirtual |
| ReadDispIdOffsetDmaEvent(HSAQueueEntry *task, const uint32_t &readDispIdOffset) | gem5::GPUCommandProcessor | inlineprivate |
| regProbeListeners() | gem5::SimObject | virtual |
| regProbePoints() | gem5::SimObject | virtual |
| regStats() | gem5::statistics::Group | virtual |
| reschedule(Event &event, Tick when, bool always=false) | gem5::EventManager | inline |
| reschedule(Event *event, Tick when, bool always=false) | gem5::EventManager | inline |
| resetClock() const | gem5::Clocked | inlineprotected |
| resetStats() | gem5::statistics::Group | virtual |
| resolveStat(std::string name) const | gem5::statistics::Group | |
| sanityCheckAKC(AMDKernelCode *akc) | gem5::GPUCommandProcessor | private |
| schedule(Event &event, Tick when) | gem5::EventManager | inline |
| schedule(Event *event, Tick when) | gem5::EventManager | inline |
| sendCompletionSignal(Addr signal_handle) | gem5::GPUCommandProcessor | |
| Serializable() | gem5::Serializable | |
| serialize(CheckpointOut &cp) const override | gem5::ClockedObject | virtual |
| serializeAll(const std::string &cpt_dir) | gem5::SimObject | static |
| serializeSection(CheckpointOut &cp, const char *name) const | gem5::Serializable | |
| serializeSection(CheckpointOut &cp, const std::string &name) const | gem5::Serializable | inline |
| setCurTick(Tick newVal) | gem5::EventManager | inline |
| setGPUDevice(AMDGPUDevice *gpu_device) | gem5::GPUCommandProcessor | |
| setShader(Shader *shader) | gem5::GPUCommandProcessor | |
| setSimObjectResolver(SimObjectResolver *resolver) | gem5::SimObject | static |
| shader() | gem5::GPUCommandProcessor | |
| signalDrainDone() const | gem5::Drainable | inlineprotected |
| signalWakeupEvent(uint32_t event_id) | gem5::GPUCommandProcessor | |
| SimObject(const Params &p) | gem5::SimObject | |
| SimObjectList typedef | gem5::SimObject | private |
| simObjectList | gem5::SimObject | privatestatic |
| startup() | gem5::SimObject | virtual |
| statGroups | gem5::statistics::Group | private |
| stats | gem5::statistics::Group | private |
| Steal enum value | gem5::GPUCommandProcessor | |
| submitAgentDispatchPkt(void *raw_pkt, uint32_t queue_id, Addr host_pkt_addr) | gem5::GPUCommandProcessor | |
| submitDispatchPkt(void *raw_pkt, uint32_t queue_id, Addr host_pkt_addr) | gem5::GPUCommandProcessor | |
| submitVendorPkt(void *raw_pkt, uint32_t queue_id, Addr host_pkt_addr) | gem5::GPUCommandProcessor | |
| sys | gem5::PioDevice | protected |
| system() | gem5::GPUCommandProcessor | |
| target_non_blit_kernel_id | gem5::GPUCommandProcessor | private |
| tick | gem5::Clocked | mutableprivate |
| ticksToCycles(Tick t) const | gem5::Clocked | inline |
| translate(Addr vaddr, Addr size) override | gem5::GPUCommandProcessor | privatevirtual |
| unserialize(CheckpointIn &cp) override | gem5::ClockedObject | virtual |
| unserializeSection(CheckpointIn &cp, const char *name) | gem5::Serializable | |
| unserializeSection(CheckpointIn &cp, const std::string &name) | gem5::Serializable | inline |
| update() const | gem5::Clocked | inlineprivate |
| updateClockPeriod() | gem5::Clocked | inline |
| updateHsaEventData(Addr signal_handle, uint64_t *event_value) | gem5::GPUCommandProcessor | |
| updateHsaEventTs(Addr signal_handle, amd_event_t *event_value) | gem5::GPUCommandProcessor | |
| updateHsaMailboxData(Addr signal_handle, uint64_t *mailbox_value) | gem5::GPUCommandProcessor | |
| updateHsaSignal(Addr signal_handle, uint64_t signal_value, HsaSignalCallbackFunction function=[](const uint64_t &) { }) | gem5::GPUCommandProcessor | |
| updateHsaSignalAsync(Addr signal_handle, int64_t diff) | gem5::GPUCommandProcessor | |
| updateHsaSignalData(Addr value_addr, int64_t diff, uint64_t *prev_value) | gem5::GPUCommandProcessor | |
| updateHsaSignalDone(uint64_t *signal_value) | gem5::GPUCommandProcessor | |
| voltage() const | gem5::Clocked | inline |
| vramRequestorId() | gem5::GPUCommandProcessor | |
| WaitScratchDmaEvent(HSAQueueEntry *task, const uint64_t &dmaBuffer) | gem5::GPUCommandProcessor | inlineprivate |
| wakeupEventQueue(Tick when=(Tick) -1) | gem5::EventManager | inline |
| walker | gem5::GPUCommandProcessor | private |
| write(PacketPtr pkt) override | gem5::GPUCommandProcessor | inlinevirtual |
| ~Clocked() | gem5::Clocked | inlineprotectedvirtual |
| ~DmaDevice()=default | gem5::DmaDevice | virtual |
| ~DmaVirtDevice() | gem5::DmaVirtDevice | inlinevirtual |
| ~Drainable() | gem5::Drainable | protectedvirtual |
| ~Group() | gem5::statistics::Group | virtual |
| ~Named()=default | gem5::Named | virtual |
| ~PioDevice() | gem5::PioDevice | virtual |
| ~Serializable() | gem5::Serializable | virtual |
| ~SimObject() | gem5::SimObject | virtual |