gem5  v21.1.0.2
Public Types | Public Member Functions | Private Types | Private Member Functions | Private Attributes | List of all members
gem5::GPUCommandProcessor Class Reference

#include <gpu_command_processor.hh>

Inheritance diagram for gem5::GPUCommandProcessor:
gem5::DmaVirtDevice gem5::DmaDevice gem5::PioDevice gem5::ClockedObject gem5::SimObject gem5::Clocked gem5::EventManager gem5::Serializable gem5::Drainable gem5::statistics::Group gem5::Named

Public Types

enum  AgentCmd { Nop = 0, Steal = 1 }
 
typedef GPUCommandProcessorParams Params
 
typedef std::function< void(const uint64_t &)> HsaSignalCallbackFunction
 
- Public Types inherited from gem5::DmaVirtDevice
typedef void(DmaDevice::* DmaFnPtr) (Addr, int, Event *, uint8_t *, Tick)
 
- Public Types inherited from gem5::DmaDevice
typedef DmaDeviceParams Params
 
- Public Types inherited from gem5::PioDevice
using Params = PioDeviceParams
 
- Public Types inherited from gem5::ClockedObject
using Params = ClockedObjectParams
 Parameters of ClockedObject. More...
 
- Public Types inherited from gem5::SimObject
typedef SimObjectParams Params
 

Public Member Functions

 GPUCommandProcessor ()=delete
 
 GPUCommandProcessor (const Params &p)
 
HSAPacketProcessorhsaPacketProc ()
 
void setShader (Shader *shader)
 
Shadershader ()
 
GPUComputeDriverdriver ()
 
void submitAgentDispatchPkt (void *raw_pkt, uint32_t queue_id, Addr host_pkt_addr)
 submitAgentDispatchPkt() is for accepting agent dispatch packets. More...
 
void submitDispatchPkt (void *raw_pkt, uint32_t queue_id, Addr host_pkt_addr)
 submitDispatchPkt() is the entry point into the CP from the HSAPP and is only meant to be used with AQL kernel dispatch packets. More...
 
void submitVendorPkt (void *raw_pkt, uint32_t queue_id, Addr host_pkt_addr)
 submitVendorPkt() is for accepting vendor-specific packets from the HSAPP. More...
 
void attachDriver (GPUComputeDriver *driver)
 
void dispatchPkt (HSAQueueEntry *task)
 Once the CP has finished extracting all relevant information about a task and has initialized the ABI state, we send a description of the task to the dispatcher. More...
 
void signalWakeupEvent (uint32_t event_id)
 
Tick write (PacketPtr pkt) override
 Pure virtual function that the device must implement. More...
 
Tick read (PacketPtr pkt) override
 Pure virtual function that the device must implement. More...
 
AddrRangeList getAddrRanges () const override
 Every PIO device is obliged to provide an implementation that returns the address ranges the device responds to. More...
 
Systemsystem ()
 
void updateHsaSignal (Addr signal_handle, uint64_t signal_value, HsaSignalCallbackFunction function=[](const uint64_t &) { })
 
uint64_t functionalReadHsaSignal (Addr signal_handle)
 
Addr getHsaSignalValueAddr (Addr signal_handle)
 
Addr getHsaSignalMailboxAddr (Addr signal_handle)
 
Addr getHsaSignalEventAddr (Addr signal_handle)
 
- Public Member Functions inherited from gem5::DmaVirtDevice
 DmaVirtDevice (const Params &p)
 
virtual ~DmaVirtDevice ()
 
void dmaReadVirt (Addr host_addr, unsigned size, DmaCallback *cb, void *data, Tick delay=0)
 Initiate a DMA read from virtual address host_addr. More...
 
void dmaWriteVirt (Addr host_addr, unsigned size, DmaCallback *b, void *data, Tick delay=0)
 Initiate a DMA write from virtual address host_addr. More...
 
void dmaVirt (DmaFnPtr dmaFn, Addr host_addr, unsigned size, DmaCallback *cb, void *data, Tick delay=0)
 Initiate a call to DmaDevice using DmaFnPtr do a DMA starting from virtual address host_addr for size number of bytes on the data. More...
 
- Public Member Functions inherited from gem5::DmaDevice
 DmaDevice (const Params &p)
 
virtual ~DmaDevice ()=default
 
void dmaWrite (Addr addr, int size, Event *event, uint8_t *data, uint32_t sid, uint32_t ssid, Tick delay=0)
 
void dmaWrite (Addr addr, int size, Event *event, uint8_t *data, Tick delay=0)
 
void dmaRead (Addr addr, int size, Event *event, uint8_t *data, uint32_t sid, uint32_t ssid, Tick delay=0)
 
void dmaRead (Addr addr, int size, Event *event, uint8_t *data, Tick delay=0)
 
bool dmaPending () const
 
void init () override
 init() is called after all C++ SimObjects have been created and all ports are connected. More...
 
unsigned int cacheBlockSize () const
 
PortgetPort (const std::string &if_name, PortID idx=InvalidPortID) override
 Get a port with a given name and index. More...
 
- Public Member Functions inherited from gem5::PioDevice
 PioDevice (const Params &p)
 
virtual ~PioDevice ()
 
void init () override
 init() is called after all C++ SimObjects have been created and all ports are connected. More...
 
PortgetPort (const std::string &if_name, PortID idx=InvalidPortID) override
 Get a port with a given name and index. More...
 
- Public Member Functions inherited from gem5::ClockedObject
 ClockedObject (const ClockedObjectParams &p)
 
void serialize (CheckpointOut &cp) const override
 Serialize an object. More...
 
void unserialize (CheckpointIn &cp) override
 Unserialize an object. More...
 
- Public Member Functions inherited from gem5::SimObject
const Paramsparams () const
 
 SimObject (const Params &p)
 
virtual ~SimObject ()
 
virtual void loadState (CheckpointIn &cp)
 loadState() is called on each SimObject when restoring from a checkpoint. More...
 
virtual void initState ()
 initState() is called on each SimObject when not restoring from a checkpoint. More...
 
virtual void regProbePoints ()
 Register probe points for this object. More...
 
virtual void regProbeListeners ()
 Register probe listeners for this object. More...
 
ProbeManagergetProbeManager ()
 Get the probe manager for this object. More...
 
virtual void startup ()
 startup() is the final initialization call before simulation. More...
 
DrainState drain () override
 Provide a default implementation of the drain interface for objects that don't need draining. More...
 
virtual void memWriteback ()
 Write back dirty buffers to memory using functional writes. More...
 
virtual void memInvalidate ()
 Invalidate the contents of memory buffers. More...
 
void serialize (CheckpointOut &cp) const override
 Serialize an object. More...
 
void unserialize (CheckpointIn &cp) override
 Unserialize an object. More...
 
- Public Member Functions inherited from gem5::EventManager
EventQueueeventQueue () const
 
void schedule (Event &event, Tick when)
 
void deschedule (Event &event)
 
void reschedule (Event &event, Tick when, bool always=false)
 
void schedule (Event *event, Tick when)
 
void deschedule (Event *event)
 
void reschedule (Event *event, Tick when, bool always=false)
 
void wakeupEventQueue (Tick when=(Tick) -1)
 This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers. More...
 
void setCurTick (Tick newVal)
 
 EventManager (EventManager &em)
 Event manger manages events in the event queue. More...
 
 EventManager (EventManager *em)
 
 EventManager (EventQueue *eq)
 
- Public Member Functions inherited from gem5::Serializable
 Serializable ()
 
virtual ~Serializable ()
 
void serializeSection (CheckpointOut &cp, const char *name) const
 Serialize an object into a new section. More...
 
void serializeSection (CheckpointOut &cp, const std::string &name) const
 
void unserializeSection (CheckpointIn &cp, const char *name)
 Unserialize an a child object. More...
 
void unserializeSection (CheckpointIn &cp, const std::string &name)
 
- Public Member Functions inherited from gem5::Drainable
DrainState drainState () const
 Return the current drain state of an object. More...
 
virtual void notifyFork ()
 Notify a child process of a fork. More...
 
- Public Member Functions inherited from gem5::statistics::Group
 Group (Group *parent, const char *name=nullptr)
 Construct a new statistics group. More...
 
virtual ~Group ()
 
virtual void regStats ()
 Callback to set stat parameters. More...
 
virtual void resetStats ()
 Callback to reset stats. More...
 
virtual void preDumpStats ()
 Callback before stats are dumped. More...
 
void addStat (statistics::Info *info)
 Register a stat with this group. More...
 
const std::map< std::string, Group * > & getStatGroups () const
 Get all child groups associated with this object. More...
 
const std::vector< Info * > & getStats () const
 Get all stats associated with this object. More...
 
void addStatGroup (const char *name, Group *block)
 Add a stat block as a child of this block. More...
 
const InforesolveStat (std::string name) const
 Resolve a stat by its name within this group. More...
 
void mergeStatGroup (Group *block)
 Merge the contents (stats & children) of a block to this block. More...
 
 Group ()=delete
 
 Group (const Group &)=delete
 
Groupoperator= (const Group &)=delete
 
- Public Member Functions inherited from gem5::Named
 Named (const std::string &name_)
 
virtual ~Named ()=default
 
virtual std::string name () const
 
- Public Member Functions inherited from gem5::Clocked
void updateClockPeriod ()
 Update the tick to the current tick. More...
 
Tick clockEdge (Cycles cycles=Cycles(0)) const
 Determine the tick when a cycle begins, by default the current one, but the argument also enables the caller to determine a future cycle. More...
 
Cycles curCycle () const
 Determine the current cycle, corresponding to a tick aligned to a clock edge. More...
 
Tick nextCycle () const
 Based on the clock of the object, determine the start tick of the first cycle that is at least one cycle in the future. More...
 
uint64_t frequency () const
 
Tick clockPeriod () const
 
double voltage () const
 
Cycles ticksToCycles (Tick t) const
 
Tick cyclesToTicks (Cycles c) const
 

Private Types

typedef void(DmaDevice::* DmaFnPtr) (Addr, int, Event *, uint8_t *, Tick)
 

Private Member Functions

void initABI (HSAQueueEntry *task)
 The CP is responsible for traversing all HSA-ABI-related data structures from memory and initializing the ABI state. More...
 
void translateOrDie (Addr vaddr, Addr &paddr) override
 Function used to translate from virtual to physical addresses. More...
 
void ReadDispIdOffsetDmaEvent (HSAQueueEntry *task, const uint32_t &readDispIdOffset)
 Perform a DMA read of the read_dispatch_id_field_base_byte_offset field, which follows directly after the read_dispatch_id (the read pointer) in the amd_hsa_queue_t struct (aka memory queue descriptor (MQD)), to find the base address of the MQD. More...
 
void MQDDmaEvent (HSAQueueEntry *task)
 Perform a DMA read of the MQD that corresponds to a hardware queue descriptor (HQD). More...
 
void WaitScratchDmaEvent (HSAQueueEntry *task, const uint64_t &dmaBuffer)
 Poll on queue_inactive signal until the runtime can get around to taking care of our lack of scratch space. More...
 

Private Attributes

Shader_shader
 
GPUDispatcherdispatcher
 
GPUComputeDriver_driver
 
HSAPacketProcessorhsaPP
 

Additional Inherited Members

- Static Public Member Functions inherited from gem5::SimObject
static void serializeAll (const std::string &cpt_dir)
 Create a checkpoint by serializing all SimObjects in the system. More...
 
static SimObjectfind (const char *name)
 Find the SimObject with the given name and return a pointer to it. More...
 
static void setSimObjectResolver (SimObjectResolver *resolver)
 There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More...
 
static SimObjectResolvergetSimObjectResolver ()
 There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More...
 
- Static Public Member Functions inherited from gem5::Serializable
static const std::string & currentSection ()
 Gets the fully-qualified name of the active section. More...
 
static void generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream)
 Generate a checkpoint file so that the serialization can be routed to it. More...
 
- Public Attributes inherited from gem5::ClockedObject
PowerStatepowerState
 
- Protected Member Functions inherited from gem5::Drainable
 Drainable ()
 
virtual ~Drainable ()
 
virtual void drainResume ()
 Resume execution after a successful drain. More...
 
void signalDrainDone () const
 Signal that an object is drained. More...
 
- Protected Member Functions inherited from gem5::Clocked
 Clocked (ClockDomain &clk_domain)
 Create a clocked object and set the clock domain based on the parameters. More...
 
 Clocked (Clocked &)=delete
 
Clockedoperator= (Clocked &)=delete
 
virtual ~Clocked ()
 Virtual destructor due to inheritance. More...
 
void resetClock () const
 Reset the object's clock using the current global tick value. More...
 
virtual void clockPeriodUpdated ()
 A hook subclasses can implement so they can do any extra work that's needed when the clock rate is changed. More...
 
- Protected Attributes inherited from gem5::DmaDevice
DmaPort dmaPort
 
- Protected Attributes inherited from gem5::PioDevice
Systemsys
 
PioPort< PioDevicepioPort
 The pioPort that handles the requests for us and provides us requests that it sees. More...
 
- Protected Attributes inherited from gem5::SimObject
const SimObjectParams & _params
 Cached copy of the object parameters. More...
 
- Protected Attributes inherited from gem5::EventManager
EventQueueeventq
 A pointer to this object's event queue. More...
 

Detailed Description

Definition at line 71 of file gpu_command_processor.hh.

Member Typedef Documentation

◆ DmaFnPtr

typedef void(DmaDevice::* gem5::GPUCommandProcessor::DmaFnPtr) (Addr, int, Event *, uint8_t *, Tick)
private

Definition at line 135 of file gpu_command_processor.hh.

◆ HsaSignalCallbackFunction

typedef std::function<void(const uint64_t &)> gem5::GPUCommandProcessor::HsaSignalCallbackFunction

Definition at line 75 of file gpu_command_processor.hh.

◆ Params

typedef GPUCommandProcessorParams gem5::GPUCommandProcessor::Params

Definition at line 74 of file gpu_command_processor.hh.

Member Enumeration Documentation

◆ AgentCmd

Enumerator
Nop 
Steal 

Definition at line 86 of file gpu_command_processor.hh.

Constructor & Destructor Documentation

◆ GPUCommandProcessor() [1/2]

gem5::GPUCommandProcessor::GPUCommandProcessor ( )
delete

◆ GPUCommandProcessor() [2/2]

gem5::GPUCommandProcessor::GPUCommandProcessor ( const Params p)

Member Function Documentation

◆ attachDriver()

void gem5::GPUCommandProcessor::attachDriver ( GPUComputeDriver driver)

Definition at line 221 of file gpu_command_processor.cc.

References _driver, and fatal_if.

Referenced by gem5::GPUComputeDriver::GPUComputeDriver().

◆ dispatchPkt()

void gem5::GPUCommandProcessor::dispatchPkt ( HSAQueueEntry task)

Once the CP has finished extracting all relevant information about a task and has initialized the ABI state, we send a description of the task to the dispatcher.

The dispatcher will create and dispatch WGs to the CUs.

Definition at line 315 of file gpu_command_processor.cc.

References gem5::GPUDispatcher::dispatch(), and dispatcher.

Referenced by MQDDmaEvent().

◆ driver()

GPUComputeDriver * gem5::GPUCommandProcessor::driver ( )

Definition at line 231 of file gpu_command_processor.cc.

References _driver.

Referenced by gem5::ComputeUnit::sendRequest(), and gem5::HSAPacketProcessor::write().

◆ functionalReadHsaSignal()

uint64_t gem5::GPUCommandProcessor::functionalReadHsaSignal ( Addr  signal_handle)

◆ getAddrRanges()

AddrRangeList gem5::GPUCommandProcessor::getAddrRanges ( ) const
overridevirtual

Every PIO device is obliged to provide an implementation that returns the address ranges the device responds to.

Returns
a list of non-overlapping address ranges

Implements gem5::PioDevice.

Definition at line 353 of file gpu_command_processor.cc.

◆ getHsaSignalEventAddr()

Addr gem5::GPUCommandProcessor::getHsaSignalEventAddr ( Addr  signal_handle)
inline

Definition at line 124 of file gpu_command_processor.hh.

Referenced by updateHsaSignal().

◆ getHsaSignalMailboxAddr()

Addr gem5::GPUCommandProcessor::getHsaSignalMailboxAddr ( Addr  signal_handle)
inline

Definition at line 119 of file gpu_command_processor.hh.

Referenced by updateHsaSignal().

◆ getHsaSignalValueAddr()

Addr gem5::GPUCommandProcessor::getHsaSignalValueAddr ( Addr  signal_handle)
inline

◆ hsaPacketProc()

HSAPacketProcessor & gem5::GPUCommandProcessor::hsaPacketProc ( )

◆ initABI()

void gem5::GPUCommandProcessor::initABI ( HSAQueueEntry task)
private

The CP is responsible for traversing all HSA-ABI-related data structures from memory and initializing the ABI state.

Information provided by the MQD, AQL packet, and code object metadata will be used to initialze register file state.

Definition at line 333 of file gpu_command_processor.cc.

References gem5::DmaVirtDevice::DmaVirtCallback< T >::dmaBuffer, gem5::DmaVirtDevice::dmaReadVirt(), gem5::HSAPacketProcessor::getQueueDesc(), hsaPP, gem5::HSAQueueEntry::queueId(), and ReadDispIdOffsetDmaEvent().

Referenced by submitDispatchPkt().

◆ MQDDmaEvent()

void gem5::GPUCommandProcessor::MQDDmaEvent ( HSAQueueEntry task)
inlineprivate

Perform a DMA read of the MQD that corresponds to a hardware queue descriptor (HQD).

We store a copy of the MQD in the HSAQueueEntry object so we can send a copy of it along with a dispatch packet, which is needed to initialize register state.

dGPUs on any version of ROCm and APUs starting with ROCm 2.2 can perform lazy allocation of private segment (scratch) memory, where the runtime will intentianally underallocate scratch resources to save framebuffer (or system on APU) memory. If we don't have enough scratch memory to launch this kernel, we need to raise a recoverable error code to the runtime by asserting queue_inactive_signal for the queue. The runtime will then try to allocate more scratch and reset this signal. When the signal is reset we should check that the runtime was successful and then proceed to launch the kernel.

Definition at line 185 of file gpu_command_processor.hh.

References gem5::HSAQueueEntry::amdQueue, gem5::_amd_queue_t::compute_tmpring_size_wavesize, dispatchPkt(), DPRINTF, fatal_if, gem5::_hsa_signal_t::handle, hsaPP, gem5::HSAPacketProcessor::inFlightPkts(), gem5::HSAQueueEntry::privMemPerItem(), gem5::_amd_queue_t::queue_inactive_signal, gem5::HSAQueueEntry::queueId(), and updateHsaSignal().

Referenced by ReadDispIdOffsetDmaEvent(), and WaitScratchDmaEvent().

◆ read()

Tick gem5::GPUCommandProcessor::read ( PacketPtr  pkt)
inlineoverridevirtual

Pure virtual function that the device must implement.

Called when a read command is recieved by the port.

Parameters
pktPacket describing this request
Returns
number of ticks it took to complete

Implements gem5::PioDevice.

Definition at line 104 of file gpu_command_processor.hh.

◆ ReadDispIdOffsetDmaEvent()

void gem5::GPUCommandProcessor::ReadDispIdOffsetDmaEvent ( HSAQueueEntry task,
const uint32_t &  readDispIdOffset 
)
inlineprivate

Perform a DMA read of the read_dispatch_id_field_base_byte_offset field, which follows directly after the read_dispatch_id (the read pointer) in the amd_hsa_queue_t struct (aka memory queue descriptor (MQD)), to find the base address of the MQD.

The MQD is the runtime's soft representation of a HW queue descriptor (HQD).

Any fields below the read dispatch ID in the amd_hsa_queue_t should not change according to the HSA standard, therefore we should be able to get them based on their known relative position to the read dispatch ID.

Now that the read pointer's offset from the base of the MQD is known, we can use that to calculate the the address of the MQD itself, the dispatcher will DMA that into the HSAQueueEntry when a kernel is launched.

DMA a copy of the MQD into the task. some fields of the MQD will be used to initialize register state in VI

Definition at line 153 of file gpu_command_processor.hh.

References gem5::HSAQueueEntry::amdQueue, gem5::DmaVirtDevice::dmaReadVirt(), gem5::HSAPacketProcessor::getQueueDesc(), gem5::HSAQueueEntry::hostAMDQueueAddr, gem5::HSAQueueDescriptor::hostReadIndexPtr, hsaPP, MQDDmaEvent(), and gem5::HSAQueueEntry::queueId().

Referenced by initABI().

◆ setShader()

void gem5::GPUCommandProcessor::setShader ( Shader shader)

Definition at line 360 of file gpu_command_processor.cc.

References _shader, and shader().

◆ shader()

Shader * gem5::GPUCommandProcessor::shader ( )

Definition at line 366 of file gpu_command_processor.cc.

References _shader.

Referenced by setShader().

◆ signalWakeupEvent()

void gem5::GPUCommandProcessor::signalWakeupEvent ( uint32_t  event_id)

Definition at line 321 of file gpu_command_processor.cc.

References _driver, and gem5::GPUComputeDriver::signalWakeupEvent().

Referenced by updateHsaSignal().

◆ submitAgentDispatchPkt()

void gem5::GPUCommandProcessor::submitAgentDispatchPkt ( void *  raw_pkt,
uint32_t  queue_id,
Addr  host_pkt_addr 
)

submitAgentDispatchPkt() is for accepting agent dispatch packets.

These packets will control the dispatch of Wg on the device, and inform the host when a specified number of Wg have been executed on the device.

For now it simply finishes the pkt.

Definition at line 268 of file gpu_command_processor.cc.

References gem5::_hsa_agent_dispatch_packet_t::arg, gem5::HSAQueueEntry::completionSignal(), dispatcher, gem5::DmaVirtDevice::dmaWriteVirt(), DPRINTF, gem5::HSAPacketProcessor::finishPkt(), hsaPP, gem5::GPUDispatcher::hsaTask(), Nop(), panic, gem5::_hsa_agent_dispatch_packet_t::return_address, and gem5::_hsa_agent_dispatch_packet_t::type.

Referenced by gem5::HSAPacketProcessor::processPkt().

◆ submitDispatchPkt()

void gem5::GPUCommandProcessor::submitDispatchPkt ( void *  raw_pkt,
uint32_t  queue_id,
Addr  host_pkt_addr 
)

submitDispatchPkt() is the entry point into the CP from the HSAPP and is only meant to be used with AQL kernel dispatch packets.

After the HSAPP receives and extracts an AQL packet, it sends it to the CP, which is responsible for gathering all relevant information about a task, initializing CU state, and sending it to the dispatcher for WG creation and dispatch.

First we need capture all information from the the AQL pkt and the code object, then store it in an HSAQueueEntry. Once the packet and code are extracted, we extract information from the queue descriptor that the CP needs to perform state initialization on the CU. Finally we call dispatch() to send the task to the dispatcher. When the task completely finishes, we call finishPkt() on the HSA packet processor in order to remove the packet from the queue, and notify the runtime that the task has completed.

we need to read a pointer in the application's address space to pull out the kernel code descriptor.

The kernel_object is a pointer to the machine code, whose entry point is an 'amd_kernel_code_t' type, which is included in the kernel binary, and describes various aspects of the kernel. The desired entry is the 'kernel_code_entry_byte_offset' field, which provides the byte offset (positive or negative) from the address of the amd_kernel_code_t to the start of the machine instructions.

BLIT kernels don't have symbol names. BLIT kernels are built-in compute kernels issued by ROCm to handle DMAs for dGPUs when the SDMA hardware engines are unavailable or explicitly disabled. They can also be used to do copies that ROCm things would be better performed by the shader than the SDMA engines. They are also sometimes used on APUs to implement asynchronous memcopy operations from 2 pointers in host memory. I have no idea what BLIT stands for.

Definition at line 98 of file gpu_command_processor.cc.

References gem5::HSAQueueEntry::codeAddr(), gem5::_hsa_dispatch_packet_t::completion_signal, DPRINTF, gem5::_hsa_dispatch_packet_t::grid_size_x, gem5::_hsa_dispatch_packet_t::grid_size_y, gem5::_hsa_dispatch_packet_t::grid_size_z, initABI(), gem5::_hsa_dispatch_packet_t::kernarg_address, gem5::AMDKernelCode::kernel_code_entry_byte_offset, gem5::_hsa_dispatch_packet_t::kernel_object, gem5::HSAQueueEntry::numScalarRegs(), gem5::HSAQueueEntry::numVectorRegs(), gem5::AMDKernelCode::runtime_loader_kernel_symbol, gem5::PioDevice::sys, gem5::System::threads, gem5::_hsa_dispatch_packet_t::workgroup_size_x, gem5::_hsa_dispatch_packet_t::workgroup_size_y, and gem5::_hsa_dispatch_packet_t::workgroup_size_z.

Referenced by gem5::HSAPacketProcessor::processPkt().

◆ submitVendorPkt()

void gem5::GPUCommandProcessor::submitVendorPkt ( void *  raw_pkt,
uint32_t  queue_id,
Addr  host_pkt_addr 
)

submitVendorPkt() is for accepting vendor-specific packets from the HSAPP.

Vendor-specific packets may be used by the runtime to send commands to the HSA device that are specific to a particular vendor. The vendor-specific packets should be defined by the vendor in the runtime. TODO: For now we simply tell the HSAPP to finish the packet, however a future patch will update this method to provide the proper handling of any required vendor-specific packets. In the version of ROCm that is currently supported (1.6) the runtime will send packets that direct the CP to invalidate the GPUs caches. We do this automatically on each kernel launch in the CU, so this is safe for now.

Definition at line 254 of file gpu_command_processor.cc.

References gem5::HSAPacketProcessor::finishPkt(), and hsaPP.

Referenced by gem5::HSAPacketProcessor::processPkt().

◆ system()

System * gem5::GPUCommandProcessor::system ( )

Definition at line 347 of file gpu_command_processor.cc.

References gem5::PioDevice::sys.

Referenced by functionalReadHsaSignal(), and updateHsaSignal().

◆ translateOrDie()

void gem5::GPUCommandProcessor::translateOrDie ( Addr  vaddr,
Addr paddr 
)
overrideprivatevirtual

Function used to translate from virtual to physical addresses.

All classes inheriting from DmaVirtDevice must define this.

Parameters
vaddrInput virtual address
paddrOutput physical address written by reference

Grab the process and try to translate the virtual address with it; with new extensions, it will likely be wrong to just arbitrarily grab context zero.

Implements gem5::DmaVirtDevice.

Definition at line 66 of file gpu_command_processor.cc.

References fatal, gem5::PioDevice::sys, gem5::System::threads, and gem5::MipsISA::vaddr.

◆ updateHsaSignal()

void gem5::GPUCommandProcessor::updateHsaSignal ( Addr  signal_handle,
uint64_t  signal_value,
HsaSignalCallbackFunction  function = [] (const uint64_t &) { } 
)

◆ WaitScratchDmaEvent()

void gem5::GPUCommandProcessor::WaitScratchDmaEvent ( HSAQueueEntry task,
const uint64_t &  dmaBuffer 
)
inlineprivate

Poll on queue_inactive signal until the runtime can get around to taking care of our lack of scratch space.

Runtime will have updated the MQD to give us more scratch space. Read it out and continue to pester the runtime until we get all that we need to launch.

TODO: Technically only need to update private segment fields since other MQD entries won't change since we last read them.

Poll until runtime signals us that scratch space has been allocated.

Definition at line 239 of file gpu_command_processor.hh.

References gem5::HSAQueueEntry::amdQueue, gem5::DmaVirtDevice::dmaReadVirt(), DPRINTF, getHsaSignalValueAddr(), gem5::_hsa_signal_t::handle, gem5::HSAQueueEntry::hostAMDQueueAddr, MQDDmaEvent(), and gem5::_amd_queue_t::queue_inactive_signal.

◆ write()

Tick gem5::GPUCommandProcessor::write ( PacketPtr  pkt)
inlineoverridevirtual

Pure virtual function that the device must implement.

Called when a write command is recieved by the port.

Parameters
pktPacket describing this request
Returns
number of ticks it took to complete

Implements gem5::PioDevice.

Definition at line 103 of file gpu_command_processor.hh.

Member Data Documentation

◆ _driver

GPUComputeDriver* gem5::GPUCommandProcessor::_driver
private

Definition at line 132 of file gpu_command_processor.hh.

Referenced by attachDriver(), driver(), and signalWakeupEvent().

◆ _shader

Shader* gem5::GPUCommandProcessor::_shader
private

Definition at line 130 of file gpu_command_processor.hh.

Referenced by setShader(), and shader().

◆ dispatcher

GPUDispatcher& gem5::GPUCommandProcessor::dispatcher
private

◆ hsaPP

HSAPacketProcessor* gem5::GPUCommandProcessor::hsaPP
private

The documentation for this class was generated from the following files:

Generated on Tue Sep 21 2021 12:27:38 for gem5 by doxygen 1.8.17