| _drainManager | gem5::Drainable | private |
| _drainState | gem5::Drainable | mutableprivate |
| _name | gem5::Named | private |
| _objNameResolver | gem5::SimObject | privatestatic |
| _params | gem5::SimObject | protected |
| ack_id | gem5::GicV2 | protected |
| activeInt | gem5::GicV2 | protected |
| addrRanges | gem5::GicV2 | protected |
| addStat(statistics::Info *info) | gem5::statistics::Group | |
| addStatGroup(const char *name, Group *block) | gem5::statistics::Group | |
| bankedRegs | gem5::GicV2 | protected |
| BaseGic(const Params &p) | gem5::BaseGic | |
| BitUnion32(SWI) Bitfield< 3 | gem5::GicV2 | protected |
| blockIntUpdate() const | gem5::BaseGic | inlineprotectedvirtual |
| clearBankedDistRange(System *sys, GicV2Registers *to, Addr daddr, size_t size) | gem5::GicV2Registers | protectedstatic |
| clearDistRange(GicV2Registers *to, Addr daddr, size_t size) | gem5::GicV2Registers | protectedstatic |
| clearInt(ContextID ctx, uint32_t int_num) | gem5::GicV2 | protected |
| clearInt(uint32_t number) override | gem5::GicV2 | virtual |
| clearPPInt(uint32_t num, uint32_t cpu) override | gem5::GicV2 | virtual |
| clockDomain | gem5::Clocked | private |
| Clocked(ClockDomain &clk_domain) | gem5::Clocked | inlineprotected |
| Clocked(Clocked &)=delete | gem5::Clocked | protected |
| clockEdge(Cycles cycles=Cycles(0)) const | gem5::Clocked | inline |
| ClockedObject(const ClockedObjectParams &p) | gem5::ClockedObject | |
| clockPeriod() const | gem5::Clocked | inline |
| clockPeriodUpdated() | gem5::Clocked | inlineprotectedvirtual |
| copyBankedDistRange(System *sys, GicV2Registers *from, GicV2Registers *to, Addr daddr, size_t size) | gem5::GicV2Registers | protectedstatic |
| copyCpuRegister(GicV2Registers *from, GicV2Registers *to, ContextID ctx, Addr daddr) | gem5::GicV2Registers | protectedstatic |
| copyDistRange(GicV2Registers *from, GicV2Registers *to, Addr daddr, size_t size) | gem5::GicV2Registers | protectedstatic |
| copyDistRegister(GicV2Registers *from, GicV2Registers *to, ContextID ctx, Addr daddr) | gem5::GicV2Registers | protectedstatic |
| copyGicState(GicV2Registers *from, GicV2Registers *to) | gem5::GicV2 | protected |
| cpu_id | gem5::GicV2 | protected |
| cpu_list | gem5::GicV2 | protected |
| CPU_MAX | gem5::GicV2 | protectedstatic |
| cpuBpr | gem5::GicV2 | protected |
| cpuControl | gem5::GicV2 | protected |
| cpuEnabled(ContextID ctx) const | gem5::GicV2 | inlineprotected |
| cpuHighestInt | gem5::GicV2 | protected |
| cpuPioDelay | gem5::GicV2 | protected |
| cpuPpiActive | gem5::GicV2 | protected |
| cpuPpiPending | gem5::GicV2 | protected |
| cpuPriority | gem5::GicV2 | protected |
| cpuRange | gem5::GicV2 | protected |
| cpuSgiActive | gem5::GicV2 | protected |
| cpuSgiActiveExt | gem5::GicV2 | protected |
| cpuSgiPending | gem5::GicV2 | protected |
| cpuSgiPendingExt | gem5::GicV2 | protected |
| cpuTarget | gem5::GicV2 | protected |
| curCycle() const | gem5::Clocked | inline |
| currentSection() | gem5::Serializable | static |
| cycle | gem5::Clocked | mutableprivate |
| cyclesToTicks(Cycles c) const | gem5::Clocked | inline |
| deschedule(Event &event) | gem5::EventManager | inline |
| deschedule(Event *event) | gem5::EventManager | inline |
| DIST_SIZE enum value | gem5::GicV2 | protected |
| distPioDelay | gem5::GicV2 | protected |
| dmDrain() | gem5::Drainable | private |
| dmDrainResume() | gem5::Drainable | private |
| drain() override | gem5::GicV2 | virtual |
| Drainable() | gem5::Drainable | protected |
| drainResume() override | gem5::GicV2 | virtual |
| drainState() const | gem5::Drainable | inline |
| enabled | gem5::GicV2 | protected |
| enableGrp0 | gem5::GicV2 | protected |
| enableGrp1 | gem5::GicV2 | protected |
| EndBitUnion(SWI) BitUnion32(IAR) Bitfield< 9 | gem5::GicV2 | protected |
| EndBitUnion(IAR) BitUnion32(CTLR) Bitfield< 3 > fiqEn | gem5::GicV2 | protected |
| EventManager(EventManager &em) | gem5::EventManager | inline |
| EventManager(EventManager *em) | gem5::EventManager | inline |
| EventManager(EventQueue *eq) | gem5::EventManager | inline |
| eventq | gem5::EventManager | protected |
| eventQueue() const | gem5::EventManager | inline |
| find(const char *name) | gem5::SimObject | static |
| frequency() const | gem5::Clocked | inline |
| gem5ExtensionsEnabled | gem5::GicV2 | protected |
| generateCheckpointOut(const std::string &cpt_dir, std::ofstream &outstream) | gem5::Serializable | static |
| genSwiMask(int cpu) | gem5::GicV2 | protected |
| getActiveInt(ContextID ctx, uint32_t ix) | gem5::GicV2 | inlineprotected |
| getAddrRanges() const override | gem5::GicV2 | inlinevirtual |
| getBankedRegs(ContextID) | gem5::GicV2 | protected |
| getCpuPriority(unsigned cpu) | gem5::GicV2 | protected |
| getCpuTarget(ContextID ctx, uint32_t ix) const | gem5::GicV2 | inlineprotected |
| getIntConfig(ContextID ctx, uint32_t ix) | gem5::GicV2 | inlineprotected |
| getIntEnabled(ContextID ctx, uint32_t ix) | gem5::GicV2 | inlineprotected |
| getIntGroup(ContextID ctx, uint32_t ix) | gem5::GicV2 | inlineprotected |
| getIntPriority(ContextID ctx, uint32_t ix) | gem5::GicV2 | inlineprotected |
| getPendingInt(ContextID ctx, uint32_t ix) | gem5::GicV2 | inlineprotected |
| getPort(const std::string &if_name, PortID idx=InvalidPortID) override | gem5::PioDevice | virtual |
| getProbeManager() | gem5::SimObject | |
| getSimObjectResolver() | gem5::SimObject | static |
| getStatGroups() const | gem5::statistics::Group | |
| getStats() const | gem5::statistics::Group | |
| getSystem() const | gem5::BaseGic | inline |
| GICC_ABPR enum value | gem5::GicV2 | protected |
| GICC_APR0 enum value | gem5::GicV2 | protected |
| GICC_APR1 enum value | gem5::GicV2 | protected |
| GICC_APR2 enum value | gem5::GicV2 | protected |
| GICC_APR3 enum value | gem5::GicV2 | protected |
| GICC_BPR enum value | gem5::GicV2 | protected |
| GICC_BPR_MINIMUM | gem5::GicV2 | protectedstatic |
| GICC_CTLR enum value | gem5::GicV2 | protected |
| GICC_DIR enum value | gem5::GicV2 | protected |
| GICC_EOIR enum value | gem5::GicV2 | protected |
| GICC_HPPIR enum value | gem5::GicV2 | protected |
| GICC_IAR enum value | gem5::GicV2 | protected |
| GICC_IIDR enum value | gem5::GicV2 | protected |
| GICC_PMR enum value | gem5::GicV2 | protected |
| GICC_RPR enum value | gem5::GicV2 | protected |
| giccIIDR | gem5::GicV2 | protected |
| GICD_CTLR enum value | gem5::GicV2 | protected |
| GICD_ICACTIVER | gem5::GicV2 | protectedstatic |
| GICD_ICENABLER | gem5::GicV2 | protectedstatic |
| GICD_ICFGR | gem5::GicV2 | protectedstatic |
| GICD_ICPENDR | gem5::GicV2 | protectedstatic |
| GICD_IGROUPR | gem5::GicV2 | protectedstatic |
| GICD_IIDR enum value | gem5::GicV2 | protected |
| GICD_IPRIORITYR | gem5::GicV2 | protectedstatic |
| GICD_ISACTIVER | gem5::GicV2 | protectedstatic |
| GICD_ISENABLER | gem5::GicV2 | protectedstatic |
| GICD_ISPENDR | gem5::GicV2 | protectedstatic |
| GICD_ITARGETSR | gem5::GicV2 | protectedstatic |
| GICD_PIDR0 enum value | gem5::GicV2 | protected |
| GICD_PIDR1 enum value | gem5::GicV2 | protected |
| GICD_PIDR2 enum value | gem5::GicV2 | protected |
| GICD_PIDR3 enum value | gem5::GicV2 | protected |
| GICD_SGIR enum value | gem5::GicV2 | protected |
| GICD_TYPER enum value | gem5::GicV2 | protected |
| gicdIIDR | gem5::GicV2 | protected |
| gicdPIDR | gem5::GicV2 | protected |
| GicV2(const Params &p) | gem5::GicV2 | |
| GicVersion enum name | gem5::BaseGic | |
| GLOBAL_INT_LINES | gem5::GicV2 | protectedstatic |
| Group()=delete | gem5::statistics::Group | |
| Group(const Group &)=delete | gem5::statistics::Group | |
| Group(Group *parent, const char *name=nullptr) | gem5::statistics::Group | |
| haveGem5Extensions | gem5::GicV2 | protected |
| iccrpr | gem5::GicV2 | protected |
| init() override | gem5::BaseGic | virtual |
| initState() | gem5::SimObject | virtual |
| INT_BITS_MAX | gem5::GicV2 | protectedstatic |
| INT_LINES_MAX | gem5::GicV2 | protectedstatic |
| intConfig | gem5::GicV2 | protected |
| intEnabled | gem5::GicV2 | protected |
| intGroup | gem5::GicV2 | protected |
| intLatency | gem5::GicV2 | protected |
| intNumToBit(int num) const | gem5::GicV2 | inlineprotected |
| intNumToWord(int num) const | gem5::GicV2 | inlineprotected |
| intPriority | gem5::GicV2 | protected |
| isFiq(ContextID ctx, uint32_t int_num) | gem5::GicV2 | inlineprotected |
| isGroup0(ContextID ctx, uint32_t int_num) | gem5::GicV2 | inlineprotected |
| isLevelSensitive(ContextID ctx, uint32_t int_num) | gem5::GicV2 | inlineprotected |
| itLines | gem5::GicV2 | protected |
| list_type | gem5::GicV2 | protected |
| loadState(CheckpointIn &cp) | gem5::SimObject | virtual |
| memInvalidate() | gem5::SimObject | inlinevirtual |
| memWriteback() | gem5::SimObject | inlinevirtual |
| mergedParent | gem5::statistics::Group | private |
| mergedStatGroups | gem5::statistics::Group | private |
| mergeStatGroup(Group *block) | gem5::statistics::Group | |
| name() const | gem5::Named | inlinevirtual |
| Named(const std::string &name_) | gem5::Named | inline |
| nextCycle() const | gem5::Clocked | inline |
| NN_CONFIG_MASK | gem5::GicV2 | protectedstatic |
| notifyFork() | gem5::Drainable | inlinevirtual |
| gem5::operator=(const Group &)=delete | gem5::statistics::Group | |
| gem5::Clocked::operator=(Clocked &)=delete | gem5::Clocked | protected |
| Params typedef | gem5::GicV2 | |
| params() const | gem5::BaseGic | |
| path | gem5::Serializable | privatestatic |
| pendingDelayedInterrupts | gem5::GicV2 | protected |
| pendingInt | gem5::GicV2 | protected |
| PioDevice(const Params &p) | gem5::PioDevice | |
| pioPort | gem5::PioDevice | protected |
| platform | gem5::BaseGic | protected |
| postDelayedFiq(uint32_t cpu) | gem5::GicV2 | protected |
| postDelayedInt(uint32_t cpu) | gem5::GicV2 | protected |
| postFiq(uint32_t cpu, Tick when) | gem5::GicV2 | protected |
| postFiqEvent | gem5::GicV2 | protected |
| postInt(uint32_t cpu, Tick when) | gem5::GicV2 | protected |
| postIntEvent | gem5::GicV2 | protected |
| powerState | gem5::ClockedObject | |
| PPI_MAX | gem5::GicV2 | protectedstatic |
| preDumpStats() | gem5::statistics::Group | virtual |
| probeManager | gem5::SimObject | private |
| read(PacketPtr pkt) override | gem5::GicV2 | virtual |
| readCpu(PacketPtr pkt) | gem5::GicV2 | protected |
| readCpu(ContextID ctx, Addr daddr) override | gem5::GicV2 | protectedvirtual |
| readDistributor(PacketPtr pkt) | gem5::GicV2 | protected |
| readDistributor(ContextID ctx, Addr daddr, size_t resp_sz) | gem5::GicV2 | protected |
| readDistributor(ContextID ctx, Addr daddr) override | gem5::GicV2 | inlineprotectedvirtual |
| regProbeListeners() | gem5::SimObject | virtual |
| regProbePoints() | gem5::SimObject | virtual |
| regStats() | gem5::statistics::Group | virtual |
| reschedule(Event &event, Tick when, bool always=false) | gem5::EventManager | inline |
| reschedule(Event *event, Tick when, bool always=false) | gem5::EventManager | inline |
| resetClock() const | gem5::Clocked | inlineprotected |
| resetStats() | gem5::statistics::Group | virtual |
| resolveStat(std::string name) const | gem5::statistics::Group | |
| schedule(Event &event, Tick when) | gem5::EventManager | inline |
| schedule(Event *event, Tick when) | gem5::EventManager | inline |
| sendInt(uint32_t number) override | gem5::GicV2 | virtual |
| sendPPInt(uint32_t num, uint32_t cpu) override | gem5::GicV2 | virtual |
| Serializable() | gem5::Serializable | |
| serialize(CheckpointOut &cp) const override | gem5::GicV2 | virtual |
| serializeAll(const std::string &cpt_dir) | gem5::SimObject | static |
| serializeSection(CheckpointOut &cp, const char *name) const | gem5::Serializable | |
| serializeSection(CheckpointOut &cp, const std::string &name) const | gem5::Serializable | inline |
| setCurTick(Tick newVal) | gem5::EventManager | inline |
| setSimObjectResolver(SimObjectResolver *resolver) | gem5::SimObject | static |
| sgi_id | gem5::GicV2 | protected |
| SGI_MASK | gem5::GicV2 | protectedstatic |
| SGI_MAX | gem5::GicV2 | protectedstatic |
| signalDrainDone() const | gem5::Drainable | inlineprotected |
| SimObject(const Params &p) | gem5::SimObject | |
| simObjectList | gem5::SimObject | privatestatic |
| SimObjectList typedef | gem5::SimObject | private |
| softInt(ContextID ctx, SWI swi) | gem5::GicV2 | protected |
| SPURIOUS_INT | gem5::GicV2 | protectedstatic |
| startup() | gem5::SimObject | virtual |
| statGroups | gem5::statistics::Group | private |
| stats | gem5::statistics::Group | private |
| supportsVersion(GicVersion version) override | gem5::GicV2 | virtual |
| sys | gem5::PioDevice | protected |
| tick | gem5::Clocked | mutableprivate |
| ticksToCycles(Tick t) const | gem5::Clocked | inline |
| unserialize(CheckpointIn &cp) override | gem5::GicV2 | virtual |
| unserializeSection(CheckpointIn &cp, const char *name) | gem5::Serializable | |
| unserializeSection(CheckpointIn &cp, const std::string &name) | gem5::Serializable | inline |
| update() const | gem5::Clocked | inlineprivate |
| updateClockPeriod() | gem5::Clocked | inline |
| updateIntState(int hint) | gem5::GicV2 | protected |
| updateRunPri() | gem5::GicV2 | protected |
| voltage() const | gem5::Clocked | inline |
| wakeupEventQueue(Tick when=(Tick) -1) | gem5::EventManager | inline |
| write(PacketPtr pkt) override | gem5::GicV2 | virtual |
| writeCpu(PacketPtr pkt) | gem5::GicV2 | protected |
| writeCpu(ContextID ctx, Addr daddr, uint32_t data) override | gem5::GicV2 | protectedvirtual |
| writeDistributor(PacketPtr pkt) | gem5::GicV2 | protected |
| writeDistributor(ContextID ctx, Addr daddr, uint32_t data, size_t data_sz) | gem5::GicV2 | protected |
| writeDistributor(ContextID ctx, Addr daddr, uint32_t data) override | gem5::GicV2 | inlineprotectedvirtual |
| ~BaseGic() | gem5::BaseGic | virtual |
| ~Clocked() | gem5::Clocked | inlineprotectedvirtual |
| ~Drainable() | gem5::Drainable | protectedvirtual |
| ~GicV2() | gem5::GicV2 | |
| ~Group() | gem5::statistics::Group | virtual |
| ~Named()=default | gem5::Named | virtual |
| ~PioDevice() | gem5::PioDevice | virtual |
| ~Serializable() | gem5::Serializable | virtual |
| ~SimObject() | gem5::SimObject | virtual |