gem5  v21.1.0.2
gem5::GicV2 Member List

This is the complete list of members for gem5::GicV2, including all inherited members.

_drainManagergem5::Drainableprivate
_drainStategem5::Drainablemutableprivate
_namegem5::Namedprivate
_objNameResolvergem5::SimObjectprivatestatic
_paramsgem5::SimObjectprotected
ack_idgem5::GicV2protected
activeIntgem5::GicV2protected
addrRangesgem5::GicV2protected
addStat(statistics::Info *info)gem5::statistics::Group
addStatGroup(const char *name, Group *block)gem5::statistics::Group
bankedRegsgem5::GicV2protected
BaseGic(const Params &p)gem5::BaseGic
BitUnion32(SWI) Bitfield< 3gem5::GicV2protected
clearInt(ContextID ctx, uint32_t int_num)gem5::GicV2protected
clearInt(uint32_t number) overridegem5::GicV2virtual
clearPPInt(uint32_t num, uint32_t cpu) overridegem5::GicV2virtual
clockDomaingem5::Clockedprivate
Clocked(ClockDomain &clk_domain)gem5::Clockedinlineprotected
Clocked(Clocked &)=deletegem5::Clockedprotected
clockEdge(Cycles cycles=Cycles(0)) constgem5::Clockedinline
ClockedObject(const ClockedObjectParams &p)gem5::ClockedObject
clockPeriod() constgem5::Clockedinline
clockPeriodUpdated()gem5::Clockedinlineprotectedvirtual
cpu_idgem5::GicV2protected
cpu_listgem5::GicV2protected
CPU_MAXgem5::GicV2protectedstatic
cpuBprgem5::GicV2protected
cpuControlgem5::GicV2protected
cpuEnabled(ContextID ctx) constgem5::GicV2inlineprotected
cpuHighestIntgem5::GicV2protected
cpuPioDelaygem5::GicV2protected
cpuPpiActivegem5::GicV2protected
cpuPpiPendinggem5::GicV2protected
cpuPrioritygem5::GicV2protected
cpuRangegem5::GicV2protected
cpuSgiActivegem5::GicV2protected
cpuSgiActiveExtgem5::GicV2protected
cpuSgiPendinggem5::GicV2protected
cpuSgiPendingExtgem5::GicV2protected
cpuTargetgem5::GicV2protected
curCycle() constgem5::Clockedinline
currentSection()gem5::Serializablestatic
cyclegem5::Clockedmutableprivate
cyclesToTicks(Cycles c) constgem5::Clockedinline
deschedule(Event &event)gem5::EventManagerinline
deschedule(Event *event)gem5::EventManagerinline
DIST_SIZE enum valuegem5::GicV2protected
distPioDelaygem5::GicV2protected
dmDrain()gem5::Drainableprivate
dmDrainResume()gem5::Drainableprivate
drain() overridegem5::GicV2virtual
Drainable()gem5::Drainableprotected
drainResume() overridegem5::GicV2virtual
drainState() constgem5::Drainableinline
enabledgem5::GicV2protected
enableGrp0gem5::GicV2protected
enableGrp1gem5::GicV2protected
EndBitUnion(SWI) BitUnion32(IAR) Bitfield< 9gem5::GicV2protected
EndBitUnion(IAR) BitUnion32(CTLR) Bitfield< 3 > fiqEngem5::GicV2protected
EventManager(EventManager &em)gem5::EventManagerinline
EventManager(EventManager *em)gem5::EventManagerinline
EventManager(EventQueue *eq)gem5::EventManagerinline
eventqgem5::EventManagerprotected
eventQueue() constgem5::EventManagerinline
find(const char *name)gem5::SimObjectstatic
frequency() constgem5::Clockedinline
gem5ExtensionsEnabledgem5::GicV2protected
generateCheckpointOut(const std::string &cpt_dir, std::ofstream &outstream)gem5::Serializablestatic
genSwiMask(int cpu)gem5::GicV2protected
getActiveInt(ContextID ctx, uint32_t ix)gem5::GicV2inlineprotected
getAddrRanges() const overridegem5::GicV2inlinevirtual
getBankedRegs(ContextID)gem5::GicV2protected
getCpuPriority(unsigned cpu)gem5::GicV2protected
getCpuTarget(ContextID ctx, uint32_t ix) constgem5::GicV2inlineprotected
getIntConfig(ContextID ctx, uint32_t ix)gem5::GicV2inlineprotected
getIntEnabled(ContextID ctx, uint32_t ix)gem5::GicV2inlineprotected
getIntGroup(ContextID ctx, uint32_t ix)gem5::GicV2inlineprotected
getIntPriority(ContextID ctx, uint32_t ix)gem5::GicV2inlineprotected
getPendingInt(ContextID ctx, uint32_t ix)gem5::GicV2inlineprotected
getPort(const std::string &if_name, PortID idx=InvalidPortID) overridegem5::PioDevicevirtual
getProbeManager()gem5::SimObject
getSimObjectResolver()gem5::SimObjectstatic
getStatGroups() constgem5::statistics::Group
getStats() constgem5::statistics::Group
getSystem() constgem5::BaseGicinline
GICC_ABPR enum valuegem5::GicV2protected
GICC_APR0 enum valuegem5::GicV2protected
GICC_APR1 enum valuegem5::GicV2protected
GICC_APR2 enum valuegem5::GicV2protected
GICC_APR3 enum valuegem5::GicV2protected
GICC_BPR enum valuegem5::GicV2protected
GICC_BPR_MINIMUMgem5::GicV2protectedstatic
GICC_CTLR enum valuegem5::GicV2protected
GICC_DIR enum valuegem5::GicV2protected
GICC_EOIR enum valuegem5::GicV2protected
GICC_HPPIR enum valuegem5::GicV2protected
GICC_IAR enum valuegem5::GicV2protected
GICC_IIDR enum valuegem5::GicV2protected
GICC_PMR enum valuegem5::GicV2protected
GICC_RPR enum valuegem5::GicV2protected
giccIIDRgem5::GicV2protected
GICD_CTLR enum valuegem5::GicV2protected
GICD_ICACTIVERgem5::GicV2protectedstatic
GICD_ICENABLERgem5::GicV2protectedstatic
GICD_ICFGRgem5::GicV2protectedstatic
GICD_ICPENDRgem5::GicV2protectedstatic
GICD_IGROUPRgem5::GicV2protectedstatic
GICD_IIDR enum valuegem5::GicV2protected
GICD_IPRIORITYRgem5::GicV2protectedstatic
GICD_ISACTIVERgem5::GicV2protectedstatic
GICD_ISENABLERgem5::GicV2protectedstatic
GICD_ISPENDRgem5::GicV2protectedstatic
GICD_ITARGETSRgem5::GicV2protectedstatic
GICD_PIDR0 enum valuegem5::GicV2protected
GICD_PIDR1 enum valuegem5::GicV2protected
GICD_PIDR2 enum valuegem5::GicV2protected
GICD_PIDR3 enum valuegem5::GicV2protected
GICD_SGIR enum valuegem5::GicV2protected
GICD_TYPER enum valuegem5::GicV2protected
gicdIIDRgem5::GicV2protected
gicdPIDRgem5::GicV2protected
GicV2(const Params &p)gem5::GicV2
GicVersion enum namegem5::BaseGic
GLOBAL_INT_LINESgem5::GicV2protectedstatic
Group()=deletegem5::statistics::Group
Group(const Group &)=deletegem5::statistics::Group
Group(Group *parent, const char *name=nullptr)gem5::statistics::Group
haveGem5Extensionsgem5::GicV2protected
iccrprgem5::GicV2protected
init() overridegem5::BaseGicvirtual
initState()gem5::SimObjectvirtual
INT_BITS_MAXgem5::GicV2protectedstatic
INT_LINES_MAXgem5::GicV2protectedstatic
intConfiggem5::GicV2protected
intEnabledgem5::GicV2protected
intGroupgem5::GicV2protected
intLatencygem5::GicV2protected
intNumToBit(int num) constgem5::GicV2inlineprotected
intNumToWord(int num) constgem5::GicV2inlineprotected
intPrioritygem5::GicV2protected
isFiq(ContextID ctx, uint32_t int_num)gem5::GicV2inlineprotected
isGroup0(ContextID ctx, uint32_t int_num)gem5::GicV2inlineprotected
isLevelSensitive(ContextID ctx, uint32_t int_num)gem5::GicV2inlineprotected
itLinesgem5::GicV2protected
list_typegem5::GicV2protected
loadState(CheckpointIn &cp)gem5::SimObjectvirtual
memInvalidate()gem5::SimObjectinlinevirtual
memWriteback()gem5::SimObjectinlinevirtual
mergedParentgem5::statistics::Groupprivate
mergedStatGroupsgem5::statistics::Groupprivate
mergeStatGroup(Group *block)gem5::statistics::Group
name() constgem5::Namedinlinevirtual
Named(const std::string &name_)gem5::Namedinline
nextCycle() constgem5::Clockedinline
NN_CONFIG_MASKgem5::GicV2protectedstatic
notifyFork()gem5::Drainableinlinevirtual
gem5::operator=(const Group &)=deletegem5::statistics::Group
gem5::Clocked::operator=(Clocked &)=deletegem5::Clockedprotected
params() constgem5::BaseGic
Params typedefgem5::GicV2
pathgem5::Serializableprivatestatic
pendingDelayedInterruptsgem5::GicV2protected
pendingIntgem5::GicV2protected
PioDevice(const Params &p)gem5::PioDevice
pioPortgem5::PioDeviceprotected
platformgem5::BaseGicprotected
postDelayedFiq(uint32_t cpu)gem5::GicV2protected
postDelayedInt(uint32_t cpu)gem5::GicV2protected
postFiq(uint32_t cpu, Tick when)gem5::GicV2protected
postFiqEventgem5::GicV2protected
postInt(uint32_t cpu, Tick when)gem5::GicV2protected
postIntEventgem5::GicV2protected
powerStategem5::ClockedObject
PPI_MAXgem5::GicV2protectedstatic
preDumpStats()gem5::statistics::Groupvirtual
probeManagergem5::SimObjectprivate
read(PacketPtr pkt) overridegem5::GicV2virtual
readCpu(PacketPtr pkt)gem5::GicV2protected
readCpu(ContextID ctx, Addr daddr) overridegem5::GicV2protectedvirtual
readDistributor(PacketPtr pkt)gem5::GicV2protected
readDistributor(ContextID ctx, Addr daddr, size_t resp_sz)gem5::GicV2protected
readDistributor(ContextID ctx, Addr daddr) overridegem5::GicV2inlineprotectedvirtual
regProbeListeners()gem5::SimObjectvirtual
regProbePoints()gem5::SimObjectvirtual
regStats()gem5::statistics::Groupvirtual
reschedule(Event &event, Tick when, bool always=false)gem5::EventManagerinline
reschedule(Event *event, Tick when, bool always=false)gem5::EventManagerinline
resetClock() constgem5::Clockedinlineprotected
resetStats()gem5::statistics::Groupvirtual
resolveStat(std::string name) constgem5::statistics::Group
schedule(Event &event, Tick when)gem5::EventManagerinline
schedule(Event *event, Tick when)gem5::EventManagerinline
sendInt(uint32_t number) overridegem5::GicV2virtual
sendPPInt(uint32_t num, uint32_t cpu) overridegem5::GicV2virtual
Serializable()gem5::Serializable
serialize(CheckpointOut &cp) const overridegem5::GicV2virtual
serializeAll(const std::string &cpt_dir)gem5::SimObjectstatic
serializeSection(CheckpointOut &cp, const char *name) constgem5::Serializable
serializeSection(CheckpointOut &cp, const std::string &name) constgem5::Serializableinline
setCurTick(Tick newVal)gem5::EventManagerinline
setSimObjectResolver(SimObjectResolver *resolver)gem5::SimObjectstatic
sgi_idgem5::GicV2protected
SGI_MASKgem5::GicV2protectedstatic
SGI_MAXgem5::GicV2protectedstatic
signalDrainDone() constgem5::Drainableinlineprotected
SimObject(const Params &p)gem5::SimObject
SimObjectList typedefgem5::SimObjectprivate
simObjectListgem5::SimObjectprivatestatic
softInt(ContextID ctx, SWI swi)gem5::GicV2protected
SPURIOUS_INTgem5::GicV2protectedstatic
startup()gem5::SimObjectvirtual
statGroupsgem5::statistics::Groupprivate
statsgem5::statistics::Groupprivate
supportsVersion(GicVersion version) overridegem5::GicV2virtual
sysgem5::PioDeviceprotected
tickgem5::Clockedmutableprivate
ticksToCycles(Tick t) constgem5::Clockedinline
unserialize(CheckpointIn &cp) overridegem5::GicV2virtual
unserializeSection(CheckpointIn &cp, const char *name)gem5::Serializable
unserializeSection(CheckpointIn &cp, const std::string &name)gem5::Serializableinline
update() constgem5::Clockedinlineprivate
updateClockPeriod()gem5::Clockedinline
updateIntState(int hint)gem5::GicV2protectedvirtual
updateRunPri()gem5::GicV2protected
voltage() constgem5::Clockedinline
wakeupEventQueue(Tick when=(Tick) -1)gem5::EventManagerinline
write(PacketPtr pkt) overridegem5::GicV2virtual
writeCpu(PacketPtr pkt)gem5::GicV2protected
writeCpu(ContextID ctx, Addr daddr, uint32_t data) overridegem5::GicV2protectedvirtual
writeDistributor(PacketPtr pkt)gem5::GicV2protected
writeDistributor(ContextID ctx, Addr daddr, uint32_t data, size_t data_sz)gem5::GicV2protected
writeDistributor(ContextID ctx, Addr daddr, uint32_t data) overridegem5::GicV2inlineprotectedvirtual
~BaseGic()gem5::BaseGicvirtual
~Clocked()gem5::Clockedinlineprotectedvirtual
~Drainable()gem5::Drainableprotectedvirtual
~GicV2()gem5::GicV2
~Group()gem5::statistics::Groupvirtual
~Named()=defaultgem5::Namedvirtual
~PioDevice()gem5::PioDevicevirtual
~Serializable()gem5::Serializablevirtual
~SimObject()gem5::SimObjectvirtual

Generated on Tue Sep 21 2021 12:27:38 for gem5 by doxygen 1.8.17