gem5  v22.1.0.0
gem5::HMCController Member List

This is the complete list of members for gem5::HMCController, including all inherited members.

_drainManagergem5::Drainableprivate
_drainStategem5::Drainablemutableprivate
_namegem5::Namedprivate
_objNameResolvergem5::SimObjectprivatestatic
_paramsgem5::SimObjectprotected
addStat(statistics::Info *info)gem5::statistics::Group
addStatGroup(const char *name, Group *block)gem5::statistics::Group
BaseXBar(const BaseXBarParams &p)gem5::BaseXBarprotected
calcPacketTiming(PacketPtr pkt, Tick header_delay)gem5::BaseXBarprotected
clockDomaingem5::Clockedprivate
Clocked(ClockDomain &clk_domain)gem5::Clockedinlineprotected
Clocked(Clocked &)=deletegem5::Clockedprotected
clockEdge(Cycles cycles=Cycles(0)) constgem5::Clockedinline
ClockedObject(const ClockedObjectParams &p)gem5::ClockedObject
clockPeriod() constgem5::Clockedinline
clockPeriodUpdated()gem5::Clockedinlineprotectedvirtual
cpuSidePortsgem5::BaseXBarprotected
curCycle() constgem5::Clockedinline
currentSection()gem5::Serializablestatic
cyclegem5::Clockedmutableprivate
cyclesToTicks(Cycles c) constgem5::Clockedinline
defaultPortIDgem5::BaseXBarprotected
defaultRangegem5::BaseXBarprotected
deschedule(Event &event)gem5::EventManagerinline
deschedule(Event *event)gem5::EventManagerinline
dmDrain()gem5::Drainableprivate
dmDrainResume()gem5::Drainableprivate
drain() overridegem5::SimObjectinlinevirtual
Drainable()gem5::Drainableprotected
drainResume()gem5::Drainableinlineprotectedvirtual
drainState() constgem5::Drainableinline
EventManager(EventManager &em)gem5::EventManagerinline
EventManager(EventManager *em)gem5::EventManagerinline
EventManager(EventQueue *eq)gem5::EventManagerinline
eventqgem5::EventManagerprotected
eventQueue() constgem5::EventManagerinline
find(const char *name)gem5::SimObjectstatic
findPort(AddrRange addr_range)gem5::BaseXBarprotected
forwardLatencygem5::BaseXBarprotected
frequency() constgem5::Clockedinline
frontendLatencygem5::BaseXBarprotected
generateCheckpointOut(const std::string &cpt_dir, std::ofstream &outstream)gem5::Serializablestatic
getAddrRanges() constgem5::BaseXBarprotected
getPort(const std::string &if_name, PortID idx=InvalidPortID) overridegem5::BaseXBarvirtual
getProbeManager()gem5::SimObject
getSimObjectResolver()gem5::SimObjectstatic
getStatGroups() constgem5::statistics::Group
getStats() constgem5::statistics::Group
gotAddrRangesgem5::BaseXBarprotected
gotAllAddrRangesgem5::BaseXBarprotected
Group()=deletegem5::statistics::Group
Group(const Group &)=deletegem5::statistics::Group
Group(Group *parent, const char *name=nullptr)gem5::statistics::Group
headerLatencygem5::BaseXBarprotected
HMCController(const HMCControllerParams &p)gem5::HMCController
init()gem5::SimObjectvirtual
initState()gem5::SimObjectvirtual
loadState(CheckpointIn &cp)gem5::SimObjectvirtual
memInvalidate()gem5::SimObjectinlinevirtual
memSidePortsgem5::BaseXBarprotected
memWriteback()gem5::SimObjectinlinevirtual
mergedParentgem5::statistics::Groupprivate
mergedStatGroupsgem5::statistics::Groupprivate
mergeStatGroup(Group *block)gem5::statistics::Group
name() constgem5::Namedinlinevirtual
Named(const std::string &name_)gem5::Namedinline
nextCycle() constgem5::Clockedinline
NoncoherentXBar(const NoncoherentXBarParams &p)gem5::NoncoherentXBar
notifyFork()gem5::Drainableinlinevirtual
numMemSidePortsgem5::HMCControllerprivate
gem5::operator=(const Group &)=deletegem5::statistics::Group
gem5::Clocked::operator=(Clocked &)=deletegem5::Clockedprotected
params() constgem5::SimObjectinline
Params typedefgem5::ClockedObject
pathgem5::Serializableprivatestatic
pktCountgem5::BaseXBarprotected
pktSizegem5::BaseXBarprotected
portMapgem5::BaseXBarprotected
powerStategem5::ClockedObject
preDumpStats()gem5::statistics::Groupvirtual
probeManagergem5::SimObjectprivate
recvAtomicBackdoor(PacketPtr pkt, PortID cpu_side_port_id, MemBackdoorPtr *backdoor=nullptr)gem5::NoncoherentXBarprotected
recvFunctional(PacketPtr pkt, PortID cpu_side_port_id)gem5::NoncoherentXBarprotected
recvRangeChange(PortID mem_side_port_id)gem5::HMCControllerprivatevirtual
recvReqRetry(PortID mem_side_port_id)gem5::NoncoherentXBarprotected
recvTimingReq(PacketPtr pkt, PortID cpu_side_port_id)gem5::HMCControllerprivatevirtual
recvTimingResp(PacketPtr pkt, PortID mem_side_port_id)gem5::NoncoherentXBarprotectedvirtual
regProbeListeners()gem5::SimObjectvirtual
regProbePoints()gem5::SimObjectvirtual
regStats() overridegem5::BaseXBarvirtual
reqLayersgem5::NoncoherentXBarprotected
reschedule(Event &event, Tick when, bool always=false)gem5::EventManagerinline
reschedule(Event *event, Tick when, bool always=false)gem5::EventManagerinline
resetClock() constgem5::Clockedinlineprotected
resetStats()gem5::statistics::Groupvirtual
resolveStat(std::string name) constgem5::statistics::Group
respLayersgem5::NoncoherentXBarprotected
responseLatencygem5::BaseXBarprotected
rotate_counter()gem5::HMCControllerprivate
routeTogem5::BaseXBarprotected
rr_countergem5::HMCControllerprivate
schedule(Event &event, Tick when)gem5::EventManagerinline
schedule(Event *event, Tick when)gem5::EventManagerinline
Serializable()gem5::Serializable
serialize(CheckpointOut &cp) const overridegem5::ClockedObjectvirtual
serializeAll(const std::string &cpt_dir)gem5::SimObjectstatic
serializeSection(CheckpointOut &cp, const char *name) constgem5::Serializable
serializeSection(CheckpointOut &cp, const std::string &name) constgem5::Serializableinline
setCurTick(Tick newVal)gem5::EventManagerinline
setSimObjectResolver(SimObjectResolver *resolver)gem5::SimObjectstatic
signalDrainDone() constgem5::Drainableinlineprotected
SimObject(const Params &p)gem5::SimObject
SimObjectList typedefgem5::SimObjectprivate
simObjectListgem5::SimObjectprivatestatic
startup()gem5::SimObjectvirtual
statGroupsgem5::statistics::Groupprivate
statsgem5::statistics::Groupprivate
tickgem5::Clockedmutableprivate
ticksToCycles(Tick t) constgem5::Clockedinline
transDistgem5::BaseXBarprotected
unserialize(CheckpointIn &cp) overridegem5::ClockedObjectvirtual
unserializeSection(CheckpointIn &cp, const char *name)gem5::Serializable
unserializeSection(CheckpointIn &cp, const std::string &name)gem5::Serializableinline
update() constgem5::Clockedinlineprivate
updateClockPeriod()gem5::Clockedinline
useDefaultRangegem5::BaseXBarprotected
voltage() constgem5::Clockedinline
wakeupEventQueue(Tick when=(Tick) -1)gem5::EventManagerinline
widthgem5::BaseXBarprotected
xbarRangesgem5::BaseXBarprotected
~BaseXBar()gem5::BaseXBarvirtual
~Clocked()gem5::Clockedinlineprotectedvirtual
~Drainable()gem5::Drainableprotectedvirtual
~Group()gem5::statistics::Groupvirtual
~Named()=defaultgem5::Namedvirtual
~NoncoherentXBar()gem5::NoncoherentXBarvirtual
~Serializable()gem5::Serializablevirtual
~SimObject()gem5::SimObjectvirtual

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