HMC Controller, in general, is responsible for translating the host protocol (AXI for example) to serial links protocol. More...
#include <hmc_controller.hh>
Inheritance diagram for gem5::HMCController:
Public Member Functions | |
| HMCController (const HMCControllerParams &p) | |
 Public Member Functions inherited from gem5::NoncoherentXBar | |
| NoncoherentXBar (const NoncoherentXBarParams &p) | |
| virtual | ~NoncoherentXBar () |
| Public Member Functions inherited from gem5::BaseXBar | |
| virtual | ~BaseXBar () |
| Port & | getPort (const std::string &if_name, PortID idx=InvalidPortID) override |
| A function used to return the port associated with this object. More... | |
| void | regStats () override |
| Callback to set stat parameters. More... | |
| Public Member Functions inherited from gem5::ClockedObject | |
| ClockedObject (const ClockedObjectParams &p) | |
| void | serialize (CheckpointOut &cp) const override |
| Serialize an object. More... | |
| void | unserialize (CheckpointIn &cp) override |
| Unserialize an object. More... | |
| Public Member Functions inherited from gem5::SimObject | |
| const Params & | params () const |
| SimObject (const Params &p) | |
| virtual | ~SimObject () |
| virtual void | init () |
| init() is called after all C++ SimObjects have been created and all ports are connected. More... | |
| virtual void | loadState (CheckpointIn &cp) |
| loadState() is called on each SimObject when restoring from a checkpoint. More... | |
| virtual void | initState () |
| initState() is called on each SimObject when not restoring from a checkpoint. More... | |
| virtual void | regProbePoints () |
| Register probe points for this object. More... | |
| virtual void | regProbeListeners () |
| Register probe listeners for this object. More... | |
| ProbeManager * | getProbeManager () |
| Get the probe manager for this object. More... | |
| virtual void | startup () |
| startup() is the final initialization call before simulation. More... | |
| DrainState | drain () override |
| Provide a default implementation of the drain interface for objects that don't need draining. More... | |
| virtual void | memWriteback () |
| Write back dirty buffers to memory using functional writes. More... | |
| virtual void | memInvalidate () |
| Invalidate the contents of memory buffers. More... | |
| void | serialize (CheckpointOut &cp) const override |
| Serialize an object. More... | |
| void | unserialize (CheckpointIn &cp) override |
| Unserialize an object. More... | |
| Public Member Functions inherited from gem5::EventManager | |
| EventQueue * | eventQueue () const |
| void | schedule (Event &event, Tick when) |
| void | deschedule (Event &event) |
| void | reschedule (Event &event, Tick when, bool always=false) |
| void | schedule (Event *event, Tick when) |
| void | deschedule (Event *event) |
| void | reschedule (Event *event, Tick when, bool always=false) |
| void | wakeupEventQueue (Tick when=(Tick) -1) |
| This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers. More... | |
| void | setCurTick (Tick newVal) |
| EventManager (EventManager &em) | |
| Event manger manages events in the event queue. More... | |
| EventManager (EventManager *em) | |
| EventManager (EventQueue *eq) | |
| Public Member Functions inherited from gem5::Serializable | |
| Serializable () | |
| virtual | ~Serializable () |
| void | serializeSection (CheckpointOut &cp, const char *name) const |
| Serialize an object into a new section. More... | |
| void | serializeSection (CheckpointOut &cp, const std::string &name) const |
| void | unserializeSection (CheckpointIn &cp, const char *name) |
| Unserialize an a child object. More... | |
| void | unserializeSection (CheckpointIn &cp, const std::string &name) |
| Public Member Functions inherited from gem5::Drainable | |
| DrainState | drainState () const |
| Return the current drain state of an object. More... | |
| virtual void | notifyFork () |
| Notify a child process of a fork. More... | |
| Public Member Functions inherited from gem5::statistics::Group | |
| Group (Group *parent, const char *name=nullptr) | |
| Construct a new statistics group. More... | |
| virtual | ~Group () |
| virtual void | resetStats () |
| Callback to reset stats. More... | |
| virtual void | preDumpStats () |
| Callback before stats are dumped. More... | |
| void | addStat (statistics::Info *info) |
| Register a stat with this group. More... | |
| const std::map< std::string, Group * > & | getStatGroups () const |
| Get all child groups associated with this object. More... | |
| const std::vector< Info * > & | getStats () const |
| Get all stats associated with this object. More... | |
| void | addStatGroup (const char *name, Group *block) |
| Add a stat block as a child of this block. More... | |
| const Info * | resolveStat (std::string name) const |
| Resolve a stat by its name within this group. More... | |
| void | mergeStatGroup (Group *block) |
| Merge the contents (stats & children) of a block to this block. More... | |
| Group ()=delete | |
| Group (const Group &)=delete | |
| Group & | operator= (const Group &)=delete |
| Public Member Functions inherited from gem5::Named | |
| Named (const std::string &name_) | |
| virtual | ~Named ()=default |
| virtual std::string | name () const |
| Public Member Functions inherited from gem5::Clocked | |
| void | updateClockPeriod () |
| Update the tick to the current tick. More... | |
| Tick | clockEdge (Cycles cycles=Cycles(0)) const |
| Determine the tick when a cycle begins, by default the current one, but the argument also enables the caller to determine a future cycle. More... | |
| Cycles | curCycle () const |
| Determine the current cycle, corresponding to a tick aligned to a clock edge. More... | |
| Tick | nextCycle () const |
| Based on the clock of the object, determine the start tick of the first cycle that is at least one cycle in the future. More... | |
| uint64_t | frequency () const |
| Tick | clockPeriod () const |
| double | voltage () const |
| Cycles | ticksToCycles (Tick t) const |
| Tick | cyclesToTicks (Cycles c) const |
Private Member Functions | |
| virtual void | recvRangeChange (PortID mem_side_port_id) |
| Function called by the port when the crossbar is recieving a range change. More... | |
| virtual bool | recvTimingReq (PacketPtr pkt, PortID cpu_side_port_id) |
| int | rotate_counter () |
| Function for rotating the round robin counter. More... | |
Private Attributes | |
| int | numMemSidePorts |
| int | rr_counter |
Additional Inherited Members | |
| Public Types inherited from gem5::ClockedObject | |
| using | Params = ClockedObjectParams |
| Parameters of ClockedObject. More... | |
| Public Types inherited from gem5::SimObject | |
| typedef SimObjectParams | Params |
| Static Public Member Functions inherited from gem5::SimObject | |
| static void | serializeAll (const std::string &cpt_dir) |
| Create a checkpoint by serializing all SimObjects in the system. More... | |
| static SimObject * | find (const char *name) |
| Find the SimObject with the given name and return a pointer to it. More... | |
| static void | setSimObjectResolver (SimObjectResolver *resolver) |
| There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More... | |
| static SimObjectResolver * | getSimObjectResolver () |
| There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More... | |
| Static Public Member Functions inherited from gem5::Serializable | |
| static const std::string & | currentSection () |
| Gets the fully-qualified name of the active section. More... | |
| static void | generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream) |
| Generate a checkpoint file so that the serialization can be routed to it. More... | |
| Public Attributes inherited from gem5::ClockedObject | |
| PowerState * | powerState |
| Protected Member Functions inherited from gem5::NoncoherentXBar | |
| virtual bool | recvTimingResp (PacketPtr pkt, PortID mem_side_port_id) |
| void | recvReqRetry (PortID mem_side_port_id) |
| Tick | recvAtomicBackdoor (PacketPtr pkt, PortID cpu_side_port_id, MemBackdoorPtr *backdoor=nullptr) |
| void | recvFunctional (PacketPtr pkt, PortID cpu_side_port_id) |
| Protected Member Functions inherited from gem5::BaseXBar | |
| PortID | findPort (AddrRange addr_range) |
| Find which port connected to this crossbar (if any) should be given a packet with this address range. More... | |
| AddrRangeList | getAddrRanges () const |
| Return the address ranges the crossbar is responsible for. More... | |
| void | calcPacketTiming (PacketPtr pkt, Tick header_delay) |
| Calculate the timing parameters for the packet. More... | |
| BaseXBar (const BaseXBarParams &p) | |
| Protected Member Functions inherited from gem5::Drainable | |
| Drainable () | |
| virtual | ~Drainable () |
| virtual void | drainResume () |
| Resume execution after a successful drain. More... | |
| void | signalDrainDone () const |
| Signal that an object is drained. More... | |
| Protected Member Functions inherited from gem5::Clocked | |
| Clocked (ClockDomain &clk_domain) | |
| Create a clocked object and set the clock domain based on the parameters. More... | |
| Clocked (Clocked &)=delete | |
| Clocked & | operator= (Clocked &)=delete |
| virtual | ~Clocked () |
| Virtual destructor due to inheritance. More... | |
| void | resetClock () const |
| Reset the object's clock using the current global tick value. More... | |
| virtual void | clockPeriodUpdated () |
| A hook subclasses can implement so they can do any extra work that's needed when the clock rate is changed. More... | |
| Protected Attributes inherited from gem5::NoncoherentXBar | |
| std::vector< ReqLayer * > | reqLayers |
| Declare the layers of this crossbar, one vector for requests and one for responses. More... | |
| std::vector< RespLayer * > | respLayers |
| Protected Attributes inherited from gem5::BaseXBar | |
| const Cycles | frontendLatency |
| Cycles of front-end pipeline including the delay to accept the request and to decode the address. More... | |
| const Cycles | forwardLatency |
| const Cycles | responseLatency |
| const Cycles | headerLatency |
| Cycles the layer is occupied processing the packet header. More... | |
| const uint32_t | width |
| the width of the xbar in bytes More... | |
| AddrRangeMap< PortID, 3 > | portMap |
| std::unordered_map< RequestPtr, PortID > | routeTo |
| Remember where request packets came from so that we can route responses to the appropriate port. More... | |
| AddrRangeList | xbarRanges |
| all contigous ranges seen by this crossbar More... | |
| AddrRange | defaultRange |
| std::vector< bool > | gotAddrRanges |
| Remember for each of the memory-side ports of the crossbar if we got an address range from the connected CPU-side ports. More... | |
| bool | gotAllAddrRanges |
| std::vector< QueuedResponsePort * > | cpuSidePorts |
| The memory-side ports and CPU-side ports of the crossbar. More... | |
| std::vector< RequestPort * > | memSidePorts |
| PortID | defaultPortID |
| Port that handles requests that don't match any of the interfaces. More... | |
| const bool | useDefaultRange |
| If true, use address range provided by default device. More... | |
| statistics::Vector | transDist |
| Stats for transaction distribution and data passing through the crossbar. More... | |
| statistics::Vector2d | pktCount |
| statistics::Vector2d | pktSize |
| Protected Attributes inherited from gem5::SimObject | |
| const SimObjectParams & | _params |
| Cached copy of the object parameters. More... | |
| Protected Attributes inherited from gem5::EventManager | |
| EventQueue * | eventq |
| A pointer to this object's event queue. More... | |
Detailed Description
HMC Controller, in general, is responsible for translating the host protocol (AXI for example) to serial links protocol.
Plus, it should have large internal buffers to hide the access latency of the cube. It is also inferred from the standard [1] and the literature [2] that serial links share the same address range and packets can travel over any of them, so a load distribution mechanism is required. This model simply queues the incoming transactions (using a Bridge) and schedules them to the serial links using a simple round robin mechanism to balance the load among them. More advanced global scheduling policies and reordering and steering of transactions can be added to this model if required [3]. [1] http://www.hybridmemorycube.org/specification-download/ [2] Low-Power Hybrid Memory Cubes With Link Power Manageme and Two-Level Prefetching (J. Ahn et. al) [3] The Open-Silicon HMC Controller IP http://www.open-silicon.com/open-silicon-ips/hmc/
Definition at line 76 of file hmc_controller.hh.
Constructor & Destructor Documentation
◆ HMCController()
| gem5::HMCController::HMCController | ( | const HMCControllerParams & | p | ) |
Definition at line 10 of file hmc_controller.cc.
References gem5::VegaISA::p.
Member Function Documentation
◆ recvRangeChange()
|
privatevirtual |
Function called by the port when the crossbar is recieving a range change.
Function called by the port when the crossbar is receiving a range change.
- Parameters
-
mem_side_port_id id of the port that received the change
Reimplemented from gem5::BaseXBar.
Definition at line 20 of file hmc_controller.cc.
References gem5::BaseXBar::gotAddrRanges, gem5::BaseXBar::gotAllAddrRanges, and gem5::BaseXBar::recvRangeChange().
◆ recvTimingReq()
Reimplemented from gem5::NoncoherentXBar.
Definition at line 40 of file hmc_controller.cc.
References gem5::Packet::cacheResponding(), gem5::BaseXBar::calcPacketTiming(), gem5::Clocked::clockEdge(), gem5::Clocked::clockPeriod(), gem5::Packet::cmdString(), gem5::Packet::cmdToIndex(), gem5::BaseXBar::cpuSidePorts, DPRINTF, gem5::BaseXBar::forwardLatency, gem5::BaseXBar::frontendLatency, gem5::Packet::getAddr(), gem5::Packet::getSize(), gem5::Packet::hasData(), gem5::Packet::headerDelay, gem5::Packet::isExpressSnoop(), gem5::BaseXBar::memSidePorts, gem5::Port::name(), gem5::Packet::needsResponse(), gem5::Packet::payloadDelay, gem5::BaseXBar::pktCount, gem5::BaseXBar::pktSize, gem5::Packet::req, gem5::NoncoherentXBar::reqLayers, rotate_counter(), gem5::BaseXBar::routeTo, and gem5::BaseXBar::transDist.
◆ rotate_counter()
|
private |
Function for rotating the round robin counter.
- Returns
- the next value of the counter
Definition at line 31 of file hmc_controller.cc.
References numMemSidePorts, and rr_counter.
Referenced by recvTimingReq().
Member Data Documentation
◆ numMemSidePorts
|
private |
Definition at line 93 of file hmc_controller.hh.
Referenced by rotate_counter().
◆ rr_counter
|
private |
Definition at line 96 of file hmc_controller.hh.
Referenced by rotate_counter().
The documentation for this class was generated from the following files:
- mem/hmc_controller.hh
- mem/hmc_controller.cc