gem5  v21.2.1.1
gem5::HSAPacketProcessor Member List

This is the complete list of members for gem5::HSAPacketProcessor, including all inherited members.

_drainManagergem5::Drainableprivate
_drainStategem5::Drainablemutableprivate
_namegem5::Namedprivate
_objNameResolvergem5::SimObjectprivatestatic
_paramsgem5::SimObjectprotected
addStat(statistics::Info *info)gem5::statistics::Group
addStatGroup(const char *name, Group *block)gem5::statistics::Group
cacheBlockSize() constgem5::DmaDeviceinline
clockDomaingem5::Clockedprivate
Clocked(ClockDomain &clk_domain)gem5::Clockedinlineprotected
Clocked(Clocked &)=deletegem5::Clockedprotected
clockEdge(Cycles cycles=Cycles(0)) constgem5::Clockedinline
ClockedObject(const ClockedObjectParams &p)gem5::ClockedObject
clockPeriod() constgem5::Clockedinline
clockPeriodUpdated()gem5::Clockedinlineprotectedvirtual
cmdQueueCmdDma(HSAPacketProcessor *hsaPP, int pid, bool isRead, uint32_t ix_start, unsigned num_pkts, dma_series_ctx *series_ctx, void *dest_4debug)gem5::HSAPacketProcessor
curCycle() constgem5::Clockedinline
currentSection()gem5::Serializablestatic
cyclegem5::Clockedmutableprivate
cyclesToTicks(Cycles c) constgem5::Clockedinline
deschedule(Event &event)gem5::EventManagerinline
deschedule(Event *event)gem5::EventManagerinline
displayQueueDescriptor(int pid, uint32_t rl_idx)gem5::HSAPacketProcessorprotected
DmaDevice(const Params &p)gem5::DmaDevice
DmaFnPtr typedefgem5::HSAPacketProcessorprotected
dmaPending() constgem5::DmaDeviceinline
dmaPortgem5::DmaDeviceprotected
dmaRead(Addr addr, int size, Event *event, uint8_t *data, uint32_t sid, uint32_t ssid, Tick delay=0)gem5::DmaDeviceinline
dmaRead(Addr addr, int size, Event *event, uint8_t *data, Tick delay=0)gem5::DmaDeviceinline
dmaReadVirt(Addr host_addr, unsigned size, DmaCallback *cb, void *data, Tick delay=0)gem5::DmaVirtDevice
dmaVirt(DmaFnPtr dmaFn, Addr host_addr, unsigned size, DmaCallback *cb, void *data, Tick delay=0)gem5::DmaVirtDevice
DmaVirtDevice(const Params &p)gem5::DmaVirtDeviceinline
dmaWrite(Addr addr, int size, Event *event, uint8_t *data, uint32_t sid, uint32_t ssid, Tick delay=0)gem5::DmaDeviceinline
dmaWrite(Addr addr, int size, Event *event, uint8_t *data, Tick delay=0)gem5::DmaDeviceinline
dmaWriteVirt(Addr host_addr, unsigned size, DmaCallback *b, void *data, Tick delay=0)gem5::DmaVirtDevice
dmDrain()gem5::Drainableprivate
dmDrainResume()gem5::Drainableprivate
drain() overridegem5::SimObjectinlinevirtual
Drainable()gem5::Drainableprotected
drainResume()gem5::Drainableinlineprotectedvirtual
drainState() constgem5::Drainableinline
EventManager(EventManager &em)gem5::EventManagerinline
EventManager(EventManager *em)gem5::EventManagerinline
EventManager(EventQueue *eq)gem5::EventManagerinline
eventqgem5::EventManagerprotected
eventQueue() constgem5::EventManagerinline
find(const char *name)gem5::SimObjectstatic
finishPkt(void *pkt, uint32_t rl_idx)gem5::HSAPacketProcessor
finishPkt(void *pkt)gem5::HSAPacketProcessorinline
frequency() constgem5::Clockedinline
generateCheckpointOut(const std::string &cpt_dir, std::ofstream &outstream)gem5::Serializablestatic
getAddrRanges() const overridegem5::HSAPacketProcessorvirtual
getCommandsFromHost(int pid, uint32_t rl_idx)gem5::HSAPacketProcessor
getPort(const std::string &if_name, PortID idx=InvalidPortID) overridegem5::DmaDevicevirtual
getProbeManager()gem5::SimObject
getQueueDesc(uint32_t queId)gem5::HSAPacketProcessorinline
getRegdListEntry(uint32_t queId)gem5::HSAPacketProcessorinline
getSimObjectResolver()gem5::SimObjectstatic
getStatGroups() constgem5::statistics::Group
getStats() constgem5::statistics::Group
gpu_devicegem5::HSAPacketProcessorprotected
Group()=deletegem5::statistics::Group
Group(const Group &)=deletegem5::statistics::Group
Group(Group *parent, const char *name=nullptr)gem5::statistics::Group
handleReadDMA()gem5::HSAPacketProcessor
HSAPacketProcessor(const Params &p)gem5::HSAPacketProcessor
hwSchdlrgem5::HSAPacketProcessorprotected
HWScheduler classgem5::HSAPacketProcessorfriend
inFlightPkts(uint32_t queId)gem5::HSAPacketProcessorinline
init() overridegem5::DmaDevicevirtual
initState()gem5::SimObjectvirtual
loadState(CheckpointIn &cp)gem5::SimObjectvirtual
memInvalidate()gem5::SimObjectinlinevirtual
memWriteback()gem5::SimObjectinlinevirtual
mergedParentgem5::statistics::Groupprivate
mergedStatGroupsgem5::statistics::Groupprivate
mergeStatGroup(Group *block)gem5::statistics::Group
name() constgem5::Namedinlinevirtual
Named(const std::string &name_)gem5::Namedinline
nextCycle() constgem5::Clockedinline
notifyFork()gem5::Drainableinlinevirtual
numHWQueuesgem5::HSAPacketProcessor
gem5::operator=(const Group &)=deletegem5::statistics::Group
gem5::Clocked::operator=(Clocked &)=deletegem5::Clockedprotected
params() constgem5::SimObjectinline
Params typedefgem5::HSAPacketProcessor
pathgem5::Serializableprivatestatic
pioAddrgem5::HSAPacketProcessor
pioDelaygem5::HSAPacketProcessor
PioDevice(const Params &p)gem5::PioDevice
pioPortgem5::PioDeviceprotected
pioSizegem5::HSAPacketProcessor
pktProcessDelaygem5::HSAPacketProcessor
powerStategem5::ClockedObject
preDumpStats()gem5::statistics::Groupvirtual
probeManagergem5::SimObjectprivate
processPkt(void *pkt, uint32_t rl_idx, Addr host_pkt_addr)gem5::HSAPacketProcessorprotected
read(Packet *) overridegem5::HSAPacketProcessorvirtual
gem5::DmaVirtDevice::read(PacketPtr pkt)=0gem5::PioDeviceprotectedpure virtual
regdQListgem5::HSAPacketProcessorprotected
regProbeListeners()gem5::SimObjectvirtual
regProbePoints()gem5::SimObjectvirtual
regStats()gem5::statistics::Groupvirtual
reschedule(Event &event, Tick when, bool always=false)gem5::EventManagerinline
reschedule(Event *event, Tick when, bool always=false)gem5::EventManagerinline
resetClock() constgem5::Clockedinlineprotected
resetStats()gem5::statistics::Groupvirtual
resolveStat(std::string name) constgem5::statistics::Group
schedAQLProcessing(uint32_t rl_idx)gem5::HSAPacketProcessor
schedAQLProcessing(uint32_t rl_idx, Tick delay)gem5::HSAPacketProcessor
schedule(Event &event, Tick when)gem5::EventManagerinline
schedule(Event *event, Tick when)gem5::EventManagerinline
sendAgentDispatchCompletionSignal(void *pkt, hsa_signal_value_t signal)gem5::HSAPacketProcessor
sendCompletionSignal(hsa_signal_value_t signal)gem5::HSAPacketProcessor
Serializable()gem5::Serializable
serialize(CheckpointOut &cp) const overridegem5::ClockedObjectvirtual
serializeAll(const std::string &cpt_dir)gem5::SimObjectstatic
serializeSection(CheckpointOut &cp, const char *name) constgem5::Serializable
serializeSection(CheckpointOut &cp, const std::string &name) constgem5::Serializableinline
setCurTick(Tick newVal)gem5::EventManagerinline
setDevice(GPUCommandProcessor *dev)gem5::HSAPacketProcessor
setDeviceQueueDesc(uint64_t hostReadIndexPointer, uint64_t basePointer, uint64_t queue_id, uint32_t size, int doorbellSize, GfxVersion gfxVersion)gem5::HSAPacketProcessor
setSimObjectResolver(SimObjectResolver *resolver)gem5::SimObjectstatic
signalDrainDone() constgem5::Drainableinlineprotected
SimObject(const Params &p)gem5::SimObject
SimObjectList typedefgem5::SimObjectprivate
simObjectListgem5::SimObjectprivatestatic
startup()gem5::SimObjectvirtual
statGroupsgem5::statistics::Groupprivate
statsgem5::statistics::Groupprivate
sysgem5::PioDeviceprotected
tickgem5::Clockedmutableprivate
ticksToCycles(Tick t) constgem5::Clockedinline
translate(Addr vaddr, Addr size) overridegem5::HSAPacketProcessorvirtual
unserialize(CheckpointIn &cp) overridegem5::ClockedObjectvirtual
unserializeSection(CheckpointIn &cp, const char *name)gem5::Serializable
unserializeSection(CheckpointIn &cp, const std::string &name)gem5::Serializableinline
unsetDeviceQueueDesc(uint64_t queue_id, int doorbellSize)gem5::HSAPacketProcessor
update() constgem5::Clockedinlineprivate
updateClockPeriod()gem5::Clockedinline
updateReadDispIdDma()gem5::HSAPacketProcessor
updateReadIndex(int, uint32_t)gem5::HSAPacketProcessor
voltage() constgem5::Clockedinline
wakeupEventQueue(Tick when=(Tick) -1)gem5::EventManagerinline
write(Packet *) overridegem5::HSAPacketProcessorvirtual
gem5::DmaVirtDevice::write(PacketPtr pkt)=0gem5::PioDeviceprotectedpure virtual
~Clocked()gem5::Clockedinlineprotectedvirtual
~DmaDevice()=defaultgem5::DmaDevicevirtual
~DmaVirtDevice()gem5::DmaVirtDeviceinlinevirtual
~Drainable()gem5::Drainableprotectedvirtual
~Group()gem5::statistics::Groupvirtual
~HSAPacketProcessor()gem5::HSAPacketProcessor
~Named()=defaultgem5::Namedvirtual
~PioDevice()gem5::PioDevicevirtual
~Serializable()gem5::Serializablevirtual
~SimObject()gem5::SimObjectvirtual

Generated on Wed May 4 2022 12:14:38 for gem5 by doxygen 1.8.17