| _drainManager | gem5::Drainable | private |
| _drainState | gem5::Drainable | mutableprivate |
| _name | gem5::Named | private |
| _objNameResolver | gem5::SimObject | privatestatic |
| _params | gem5::SimObject | protected |
| addStat(statistics::Info *info) | gem5::statistics::Group | |
| addStatGroup(const char *name, Group *block) | gem5::statistics::Group | |
| cacheBlockSize() const | gem5::DmaDevice | inline |
| clockDomain | gem5::Clocked | private |
| Clocked(ClockDomain &clk_domain) | gem5::Clocked | inlineprotected |
| Clocked(Clocked &)=delete | gem5::Clocked | protected |
| clockEdge(Cycles cycles=Cycles(0)) const | gem5::Clocked | inline |
| ClockedObject(const ClockedObjectParams &p) | gem5::ClockedObject | |
| clockPeriod() const | gem5::Clocked | inline |
| clockPeriodUpdated() | gem5::Clocked | inlineprotectedvirtual |
| cmdQueueCmdDma(HSAPacketProcessor *hsaPP, int pid, bool isRead, uint32_t ix_start, unsigned num_pkts, dma_series_ctx *series_ctx, void *dest_4debug) | gem5::HSAPacketProcessor | |
| curCycle() const | gem5::Clocked | inline |
| currentSection() | gem5::Serializable | static |
| cycle | gem5::Clocked | mutableprivate |
| cyclesToTicks(Cycles c) const | gem5::Clocked | inline |
| deschedule(Event &event) | gem5::EventManager | inline |
| deschedule(Event *event) | gem5::EventManager | inline |
| displayQueueDescriptor(int pid, uint32_t rl_idx) | gem5::HSAPacketProcessor | protected |
| DmaDevice(const Params &p) | gem5::DmaDevice | |
| DmaFnPtr typedef | gem5::HSAPacketProcessor | protected |
| dmaPending() const | gem5::DmaDevice | inline |
| dmaPort | gem5::DmaDevice | protected |
| dmaRead(Addr addr, int size, Event *event, uint8_t *data, uint32_t sid, uint32_t ssid, Tick delay=0) | gem5::DmaDevice | inline |
| dmaRead(Addr addr, int size, Event *event, uint8_t *data, Tick delay=0) | gem5::DmaDevice | inline |
| dmaReadVirt(Addr host_addr, unsigned size, DmaCallback *cb, void *data, Tick delay=0) | gem5::DmaVirtDevice | |
| dmaVirt(DmaFnPtr dmaFn, Addr host_addr, unsigned size, DmaCallback *cb, void *data, Tick delay=0) | gem5::DmaVirtDevice | |
| DmaVirtDevice(const Params &p) | gem5::DmaVirtDevice | inline |
| dmaWrite(Addr addr, int size, Event *event, uint8_t *data, uint32_t sid, uint32_t ssid, Tick delay=0) | gem5::DmaDevice | inline |
| dmaWrite(Addr addr, int size, Event *event, uint8_t *data, Tick delay=0) | gem5::DmaDevice | inline |
| dmaWriteVirt(Addr host_addr, unsigned size, DmaCallback *b, void *data, Tick delay=0) | gem5::DmaVirtDevice | |
| dmDrain() | gem5::Drainable | private |
| dmDrainResume() | gem5::Drainable | private |
| drain() override | gem5::SimObject | inlinevirtual |
| Drainable() | gem5::Drainable | protected |
| drainResume() | gem5::Drainable | inlineprotectedvirtual |
| drainState() const | gem5::Drainable | inline |
| EventManager(EventManager &em) | gem5::EventManager | inline |
| EventManager(EventManager *em) | gem5::EventManager | inline |
| EventManager(EventQueue *eq) | gem5::EventManager | inline |
| eventq | gem5::EventManager | protected |
| eventQueue() const | gem5::EventManager | inline |
| find(const char *name) | gem5::SimObject | static |
| finishPkt(void *pkt, uint32_t rl_idx) | gem5::HSAPacketProcessor | |
| finishPkt(void *pkt) | gem5::HSAPacketProcessor | inline |
| frequency() const | gem5::Clocked | inline |
| generateCheckpointOut(const std::string &cpt_dir, std::ofstream &outstream) | gem5::Serializable | static |
| getAddrRanges() const override | gem5::HSAPacketProcessor | virtual |
| getCommandsFromHost(int pid, uint32_t rl_idx) | gem5::HSAPacketProcessor | |
| getPort(const std::string &if_name, PortID idx=InvalidPortID) override | gem5::DmaDevice | virtual |
| getProbeManager() | gem5::SimObject | |
| getQueueDesc(uint32_t queId) | gem5::HSAPacketProcessor | inline |
| getRegdListEntry(uint32_t queId) | gem5::HSAPacketProcessor | inline |
| getSimObjectResolver() | gem5::SimObject | static |
| getStatGroups() const | gem5::statistics::Group | |
| getStats() const | gem5::statistics::Group | |
| gpu_device | gem5::HSAPacketProcessor | protected |
| gpuDevice | gem5::HSAPacketProcessor | protected |
| Group()=delete | gem5::statistics::Group | |
| Group(const Group &)=delete | gem5::statistics::Group | |
| Group(Group *parent, const char *name=nullptr) | gem5::statistics::Group | |
| handleReadDMA() | gem5::HSAPacketProcessor | |
| HSAPacketProcessor(const Params &p) | gem5::HSAPacketProcessor | |
| hwSchdlr | gem5::HSAPacketProcessor | protected |
| HWScheduler class | gem5::HSAPacketProcessor | friend |
| hwScheduler() | gem5::HSAPacketProcessor | inline |
| inFlightPkts(uint32_t queId) | gem5::HSAPacketProcessor | inline |
| init() override | gem5::DmaDevice | virtual |
| initState() | gem5::SimObject | virtual |
| loadState(CheckpointIn &cp) | gem5::SimObject | virtual |
| memInvalidate() | gem5::SimObject | inlinevirtual |
| memWriteback() | gem5::SimObject | inlinevirtual |
| mergedParent | gem5::statistics::Group | private |
| mergedStatGroups | gem5::statistics::Group | private |
| mergeStatGroup(Group *block) | gem5::statistics::Group | |
| name() const | gem5::Named | inlinevirtual |
| Named(const std::string &name_) | gem5::Named | inline |
| nextCycle() const | gem5::Clocked | inline |
| notifyFork() | gem5::Drainable | inlinevirtual |
| numHWQueues | gem5::HSAPacketProcessor | |
| gem5::operator=(const Group &)=delete | gem5::statistics::Group | |
| gem5::Clocked::operator=(Clocked &)=delete | gem5::Clocked | protected |
| Params typedef | gem5::HSAPacketProcessor | |
| params() const | gem5::SimObject | inline |
| path | gem5::Serializable | privatestatic |
| pioAddr | gem5::HSAPacketProcessor | |
| pioDelay | gem5::HSAPacketProcessor | |
| PioDevice(const Params &p) | gem5::PioDevice | |
| pioPort | gem5::PioDevice | protected |
| pioSize | gem5::HSAPacketProcessor | |
| pktProcessDelay | gem5::HSAPacketProcessor | |
| powerState | gem5::ClockedObject | |
| preDumpStats() | gem5::statistics::Group | virtual |
| probeManager | gem5::SimObject | private |
| processPkt(void *pkt, uint32_t rl_idx, Addr host_pkt_addr) | gem5::HSAPacketProcessor | protected |
| read(Packet *) override | gem5::HSAPacketProcessor | virtual |
| gem5::DmaVirtDevice::read(PacketPtr pkt)=0 | gem5::PioDevice | protectedpure virtual |
| regdQList | gem5::HSAPacketProcessor | protected |
| regProbeListeners() | gem5::SimObject | virtual |
| regProbePoints() | gem5::SimObject | virtual |
| regStats() | gem5::statistics::Group | virtual |
| reschedule(Event &event, Tick when, bool always=false) | gem5::EventManager | inline |
| reschedule(Event *event, Tick when, bool always=false) | gem5::EventManager | inline |
| resetClock() const | gem5::Clocked | inlineprotected |
| resetStats() | gem5::statistics::Group | virtual |
| resolveStat(std::string name) const | gem5::statistics::Group | |
| schedAQLProcessing(uint32_t rl_idx) | gem5::HSAPacketProcessor | |
| schedAQLProcessing(uint32_t rl_idx, Tick delay) | gem5::HSAPacketProcessor | |
| schedule(Event &event, Tick when) | gem5::EventManager | inline |
| schedule(Event *event, Tick when) | gem5::EventManager | inline |
| sendAgentDispatchCompletionSignal(void *pkt, hsa_signal_value_t signal) | gem5::HSAPacketProcessor | |
| sendCompletionSignal(hsa_signal_value_t signal) | gem5::HSAPacketProcessor | |
| Serializable() | gem5::Serializable | |
| serialize(CheckpointOut &cp) const override | gem5::ClockedObject | virtual |
| serializeAll(const std::string &cpt_dir) | gem5::SimObject | static |
| serializeSection(CheckpointOut &cp, const char *name) const | gem5::Serializable | |
| serializeSection(CheckpointOut &cp, const std::string &name) const | gem5::Serializable | inline |
| setCurTick(Tick newVal) | gem5::EventManager | inline |
| setDevice(GPUCommandProcessor *dev) | gem5::HSAPacketProcessor | |
| setDeviceQueueDesc(uint64_t hostReadIndexPointer, uint64_t basePointer, uint64_t queue_id, uint32_t size, int doorbellSize, GfxVersion gfxVersion, Addr offset=0, uint64_t rd_idx=0) | gem5::HSAPacketProcessor | |
| setGPUDevice(AMDGPUDevice *gpu_device) | gem5::HSAPacketProcessor | |
| setSimObjectResolver(SimObjectResolver *resolver) | gem5::SimObject | static |
| signalDrainDone() const | gem5::Drainable | inlineprotected |
| SimObject(const Params &p) | gem5::SimObject | |
| SimObjectList typedef | gem5::SimObject | private |
| simObjectList | gem5::SimObject | privatestatic |
| startup() | gem5::SimObject | virtual |
| statGroups | gem5::statistics::Group | private |
| stats | gem5::statistics::Group | private |
| sys | gem5::PioDevice | protected |
| tick | gem5::Clocked | mutableprivate |
| ticksToCycles(Tick t) const | gem5::Clocked | inline |
| translate(Addr vaddr, Addr size) override | gem5::HSAPacketProcessor | virtual |
| unserialize(CheckpointIn &cp) override | gem5::ClockedObject | virtual |
| unserializeSection(CheckpointIn &cp, const char *name) | gem5::Serializable | |
| unserializeSection(CheckpointIn &cp, const std::string &name) | gem5::Serializable | inline |
| unsetDeviceQueueDesc(uint64_t queue_id, int doorbellSize) | gem5::HSAPacketProcessor | |
| update() const | gem5::Clocked | inlineprivate |
| updateClockPeriod() | gem5::Clocked | inline |
| updateReadDispIdDma() | gem5::HSAPacketProcessor | |
| updateReadIndex(int, uint32_t) | gem5::HSAPacketProcessor | |
| voltage() const | gem5::Clocked | inline |
| wakeupEventQueue(Tick when=(Tick) -1) | gem5::EventManager | inline |
| walker | gem5::HSAPacketProcessor | protected |
| write(Packet *) override | gem5::HSAPacketProcessor | virtual |
| gem5::DmaVirtDevice::write(PacketPtr pkt)=0 | gem5::PioDevice | protectedpure virtual |
| ~Clocked() | gem5::Clocked | inlineprotectedvirtual |
| ~DmaDevice()=default | gem5::DmaDevice | virtual |
| ~DmaVirtDevice() | gem5::DmaVirtDevice | inlinevirtual |
| ~Drainable() | gem5::Drainable | protectedvirtual |
| ~Group() | gem5::statistics::Group | virtual |
| ~HSAPacketProcessor() | gem5::HSAPacketProcessor | |
| ~Named()=default | gem5::Named | virtual |
| ~PioDevice() | gem5::PioDevice | virtual |
| ~Serializable() | gem5::Serializable | virtual |
| ~SimObject() | gem5::SimObject | virtual |