#include <hsa_packet_processor.hh>

Inheritance diagram for gem5::HSAPacketProcessor:

Classes
struct	dma_series_ctx
	Calls getCurrentEntry once the queueEntry has been dmaRead. More...

class	QueueProcessEvent

class	RQLEntry

class	SignalState

Public Types
typedef HSAPacketProcessorParams	Params

Public Types inherited from gem5::DmaVirtDevice
typedef void(DmaDevice::*	DmaFnPtr) (Addr, int, Event , uint8_t , Tick)

Public Types inherited from gem5::DmaDevice
typedef DmaDeviceParams	Params

Public Types inherited from gem5::PioDevice
using	Params = PioDeviceParams

Public Types inherited from gem5::ClockedObject
using	Params = ClockedObjectParams
	Parameters of ClockedObject. More...

Public Types inherited from gem5::SimObject
typedef SimObjectParams	Params

Public Member Functions
HSAQueueDescriptor *	getQueueDesc (uint32_t queId)

class RQLEntry *	getRegdListEntry (uint32_t queId)

uint64_t	inFlightPkts (uint32_t queId)

	HSAPacketProcessor (const Params &p)

	~HSAPacketProcessor ()

TranslationGenPtr	translate (Addr vaddr, Addr size) override
	Function used to translate a range of addresses from virtual to physical addresses. More...

void	setDeviceQueueDesc (uint64_t hostReadIndexPointer, uint64_t basePointer, uint64_t queue_id, uint32_t size, int doorbellSize, GfxVersion gfxVersion, Addr offset=0, uint64_t rd_idx=0)

void	unsetDeviceQueueDesc (uint64_t queue_id, int doorbellSize)

void	setDevice (GPUCommandProcessor *dev)

void	setGPUDevice (AMDGPUDevice *gpu_device)

void	updateReadIndex (int, uint32_t)

void	getCommandsFromHost (int pid, uint32_t rl_idx)

HWScheduler *	hwScheduler ()

virtual Tick	read (Packet *) override

virtual Tick	write (Packet *) override

virtual AddrRangeList	getAddrRanges () const override
	Every PIO device is obliged to provide an implementation that returns the address ranges the device responds to. More...

void	finishPkt (void *pkt, uint32_t rl_idx)

void	finishPkt (void *pkt)

void	schedAQLProcessing (uint32_t rl_idx)

void	schedAQLProcessing (uint32_t rl_idx, Tick delay)

void	sendAgentDispatchCompletionSignal (void *pkt, hsa_signal_value_t signal)

void	sendCompletionSignal (hsa_signal_value_t signal)

void	updateReadDispIdDma ()
	this event is used to update the read_disp_id field (the read pointer) of the MQD, which is how the host code knows the status of the HQD's read pointer More...

void	cmdQueueCmdDma (HSAPacketProcessor hsaPP, int pid, bool isRead, uint32_t ix_start, unsigned num_pkts, dma_series_ctx series_ctx, void *dest_4debug)

void	handleReadDMA ()

Public Member Functions inherited from gem5::DmaVirtDevice
	DmaVirtDevice (const Params &p)

virtual	~DmaVirtDevice ()

void	dmaReadVirt (Addr host_addr, unsigned size, DmaCallback cb, void data, Tick delay=0)
	Initiate a DMA read from virtual address host_addr. More...

void	dmaWriteVirt (Addr host_addr, unsigned size, DmaCallback b, void data, Tick delay=0)
	Initiate a DMA write from virtual address host_addr. More...

void	dmaVirt (DmaFnPtr dmaFn, Addr host_addr, unsigned size, DmaCallback cb, void data, Tick delay=0)
	Initiate a call to DmaDevice using DmaFnPtr do a DMA starting from virtual address host_addr for size number of bytes on the data. More...

Public Member Functions inherited from gem5::DmaDevice
	DmaDevice (const Params &p)

virtual	~DmaDevice ()=default

void	dmaWrite (Addr addr, int size, Event event, uint8_t data, uint32_t sid, uint32_t ssid, Tick delay=0)

void	dmaWrite (Addr addr, int size, Event event, uint8_t data, Tick delay=0)

void	dmaRead (Addr addr, int size, Event event, uint8_t data, uint32_t sid, uint32_t ssid, Tick delay=0)

void	dmaRead (Addr addr, int size, Event event, uint8_t data, Tick delay=0)

bool	dmaPending () const

void	init () override
	init() is called after all C++ SimObjects have been created and all ports are connected. More...

unsigned int	cacheBlockSize () const

Port &	getPort (const std::string &if_name, PortID idx=InvalidPortID) override
	Get a port with a given name and index. More...

Public Member Functions inherited from gem5::PioDevice
	PioDevice (const Params &p)

virtual	~PioDevice ()

void	init () override
	init() is called after all C++ SimObjects have been created and all ports are connected. More...

Port &	getPort (const std::string &if_name, PortID idx=InvalidPortID) override
	Get a port with a given name and index. More...

Public Member Functions inherited from gem5::ClockedObject
	ClockedObject (const ClockedObjectParams &p)

void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...

void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...

Public Member Functions inherited from gem5::SimObject
const Params &	params () const

	SimObject (const Params &p)

virtual	~SimObject ()

virtual void	loadState (CheckpointIn &cp)
	loadState() is called on each SimObject when restoring from a checkpoint. More...

virtual void	initState ()
	initState() is called on each SimObject when not restoring from a checkpoint. More...

virtual void	regProbePoints ()
	Register probe points for this object. More...

virtual void	regProbeListeners ()
	Register probe listeners for this object. More...

ProbeManager *	getProbeManager ()
	Get the probe manager for this object. More...

virtual void	startup ()
	startup() is the final initialization call before simulation. More...

DrainState	drain () override
	Provide a default implementation of the drain interface for objects that don't need draining. More...

virtual void	memWriteback ()
	Write back dirty buffers to memory using functional writes. More...

virtual void	memInvalidate ()
	Invalidate the contents of memory buffers. More...

void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...

void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...

Public Member Functions inherited from gem5::EventManager
EventQueue *	eventQueue () const

void	schedule (Event &event, Tick when)

void	deschedule (Event &event)

void	reschedule (Event &event, Tick when, bool always=false)

void	schedule (Event *event, Tick when)

void	deschedule (Event *event)

void	reschedule (Event *event, Tick when, bool always=false)

void	wakeupEventQueue (Tick when=(Tick) -1)
	This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers. More...

void	setCurTick (Tick newVal)

	EventManager (EventManager &em)
	Event manger manages events in the event queue. More...

	EventManager (EventManager *em)

	EventManager (EventQueue *eq)

Public Member Functions inherited from gem5::Serializable
	Serializable ()

virtual	~Serializable ()

void	serializeSection (CheckpointOut &cp, const char *name) const
	Serialize an object into a new section. More...

void	serializeSection (CheckpointOut &cp, const std::string &name) const

void	unserializeSection (CheckpointIn &cp, const char *name)
	Unserialize an a child object. More...

void	unserializeSection (CheckpointIn &cp, const std::string &name)

Public Member Functions inherited from gem5::Drainable
DrainState	drainState () const
	Return the current drain state of an object. More...

virtual void	notifyFork ()
	Notify a child process of a fork. More...

Public Member Functions inherited from gem5::statistics::Group
	Group (Group parent, const char name=nullptr)
	Construct a new statistics group. More...

virtual	~Group ()

virtual void	regStats ()
	Callback to set stat parameters. More...

virtual void	resetStats ()
	Callback to reset stats. More...

virtual void	preDumpStats ()
	Callback before stats are dumped. More...

void	addStat (statistics::Info *info)
	Register a stat with this group. More...

const std::map< std::string, Group * > &	getStatGroups () const
	Get all child groups associated with this object. More...

const std::vector< Info * > &	getStats () const
	Get all stats associated with this object. More...

void	addStatGroup (const char name, Group block)
	Add a stat block as a child of this block. More...

const Info *	resolveStat (std::string name) const
	Resolve a stat by its name within this group. More...

void	mergeStatGroup (Group *block)
	Merge the contents (stats & children) of a block to this block. More...

	Group ()=delete

	Group (const Group &)=delete

Group &	operator= (const Group &)=delete

Public Member Functions inherited from gem5::Named
	Named (const std::string &name_)

virtual	~Named ()=default

virtual std::string	name () const

Public Member Functions inherited from gem5::Clocked
void	updateClockPeriod ()
	Update the tick to the current tick. More...

Tick	clockEdge (Cycles cycles=Cycles(0)) const
	Determine the tick when a cycle begins, by default the current one, but the argument also enables the caller to determine a future cycle. More...

Cycles	curCycle () const
	Determine the current cycle, corresponding to a tick aligned to a clock edge. More...

Tick	nextCycle () const
	Based on the clock of the object, determine the start tick of the first cycle that is at least one cycle in the future. More...

uint64_t	frequency () const

Tick	clockPeriod () const

double	voltage () const

Cycles	ticksToCycles (Tick t) const

Tick	cyclesToTicks (Cycles c) const

Public Attributes
int	numHWQueues

Addr	pioAddr

Addr	pioSize

Tick	pioDelay

const Tick	pktProcessDelay

Public Attributes inherited from gem5::ClockedObject
PowerState *	powerState

Protected Types
typedef void(DmaDevice::*	DmaFnPtr) (Addr, int, Event , uint8_t , Tick)

Protected Member Functions
Q_STATE	processPkt (void *pkt, uint32_t rl_idx, Addr host_pkt_addr)

void	displayQueueDescriptor (int pid, uint32_t rl_idx)

Protected Member Functions inherited from gem5::PioDevice
virtual Tick	read (PacketPtr pkt)=0
	Pure virtual function that the device must implement. More...

virtual Tick	write (PacketPtr pkt)=0
	Pure virtual function that the device must implement. More...

Protected Member Functions inherited from gem5::Drainable
	Drainable ()

virtual	~Drainable ()

virtual void	drainResume ()
	Resume execution after a successful drain. More...

void	signalDrainDone () const
	Signal that an object is drained. More...

Protected Member Functions inherited from gem5::Clocked
	Clocked (ClockDomain &clk_domain)
	Create a clocked object and set the clock domain based on the parameters. More...

	Clocked (Clocked &)=delete

Clocked &	operator= (Clocked &)=delete

virtual	~Clocked ()
	Virtual destructor due to inheritance. More...

void	resetClock () const
	Reset the object's clock using the current global tick value. More...

virtual void	clockPeriodUpdated ()
	A hook subclasses can implement so they can do any extra work that's needed when the clock rate is changed. More...

Protected Attributes
GPUCommandProcessor *	gpu_device

HWScheduler *	hwSchdlr

AMDGPUDevice *	gpuDevice

VegaISA::Walker *	walker

std::vector< class RQLEntry * >	regdQList

Protected Attributes inherited from gem5::DmaDevice
DmaPort	dmaPort

Protected Attributes inherited from gem5::PioDevice
System *	sys

PioPort< PioDevice >	pioPort
	The pioPort that handles the requests for us and provides us requests that it sees. More...

Protected Attributes inherited from gem5::SimObject
const SimObjectParams &	_params
	Cached copy of the object parameters. More...

Protected Attributes inherited from gem5::EventManager
EventQueue *	eventq
	A pointer to this object's event queue. More...

Friends
class	HWScheduler

Additional Inherited Members
Static Public Member Functions inherited from gem5::SimObject
static void	serializeAll (const std::string &cpt_dir)
	Create a checkpoint by serializing all SimObjects in the system. More...

static SimObject *	find (const char *name)
	Find the SimObject with the given name and return a pointer to it. More...

static void	setSimObjectResolver (SimObjectResolver *resolver)
	There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More...

static SimObjectResolver *	getSimObjectResolver ()
	There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More...

Static Public Member Functions inherited from gem5::Serializable
static const std::string &	currentSection ()
	Gets the fully-qualified name of the active section. More...

static void	generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream)
	Generate a checkpoint file so that the serialization can be routed to it. More...

Detailed Description

Definition at line 254 of file hsa_packet_processor.hh.

Member Typedef Documentation

◆ DmaFnPtr

typedef void(DmaDevice::* gem5::HSAPacketProcessor::DmaFnPtr) (Addr, int, Event *, uint8_t *, Tick)

protected

Definition at line 258 of file hsa_packet_processor.hh.

◆ Params

typedef HSAPacketProcessorParams gem5::HSAPacketProcessor::Params

Definition at line 353 of file hsa_packet_processor.hh.

Constructor & Destructor Documentation

◆ HSAPacketProcessor()

gem5::HSAPacketProcessor::HSAPacketProcessor ( const Params & p )

Definition at line 76 of file hsa_packet_processor.cc.

References DPRINTF, gem5::ArmISA::i, and gem5::VegaISA::p.

◆ ~HSAPacketProcessor()

gem5::HSAPacketProcessor::~HSAPacketProcessor ( )

Definition at line 89 of file hsa_packet_processor.cc.

References regdQList.

Member Function Documentation

◆ cmdQueueCmdDma()

void gem5::HSAPacketProcessor::cmdQueueCmdDma	(	HSAPacketProcessor *	hsaPP,
		int	pid,
		bool	isRead,
		uint32_t	ix_start,
		unsigned	num_pkts,
		dma_series_ctx *	series_ctx,
		void *	dest_4debug
	)

Definition at line 232 of file hsa_packet_processor.cc.

References gem5::AQLRingBuffer::dispIdx(), gem5::HSAQueueDescriptor::dmaInProgress, DPRINTF, gem5::HSAPacketProcessor::dma_series_ctx::pkts_2_go, gem5::AQLRingBuffer::rdIdx(), regdQList, gem5::HSAPacketProcessor::dma_series_ctx::rl_idx, schedAQLProcessing(), and gem5::AQLRingBuffer::wrIdx().

Referenced by getCommandsFromHost().

◆ displayQueueDescriptor()

void gem5::HSAPacketProcessor::displayQueueDescriptor	(	int	pid,
		uint32_t	rl_idx
	)

protected

Definition at line 582 of file hsa_packet_processor.cc.

References gem5::HSAQueueDescriptor::basePointer, gem5::HSAQueueDescriptor::doorbellPointer, DPRINTF, gem5::HSAQueueDescriptor::numElts, gem5::HSAQueueDescriptor::readIndex, regdQList, and gem5::HSAQueueDescriptor::writeIndex.

◆ finishPkt() [1/2]

void gem5::HSAPacketProcessor::finishPkt ( void * pkt )

inline

Definition at line 375 of file hsa_packet_processor.hh.

References finishPkt().

Referenced by finishPkt().

◆ finishPkt() [2/2]

void gem5::HSAPacketProcessor::finishPkt	(	void *	pkt,
		uint32_t	rl_idx
	)

Definition at line 671 of file hsa_packet_processor.cc.

References DPRINTF, getCommandsFromHost(), gem5::HSAQueueDescriptor::isEmpty(), gem5::HSAQueueDescriptor::numElts, gem5::HSAQueueDescriptor::readIndex, regdQList, schedAQLProcessing(), gem5::HSAQueueDescriptor::spaceUsed(), gem5::HSAQueueDescriptor::stalledOnDmaBufAvailability, updateReadIndex(), and gem5::HSAQueueDescriptor::writeIndex.

Referenced by gem5::GPUDispatcher::notifyWgCompl(), processPkt(), gem5::GPUCommandProcessor::submitAgentDispatchPkt(), and gem5::GPUCommandProcessor::submitVendorPkt().

◆ getAddrRanges()

AddrRangeList gem5::HSAPacketProcessor::getAddrRanges ( ) const

overridevirtual

Every PIO device is obliged to provide an implementation that returns the address ranges the device responds to.

Returns: a list of non-overlapping address ranges

Implements gem5::PioDevice.

Definition at line 128 of file hsa_packet_processor.cc.

References pioAddr, pioSize, and gem5::RangeSize().

◆ getCommandsFromHost()

void gem5::HSAPacketProcessor::getCommandsFromHost	(	int	pid,
		uint32_t	rl_idx
	)

◆ getQueueDesc()

HSAQueueDescriptor* gem5::HSAPacketProcessor::getQueueDesc ( uint32_t queId )

inline

Definition at line 330 of file hsa_packet_processor.hh.

References regdQList.

Referenced by gem5::GPUCommandProcessor::initABI(), and gem5::GPUCommandProcessor::ReadDispIdOffsetDmaEvent().

◆ getRegdListEntry()

class RQLEntry* gem5::HSAPacketProcessor::getRegdListEntry ( uint32_t queId )

inline

Definition at line 335 of file hsa_packet_processor.hh.

References regdQList.

Referenced by gem5::HWScheduler::addQCntxt(), gem5::HWScheduler::findEmptyHWQ(), gem5::HWScheduler::isRLQIdle(), gem5::HWScheduler::removeQCntxt(), and gem5::HWScheduler::unregisterQueue().

◆ handleReadDMA()

void gem5::HSAPacketProcessor::handleReadDMA ( )

◆ hwScheduler()

HWScheduler* gem5::HSAPacketProcessor::hwScheduler ( )

inline

Definition at line 368 of file hsa_packet_processor.hh.

References hwSchdlr.

Referenced by gem5::AMDGPUDevice::writeDoorbell().

◆ inFlightPkts()

uint64_t gem5::HSAPacketProcessor::inFlightPkts ( uint32_t queId )

inline

Definition at line 341 of file hsa_packet_processor.hh.

References regdQList.

Referenced by gem5::HWScheduler::isRLQIdle(), and gem5::GPUCommandProcessor::MQDDmaEvent().

◆ processPkt()

Q_STATE gem5::HSAPacketProcessor::processPkt	(	void *	pkt,
		uint32_t	rl_idx,
		Addr	host_pkt_addr
	)

protected

Definition at line 283 of file hsa_packet_processor.cc.

References gem5::HSAPacketProcessor::SignalState::allRead, gem5::BLOCKED_BBIT, gem5::BLOCKED_BPKT, gem5::HSAPacketProcessor::SignalState::discardRead, gem5::DmaVirtDevice::dmaReadVirt(), DPRINTF, fatal, finishPkt(), gem5::GPUCommandProcessor::functionalReadHsaSignal(), gpu_device, gem5::HSAPacketProcessor::SignalState::handleReadDMA(), HSA_PACKET_TYPE_AGENT_DISPATCH, HSA_PACKET_TYPE_BARRIER_AND, HSA_PACKET_TYPE_BARRIER_OR, HSA_PACKET_TYPE_INVALID, HSA_PACKET_TYPE_KERNEL_DISPATCH, HSA_PACKET_TYPE_VENDOR_SPECIFIC, gem5::ArmISA::i, IS_BARRIER, NumSignalsPerBarrier, gem5::HSAPacketProcessor::SignalState::pendingReads, PKT_TYPE, regdQList, gem5::HSAPacketProcessor::SignalState::resetSigVals(), sendAgentDispatchCompletionSignal(), gem5::GPUCommandProcessor::submitAgentDispatchPkt(), gem5::GPUCommandProcessor::submitDispatchPkt(), gem5::GPUCommandProcessor::submitVendorPkt(), gem5::UNBLOCKED, gem5::GPUCommandProcessor::updateHsaSignal(), and gem5::HSAPacketProcessor::SignalState::values.

Referenced by gem5::HSAPacketProcessor::QueueProcessEvent::process().

◆ read()

Tick gem5::HSAPacketProcessor::read ( Packet * pkt )

overridevirtual

Definition at line 170 of file hsa_packet_processor.cc.

References gem5::Packet::makeAtomicResponse(), pioDelay, and gem5::Packet::setBadAddress().

◆ schedAQLProcessing() [1/2]

void gem5::HSAPacketProcessor::schedAQLProcessing ( uint32_t rl_idx )

Definition at line 277 of file hsa_packet_processor.cc.

References pktProcessDelay.

Referenced by cmdQueueCmdDma(), finishPkt(), gem5::HSAPacketProcessor::QueueProcessEvent::process(), and gem5::HWScheduler::scheduleAndWakeupMappedQ().

◆ schedAQLProcessing() [2/2]

void gem5::HSAPacketProcessor::schedAQLProcessing	(	uint32_t	rl_idx,
		Tick	delay
	)

Definition at line 263 of file hsa_packet_processor.cc.

References gem5::HSAPacketProcessor::RQLEntry::aqlProcessEvent, gem5::curTick(), DPRINTF, regdQList, gem5::EventManager::schedule(), and gem5::Event::scheduled().

◆ sendAgentDispatchCompletionSignal()

void gem5::HSAPacketProcessor::sendAgentDispatchCompletionSignal	(	void *	pkt,
		hsa_signal_value_t	signal
	)

HACK: The semantics of the HSA signal is to decrement the current signal value. I'm going to cheat here and read out the value from main memory using functional access, and then just DMA the decremented value. The reason for this is that the DMASequencer does not support atomic operations.

Definition at line 713 of file hsa_packet_processor.cc.

References gem5::DmaVirtDevice::dmaWriteVirt(), DPRINTF, gem5::PioDevice::sys, and gem5::System::threads.

Referenced by processPkt().

◆ sendCompletionSignal()

void gem5::HSAPacketProcessor::sendCompletionSignal ( hsa_signal_value_t signal )

HACK: The semantics of the HSA signal is to decrement the current signal value. I'm going to cheat here and read out the value from main memory using functional access, and then just DMA the decremented value. The reason for this is that the DMASequencer does not support atomic operations.

Definition at line 743 of file hsa_packet_processor.cc.

References gem5::DmaVirtDevice::dmaWriteVirt(), DPRINTF, gem5::PioDevice::sys, and gem5::System::threads.

◆ setDevice()

void gem5::HSAPacketProcessor::setDevice ( GPUCommandProcessor * dev )

Definition at line 646 of file hsa_packet_processor.cc.

References gpu_device.

Referenced by gem5::GPUCommandProcessor::GPUCommandProcessor().

◆ setDeviceQueueDesc()

void gem5::HSAPacketProcessor::setDeviceQueueDesc	(	uint64_t	hostReadIndexPointer,
		uint64_t	basePointer,
		uint64_t	queue_id,
		uint32_t	size,
		int	doorbellSize,
		GfxVersion	gfxVersion,
		Addr	offset = `0`,
		uint64_t	rd_idx = `0`
	)

Definition at line 112 of file hsa_packet_processor.cc.

References DPRINTF, hwSchdlr, gem5::ArmISA::offset, and gem5::HWScheduler::registerNewQueue().

Referenced by gem5::GPUComputeDriver::allocateQueue(), and gem5::PM4PacketProcessor::processMQD().

◆ setGPUDevice()

void gem5::HSAPacketProcessor::setGPUDevice ( AMDGPUDevice * gpu_device )

Definition at line 97 of file hsa_packet_processor.cc.

References gpu_device, gpuDevice, gem5::VegaISA::Walker::setDevRequestor(), gem5::AMDGPUDevice::vramRequestorId(), and walker.

Referenced by gem5::AMDGPUDevice::AMDGPUDevice().

◆ translate()

TranslationGenPtr gem5::HSAPacketProcessor::translate	(	Addr	vaddr,
		Addr	size
	)

overridevirtual

Function used to translate a range of addresses from virtual to physical addresses.

All classes inheriting from DmaVirtDevice must define this.

Parameters

vaddr	Virtual address of the start of the range
size	Size of the range in bytes

Returns: A translation generator for this range

Implements gem5::DmaVirtDevice.

Definition at line 178 of file hsa_packet_processor.cc.

References gem5::FullSystem, gem5::AMDGPUDevice::getVM(), gpuDevice, gem5::PioDevice::sys, gem5::System::threads, gem5::MipsISA::vaddr, and walker.

◆ unsetDeviceQueueDesc()

void gem5::HSAPacketProcessor::unsetDeviceQueueDesc	(	uint64_t	queue_id,
		int	doorbellSize
	)

Definition at line 106 of file hsa_packet_processor.cc.

References hwSchdlr, and gem5::HWScheduler::unregisterQueue().

Referenced by gem5::GPUComputeDriver::ioctl().

◆ updateReadDispIdDma()

void gem5::HSAPacketProcessor::updateReadDispIdDma ( )

this event is used to update the read_disp_id field (the read pointer) of the MQD, which is how the host code knows the status of the HQD's read pointer

Definition at line 202 of file hsa_packet_processor.cc.

References DPRINTF.

Referenced by updateReadIndex().

◆ updateReadIndex()

void gem5::HSAPacketProcessor::updateReadIndex	(	int	pid,
		uint32_t	rl_idx
	)

Definition at line 208 of file hsa_packet_processor.cc.

References gem5::DmaVirtDevice::dmaWriteVirt(), DPRINTF, getCommandsFromHost(), gem5::HSAQueueDescriptor::hostReadIndexPtr, gem5::HSAQueueDescriptor::isEmpty(), gem5::HSAQueueDescriptor::numElts, gem5::AQLRingBuffer::rdIdx(), gem5::AQLRingBuffer::rdIdxPtr(), gem5::HSAQueueDescriptor::readIndex, regdQList, gem5::HSAQueueDescriptor::spaceUsed(), updateReadDispIdDma(), gem5::AQLRingBuffer::wrIdx(), and gem5::HSAQueueDescriptor::writeIndex.

Referenced by finishPkt().

◆ write()

Tick gem5::HSAPacketProcessor::write ( Packet * pkt )

overridevirtual

Definition at line 140 of file hsa_packet_processor.cc.

References gem5::GPUComputeDriver::doorbellSize(), DPRINTF, gem5::GPUCommandProcessor::driver(), fatal, gem5::Packet::getAddr(), gem5::Packet::getLE(), gem5::Packet::getSize(), gpu_device, hwSchdlr, gem5::Packet::makeAtomicResponse(), pioAddr, pioDelay, pioSize, and gem5::HWScheduler::write().

Friends And Related Function Documentation

◆ HWScheduler

friend class HWScheduler

friend

Definition at line 256 of file hsa_packet_processor.hh.

Member Data Documentation

◆ gpu_device

GPUCommandProcessor* gem5::HSAPacketProcessor::gpu_device

protected

Definition at line 259 of file hsa_packet_processor.hh.

Referenced by processPkt(), setDevice(), setGPUDevice(), and write().

◆ gpuDevice

AMDGPUDevice* gem5::HSAPacketProcessor::gpuDevice

protected

Definition at line 261 of file hsa_packet_processor.hh.

Referenced by setGPUDevice(), and translate().

◆ hwSchdlr

HWScheduler* gem5::HSAPacketProcessor::hwSchdlr

protected

Definition at line 260 of file hsa_packet_processor.hh.

Referenced by hwScheduler(), setDeviceQueueDesc(), unsetDeviceQueueDesc(), and write().

◆ numHWQueues

int gem5::HSAPacketProcessor::numHWQueues

Definition at line 347 of file hsa_packet_processor.hh.

Referenced by gem5::HWScheduler::findEmptyHWQ(), gem5::HWScheduler::findNextIdleRLQ(), and gem5::HWScheduler::updateRRVars().

◆ pioAddr

Addr gem5::HSAPacketProcessor::pioAddr

Definition at line 348 of file hsa_packet_processor.hh.

Referenced by getAddrRanges(), gem5::GPUComputeDriver::ioctl(), gem5::GPUComputeDriver::mmap(), and write().

◆ pioDelay

Tick gem5::HSAPacketProcessor::pioDelay

Definition at line 350 of file hsa_packet_processor.hh.

Referenced by read(), and write().

◆ pioSize

Addr gem5::HSAPacketProcessor::pioSize

Definition at line 349 of file hsa_packet_processor.hh.

Referenced by getAddrRanges(), and write().

◆ pktProcessDelay

const Tick gem5::HSAPacketProcessor::pktProcessDelay

Definition at line 351 of file hsa_packet_processor.hh.

Referenced by schedAQLProcessing().

◆ regdQList

std::vector<class RQLEntry *> gem5::HSAPacketProcessor::regdQList

protected

Definition at line 323 of file hsa_packet_processor.hh.

Referenced by cmdQueueCmdDma(), displayQueueDescriptor(), finishPkt(), getCommandsFromHost(), getQueueDesc(), getRegdListEntry(), inFlightPkts(), gem5::HSAPacketProcessor::QueueProcessEvent::process(), processPkt(), schedAQLProcessing(), gem5::HWScheduler::scheduleAndWakeupMappedQ(), updateReadIndex(), and ~HSAPacketProcessor().

◆ walker

VegaISA::Walker* gem5::HSAPacketProcessor::walker

protected

Definition at line 262 of file hsa_packet_processor.hh.

Referenced by setGPUDevice(), and translate().

The documentation for this class was generated from the following files:

dev/hsa/hsa_packet_processor.hh
dev/hsa/hsa_packet_processor.cc

Classes

Public Types

Public Member Functions

Public Attributes

Protected Types

Protected Member Functions

Protected Attributes

Friends

Additional Inherited Members

Detailed Description

Member Typedef Documentation

◆ DmaFnPtr

◆ Params

Constructor & Destructor Documentation

◆ HSAPacketProcessor()

◆ ~HSAPacketProcessor()

Member Function Documentation

◆ cmdQueueCmdDma()

◆ displayQueueDescriptor()

◆ finishPkt() [1/2]

◆ finishPkt() [2/2]

◆ getAddrRanges()

◆ getCommandsFromHost()

◆ getQueueDesc()

◆ getRegdListEntry()

◆ handleReadDMA()

◆ hwScheduler()

◆ inFlightPkts()

◆ processPkt()

◆ read()

◆ schedAQLProcessing() [1/2]

◆ schedAQLProcessing() [2/2]

◆ sendAgentDispatchCompletionSignal()

◆ sendCompletionSignal()

◆ setDevice()

◆ setDeviceQueueDesc()

◆ setGPUDevice()

◆ translate()

◆ unsetDeviceQueueDesc()

◆ updateReadDispIdDma()

◆ updateReadIndex()

◆ write()

Friends And Related Function Documentation

◆ HWScheduler

Member Data Documentation

◆ gpu_device

◆ gpuDevice

◆ hwSchdlr

◆ numHWQueues

◆ pioAddr

◆ pioDelay

◆ pioSize

◆ pktProcessDelay

◆ regdQList

◆ walker