gem5  v22.0.0.2
gem5::PowerISA::TLB Member List

This is the complete list of members for gem5::PowerISA::TLB, including all inherited members.

_drainManagergem5::Drainableprivate
_drainStategem5::Drainablemutableprivate
_namegem5::Namedprivate
_nextLevelgem5::BaseTLBprotected
_objNameResolvergem5::SimObjectprivatestatic
_paramsgem5::SimObjectprotected
_typegem5::BaseTLBprotected
addStat(statistics::Info *info)gem5::statistics::Group
addStatGroup(const char *name, Group *block)gem5::statistics::Group
BaseTLB(const BaseTLBParams &p)gem5::BaseTLBinlineprotected
checkCacheability(const RequestPtr &req)gem5::PowerISA::TLBinlinestatic
currentSection()gem5::Serializablestatic
demapPage(Addr vaddr, uint64_t asn) overridegem5::PowerISA::TLBinlinevirtual
deschedule(Event &event)gem5::EventManagerinline
deschedule(Event *event)gem5::EventManagerinline
dmDrain()gem5::Drainableprivate
dmDrainResume()gem5::Drainableprivate
drain() overridegem5::SimObjectinlinevirtual
Drainable()gem5::Drainableprotected
drainResume()gem5::Drainableinlineprotectedvirtual
drainState() constgem5::Drainableinline
EventManager(EventManager &em)gem5::EventManagerinline
EventManager(EventManager *em)gem5::EventManagerinline
EventManager(EventQueue *eq)gem5::EventManagerinline
eventqgem5::EventManagerprotected
eventQueue() constgem5::EventManagerinline
finalizePhysical(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) const overridegem5::PowerISA::TLBvirtual
find(const char *name)gem5::SimObjectstatic
flushAll() overridegem5::PowerISA::TLBvirtual
generateCheckpointOut(const std::string &cpt_dir, std::ofstream &outstream)gem5::Serializablestatic
getEntry(unsigned) constgem5::PowerISA::TLB
getPort(const std::string &if_name, PortID idx=InvalidPortID)gem5::SimObjectvirtual
getProbeManager()gem5::SimObject
getSimObjectResolver()gem5::SimObjectstatic
getsize() constgem5::PowerISA::TLBinline
getStatGroups() constgem5::statistics::Group
getStats() constgem5::statistics::Group
getTableWalkerPort()gem5::BaseTLBinlinevirtual
Group()=deletegem5::statistics::Group
Group(const Group &)=deletegem5::statistics::Group
Group(Group *parent, const char *name=nullptr)gem5::statistics::Group
index(bool advance=true)gem5::PowerISA::TLB
init()gem5::SimObjectvirtual
initState()gem5::SimObjectvirtual
insert(Addr vaddr, PowerISA::PTE &pte)gem5::PowerISA::TLB
insertAt(PowerISA::PTE &pte, unsigned Index, int _smallPages)gem5::PowerISA::TLB
loadState(CheckpointIn &cp)gem5::SimObjectvirtual
lookup(Addr vpn, uint8_t asn) constgem5::PowerISA::TLBprotected
lookupTablegem5::PowerISA::TLBprotected
memInvalidate()gem5::BaseTLBinlinevirtual
memWriteback()gem5::SimObjectinlinevirtual
mergedParentgem5::statistics::Groupprivate
mergedStatGroupsgem5::statistics::Groupprivate
mergeStatGroup(Group *block)gem5::statistics::Group
name() constgem5::Namedinlinevirtual
Named(const std::string &name_)gem5::Namedinline
nextLevel() constgem5::BaseTLBinline
nextnlu()gem5::PowerISA::TLBinlineprotected
nlugem5::PowerISA::TLBprotected
notifyFork()gem5::Drainableinlinevirtual
operator=(const Group &)=deletegem5::statistics::Group
PageTable typedefgem5::PowerISA::TLBprotected
params() constgem5::SimObjectinline
Params typedefgem5::PowerISA::TLB
pathgem5::Serializableprivatestatic
preDumpStats()gem5::statistics::Groupvirtual
probeEntry(Addr vpn, uint8_t) constgem5::PowerISA::TLB
probeManagergem5::SimObjectprivate
regProbeListeners()gem5::SimObjectvirtual
regProbePoints()gem5::SimObjectvirtual
regStats()gem5::statistics::Groupvirtual
reschedule(Event &event, Tick when, bool always=false)gem5::EventManagerinline
reschedule(Event *event, Tick when, bool always=false)gem5::EventManagerinline
resetStats()gem5::statistics::Groupvirtual
resolveStat(std::string name) constgem5::statistics::Group
schedule(Event &event, Tick when)gem5::EventManagerinline
schedule(Event *event, Tick when)gem5::EventManagerinline
Serializable()gem5::Serializable
serialize(CheckpointOut &cp) const overridegem5::PowerISA::TLBvirtual
serializeAll(const std::string &cpt_dir)gem5::SimObjectstatic
serializeSection(CheckpointOut &cp, const char *name) constgem5::Serializable
serializeSection(CheckpointOut &cp, const std::string &name) constgem5::Serializableinline
setCurTick(Tick newVal)gem5::EventManagerinline
setSimObjectResolver(SimObjectResolver *resolver)gem5::SimObjectstatic
signalDrainDone() constgem5::Drainableinlineprotected
SimObject(const Params &p)gem5::SimObject
SimObjectList typedefgem5::SimObjectprivate
simObjectListgem5::SimObjectprivatestatic
sizegem5::PowerISA::TLBprotected
smallPagesgem5::PowerISA::TLB
startup()gem5::SimObjectvirtual
statGroupsgem5::statistics::Groupprivate
statsgem5::statistics::Groupprivate
tablegem5::PowerISA::TLBprotected
takeOverFrom(BaseTLB *otlb) overridegem5::PowerISA::TLBinlinevirtual
TLB(const Params &p)gem5::PowerISA::TLB
translateAtomic(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) overridegem5::PowerISA::TLBvirtual
translateData(const RequestPtr &req, ThreadContext *tc, bool write)gem5::PowerISA::TLB
translateFunctional(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) overridegem5::PowerISA::TLBvirtual
translateInst(const RequestPtr &req, ThreadContext *tc)gem5::PowerISA::TLB
translateTiming(const RequestPtr &req, ThreadContext *tc, BaseMMU::Translation *translation, BaseMMU::Mode mode) overridegem5::PowerISA::TLBvirtual
type() constgem5::BaseTLBinline
unserialize(CheckpointIn &cp) overridegem5::PowerISA::TLBvirtual
unserializeSection(CheckpointIn &cp, const char *name)gem5::Serializable
unserializeSection(CheckpointIn &cp, const std::string &name)gem5::Serializableinline
validVirtualAddress(Addr vaddr)gem5::PowerISA::TLBstatic
wakeupEventQueue(Tick when=(Tick) -1)gem5::EventManagerinline
~Drainable()gem5::Drainableprotectedvirtual
~Group()gem5::statistics::Groupvirtual
~Named()=defaultgem5::Namedvirtual
~Serializable()gem5::Serializablevirtual
~SimObject()gem5::SimObjectvirtual
~TLB()gem5::PowerISA::TLBvirtual

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