| _drainManager | gem5::Drainable | private |
| _drainState | gem5::Drainable | mutableprivate |
| _name | gem5::Named | private |
| _nextLevel | gem5::BaseTLB | protected |
| _objNameResolver | gem5::SimObject | privatestatic |
| _params | gem5::SimObject | protected |
| _type | gem5::BaseTLB | protected |
| addStat(statistics::Info *info) | gem5::statistics::Group | |
| addStatGroup(const char *name, Group *block) | gem5::statistics::Group | |
| BaseTLB(const BaseTLBParams &p) | gem5::BaseTLB | inlineprotected |
| checkPermissions(STATUS status, PrivilegeMode pmode, Addr vaddr, BaseMMU::Mode mode, PTESv39 pte) | gem5::RiscvISA::TLB | |
| createPagefault(Addr vaddr, BaseMMU::Mode mode) | gem5::RiscvISA::TLB | |
| currentSection() | gem5::Serializable | static |
| demapPage(Addr vaddr, uint64_t asn) override | gem5::RiscvISA::TLB | virtual |
| deschedule(Event &event) | gem5::EventManager | inline |
| deschedule(Event *event) | gem5::EventManager | inline |
| dmDrain() | gem5::Drainable | private |
| dmDrainResume() | gem5::Drainable | private |
| doTranslate(const RequestPtr &req, ThreadContext *tc, BaseMMU::Translation *translation, BaseMMU::Mode mode, bool &delayed) | gem5::RiscvISA::TLB | private |
| drain() override | gem5::SimObject | inlinevirtual |
| Drainable() | gem5::Drainable | protected |
| drainResume() | gem5::Drainable | inlineprotectedvirtual |
| drainState() const | gem5::Drainable | inline |
| EntryList typedef | gem5::RiscvISA::TLB | private |
| EventManager(EventManager &em) | gem5::EventManager | inline |
| EventManager(EventManager *em) | gem5::EventManager | inline |
| EventManager(EventQueue *eq) | gem5::EventManager | inline |
| eventq | gem5::EventManager | protected |
| eventQueue() const | gem5::EventManager | inline |
| evictLRU() | gem5::RiscvISA::TLB | private |
| finalizePhysical(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) const override | gem5::RiscvISA::TLB | virtual |
| find(const char *name) | gem5::SimObject | static |
| flushAll() override | gem5::RiscvISA::TLB | virtual |
| freeList | gem5::RiscvISA::TLB | protected |
| generateCheckpointOut(const std::string &cpt_dir, std::ofstream &outstream) | gem5::Serializable | static |
| getMemPriv(ThreadContext *tc, BaseMMU::Mode mode) | gem5::RiscvISA::TLB | |
| getPort(const std::string &if_name, PortID idx=InvalidPortID) | gem5::SimObject | virtual |
| getProbeManager() | gem5::SimObject | |
| getSimObjectResolver() | gem5::SimObject | static |
| getStatGroups() const | gem5::statistics::Group | |
| getStats() const | gem5::statistics::Group | |
| getTableWalkerPort() override | gem5::RiscvISA::TLB | virtual |
| getWalker() | gem5::RiscvISA::TLB | |
| Group()=delete | gem5::statistics::Group | |
| Group(const Group &)=delete | gem5::statistics::Group | |
| Group(Group *parent, const char *name=nullptr) | gem5::statistics::Group | |
| init() | gem5::SimObject | virtual |
| initState() | gem5::SimObject | virtual |
| insert(Addr vpn, const TlbEntry &entry) | gem5::RiscvISA::TLB | |
| loadState(CheckpointIn &cp) | gem5::SimObject | virtual |
| lookup(Addr vpn, uint16_t asid, BaseMMU::Mode mode, bool hidden) | gem5::RiscvISA::TLB | |
| lruSeq | gem5::RiscvISA::TLB | protected |
| memInvalidate() | gem5::BaseTLB | inlinevirtual |
| memWriteback() | gem5::SimObject | inlinevirtual |
| mergedParent | gem5::statistics::Group | private |
| mergedStatGroups | gem5::statistics::Group | private |
| mergeStatGroup(Group *block) | gem5::statistics::Group | |
| name() const | gem5::Named | inlinevirtual |
| Named(const std::string &name_) | gem5::Named | inline |
| nextLevel() const | gem5::BaseTLB | inline |
| nextSeq() | gem5::RiscvISA::TLB | inlineprivate |
| notifyFork() | gem5::Drainable | inlinevirtual |
| operator=(const Group &)=delete | gem5::statistics::Group | |
| Params typedef | gem5::RiscvISA::TLB | |
| params() const | gem5::SimObject | inline |
| path | gem5::Serializable | privatestatic |
| pma | gem5::RiscvISA::TLB | |
| pmp | gem5::RiscvISA::TLB | |
| preDumpStats() | gem5::statistics::Group | virtual |
| probeManager | gem5::SimObject | private |
| regProbeListeners() | gem5::SimObject | virtual |
| regProbePoints() | gem5::SimObject | virtual |
| regStats() | gem5::statistics::Group | virtual |
| remove(size_t idx) | gem5::RiscvISA::TLB | private |
| reschedule(Event &event, Tick when, bool always=false) | gem5::EventManager | inline |
| reschedule(Event *event, Tick when, bool always=false) | gem5::EventManager | inline |
| resetStats() | gem5::statistics::Group | virtual |
| resolveStat(std::string name) const | gem5::statistics::Group | |
| schedule(Event &event, Tick when) | gem5::EventManager | inline |
| schedule(Event *event, Tick when) | gem5::EventManager | inline |
| Serializable() | gem5::Serializable | |
| serialize(CheckpointOut &cp) const override | gem5::RiscvISA::TLB | virtual |
| serializeAll(const std::string &cpt_dir) | gem5::SimObject | static |
| serializeSection(CheckpointOut &cp, const char *name) const | gem5::Serializable | |
| serializeSection(CheckpointOut &cp, const std::string &name) const | gem5::Serializable | inline |
| setCurTick(Tick newVal) | gem5::EventManager | inline |
| setSimObjectResolver(SimObjectResolver *resolver) | gem5::SimObject | static |
| signalDrainDone() const | gem5::Drainable | inlineprotected |
| SimObject(const Params &p) | gem5::SimObject | |
| SimObjectList typedef | gem5::SimObject | private |
| simObjectList | gem5::SimObject | privatestatic |
| size | gem5::RiscvISA::TLB | protected |
| startup() | gem5::SimObject | virtual |
| statGroups | gem5::statistics::Group | private |
| stats | gem5::RiscvISA::TLB | protected |
| takeOverFrom(BaseTLB *old) override | gem5::RiscvISA::TLB | inlinevirtual |
| TLB(const Params &p) | gem5::RiscvISA::TLB | |
| tlb | gem5::RiscvISA::TLB | protected |
| translate(const RequestPtr &req, ThreadContext *tc, BaseMMU::Translation *translation, BaseMMU::Mode mode, bool &delayed) | gem5::RiscvISA::TLB | private |
| translateAtomic(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) override | gem5::RiscvISA::TLB | virtual |
| translateFunctional(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) override | gem5::RiscvISA::TLB | virtual |
| translateTiming(const RequestPtr &req, ThreadContext *tc, BaseMMU::Translation *translation, BaseMMU::Mode mode) override | gem5::RiscvISA::TLB | virtual |
| translateWithTLB(Addr vaddr, uint16_t asid, BaseMMU::Mode mode) | gem5::RiscvISA::TLB | |
| trie | gem5::RiscvISA::TLB | protected |
| type() const | gem5::BaseTLB | inline |
| unserialize(CheckpointIn &cp) override | gem5::RiscvISA::TLB | virtual |
| unserializeSection(CheckpointIn &cp, const char *name) | gem5::Serializable | |
| unserializeSection(CheckpointIn &cp, const std::string &name) | gem5::Serializable | inline |
| wakeupEventQueue(Tick when=(Tick) -1) | gem5::EventManager | inline |
| walker | gem5::RiscvISA::TLB | protected |
| ~Drainable() | gem5::Drainable | protectedvirtual |
| ~Group() | gem5::statistics::Group | virtual |
| ~Named()=default | gem5::Named | virtual |
| ~Serializable() | gem5::Serializable | virtual |
| ~SimObject() | gem5::SimObject | virtual |