gem5 v24.1.0.1
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#include <tlb.hh>
Classes | |
struct | TlbStats |
Public Types | |
typedef RiscvTLBParams | Params |
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typedef SimObjectParams | Params |
Public Member Functions | |
TLB (const Params &p) | |
Walker * | getWalker () |
void | takeOverFrom (BaseTLB *old) override |
Take over from an old tlb context. | |
TlbEntry * | insert (Addr vpn, const TlbEntry &entry) |
Insert an entry into the TLB. | |
void | flushAll () override |
Remove all entries from the TLB. | |
void | demapPage (Addr vaddr, uint64_t asn) override |
Fault | checkPermissions (STATUS status, PrivilegeMode pmode, Addr vaddr, BaseMMU::Mode mode, PTESv39 pte) |
Fault | createPagefault (Addr vaddr, BaseMMU::Mode mode) |
PrivilegeMode | getMemPriv (ThreadContext *tc, BaseMMU::Mode mode) |
void | serialize (CheckpointOut &cp) const override |
Serialize an object. | |
void | unserialize (CheckpointIn &cp) override |
Unserialize an object. | |
Port * | getTableWalkerPort () override |
Get the table walker port. | |
Addr | hiddenTranslateWithTLB (Addr vaddr, uint16_t asid, Addr xmode, BaseMMU::Mode mode) |
Fault | translateAtomic (const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) override |
void | translateTiming (const RequestPtr &req, ThreadContext *tc, BaseMMU::Translation *translation, BaseMMU::Mode mode) override |
Fault | translateFunctional (const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) override |
Fault | finalizePhysical (const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) const override |
Do post-translation physical address finalization. | |
Addr | getValidAddr (Addr vaddr, ThreadContext *tc, BaseMMU::Mode mode) |
TlbEntry * | lookup (Addr vpn, uint16_t asid, BaseMMU::Mode mode, bool hidden) |
Perform the tlb lookup. | |
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void | memInvalidate () |
Invalidate the contents of memory buffers. | |
TypeTLB | type () const |
BaseTLB * | nextLevel () const |
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const Params & | params () const |
SimObject (const Params &p) | |
virtual | ~SimObject () |
virtual void | init () |
init() is called after all C++ SimObjects have been created and all ports are connected. | |
virtual void | loadState (CheckpointIn &cp) |
loadState() is called on each SimObject when restoring from a checkpoint. | |
virtual void | initState () |
initState() is called on each SimObject when not restoring from a checkpoint. | |
virtual void | regProbePoints () |
Register probe points for this object. | |
virtual void | regProbeListeners () |
Register probe listeners for this object. | |
ProbeManager * | getProbeManager () |
Get the probe manager for this object. | |
virtual Port & | getPort (const std::string &if_name, PortID idx=InvalidPortID) |
Get a port with a given name and index. | |
virtual void | startup () |
startup() is the final initialization call before simulation. | |
DrainState | drain () override |
Provide a default implementation of the drain interface for objects that don't need draining. | |
virtual void | memWriteback () |
Write back dirty buffers to memory using functional writes. | |
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EventQueue * | eventQueue () const |
void | schedule (Event &event, Tick when) |
void | deschedule (Event &event) |
void | reschedule (Event &event, Tick when, bool always=false) |
void | schedule (Event *event, Tick when) |
void | deschedule (Event *event) |
void | reschedule (Event *event, Tick when, bool always=false) |
void | wakeupEventQueue (Tick when=(Tick) -1) |
This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers. | |
void | setCurTick (Tick newVal) |
EventManager (EventManager &em) | |
Event manger manages events in the event queue. | |
EventManager (EventManager *em) | |
EventManager (EventQueue *eq) | |
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Serializable () | |
virtual | ~Serializable () |
void | serializeSection (CheckpointOut &cp, const char *name) const |
Serialize an object into a new section. | |
void | serializeSection (CheckpointOut &cp, const std::string &name) const |
void | unserializeSection (CheckpointIn &cp, const char *name) |
Unserialize an a child object. | |
void | unserializeSection (CheckpointIn &cp, const std::string &name) |
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DrainState | drainState () const |
Return the current drain state of an object. | |
virtual void | notifyFork () |
Notify a child process of a fork. | |
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Group (Group *parent, const char *name=nullptr) | |
Construct a new statistics group. | |
virtual | ~Group () |
virtual void | regStats () |
Callback to set stat parameters. | |
virtual void | resetStats () |
Callback to reset stats. | |
virtual void | preDumpStats () |
Callback before stats are dumped. | |
void | addStat (statistics::Info *info) |
Register a stat with this group. | |
const std::map< std::string, Group * > & | getStatGroups () const |
Get all child groups associated with this object. | |
const std::vector< Info * > & | getStats () const |
Get all stats associated with this object. | |
void | addStatGroup (const char *name, Group *block) |
Add a stat block as a child of this block. | |
const Info * | resolveStat (std::string name) const |
Resolve a stat by its name within this group. | |
void | mergeStatGroup (Group *block) |
Merge the contents (stats & children) of a block to this block. | |
Group (const Group &)=delete | |
Group & | operator= (const Group &)=delete |
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Named (const std::string &name_) | |
virtual | ~Named ()=default |
virtual std::string | name () const |
Public Attributes | |
BasePMAChecker * | pma |
PMP * | pmp |
Protected Attributes | |
size_t | size |
std::vector< TlbEntry > | tlb |
TlbEntryTrie | trie |
EntryList | freeList |
uint64_t | lruSeq |
Walker * | walker |
gem5::RiscvISA::TLB::TlbStats | stats |
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TypeTLB | _type |
BaseTLB * | _nextLevel |
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const SimObjectParams & | _params |
Cached copy of the object parameters. | |
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EventQueue * | eventq |
A pointer to this object's event queue. | |
Private Types | |
typedef std::list< TlbEntry * > | EntryList |
Private Member Functions | |
uint64_t | nextSeq () |
void | evictLRU () |
void | remove (size_t idx) |
Fault | translate (const RequestPtr &req, ThreadContext *tc, BaseMMU::Translation *translation, BaseMMU::Mode mode, bool &delayed) |
Fault | doTranslate (const RequestPtr &req, ThreadContext *tc, BaseMMU::Translation *translation, BaseMMU::Mode mode, bool &delayed) |
Additional Inherited Members | |
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static void | serializeAll (const std::string &cpt_dir) |
Create a checkpoint by serializing all SimObjects in the system. | |
static SimObject * | find (const char *name) |
Find the SimObject with the given name and return a pointer to it. | |
static void | setSimObjectResolver (SimObjectResolver *resolver) |
There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. | |
static SimObjectResolver * | getSimObjectResolver () |
There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. | |
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static const std::string & | currentSection () |
Gets the fully-qualified name of the active section. | |
static void | generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream) |
Generate a checkpoint file so that the serialization can be routed to it. | |
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BaseTLB (const BaseTLBParams &p) | |
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Drainable () | |
virtual | ~Drainable () |
virtual void | drainResume () |
Resume execution after a successful drain. | |
void | signalDrainDone () const |
Signal that an object is drained. | |
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private |
typedef RiscvTLBParams gem5::RiscvISA::TLB::Params |
gem5::RiscvISA::TLB::TLB | ( | const Params & | p | ) |
Fault gem5::TLB::checkPermissions | ( | STATUS | status, |
PrivilegeMode | pmode, | ||
Addr | vaddr, | ||
BaseMMU::Mode | mode, | ||
PTESv39 | pte | ||
) |
Definition at line 251 of file tlb.cc.
References DPRINTF, gem5::ArmISA::mode, gem5::NoFault, gem5::ArmISA::status, and gem5::MipsISA::vaddr.
Referenced by gem5::RiscvISA::Walker::startWalkWrapper().
Fault gem5::TLB::createPagefault | ( | Addr | vaddr, |
BaseMMU::Mode | mode | ||
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Definition at line 285 of file tlb.cc.
References gem5::ArmISA::mode, and gem5::MipsISA::vaddr.
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overridevirtual |
Implements gem5::BaseTLB.
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private |
Definition at line 307 of file tlb.cc.
References DPRINTF, gem5::ArmISA::e, gem5::RiscvISA::getVPNFromVAddr(), gem5::ArmISA::mask, gem5::RiscvISA::MISCREG_SATP, gem5::RiscvISA::MISCREG_STATUS, gem5::ArmISA::mode, gem5::NoFault, gem5::ThreadContext::readMiscReg(), gem5::ArmISA::status, and gem5::MipsISA::vaddr.
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private |
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overridevirtual |
Do post-translation physical address finalization.
This method is used by some architectures that need post-translation massaging of physical addresses. For example, X86 uses this to remap physical addresses in the APIC range to a range of physical memory not normally available to real x86 implementations.
req | Request to updated in-place. |
tc | Thread context that created the request. |
mode | Request type (read/write/execute). |
Implements gem5::BaseTLB.
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overridevirtual |
Remove all entries from the TLB.
Implements gem5::BaseTLB.
PrivilegeMode gem5::TLB::getMemPriv | ( | ThreadContext * | tc, |
BaseMMU::Mode | mode | ||
) |
Definition at line 356 of file tlb.cc.
References gem5::RiscvISA::MISCREG_PRV, gem5::RiscvISA::MISCREG_STATUS, gem5::ArmISA::mode, gem5::ThreadContext::readMiscReg(), and gem5::ArmISA::status.
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overridevirtual |
Get the table walker port.
This is used for migrating port connections during a CPU takeOverFrom() call. For architectures that do not have a table walker, NULL is returned, hence the use of a pointer rather than a reference. For RISC-V this method will always return a valid port pointer.
Reimplemented from gem5::BaseTLB.
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inline |
For RV32, we follow what the specification said: When mapping between narrower and wider addresses, RISC-V zero-extends a narrower physical address to a wider size.
Definition at line 148 of file tlb.hh.
References gem5::bits(), gem5::ThreadContext::getIsaPtr(), gem5::RiscvISA::RV32, gem5::RiscvISA::ISA::rvType(), and gem5::RiscvISA::vaddr.
Walker * gem5::RiscvISA::TLB::getWalker | ( | ) |
Addr gem5::TLB::hiddenTranslateWithTLB | ( | Addr | vaddr, |
uint16_t | asid, | ||
Addr | xmode, | ||
BaseMMU::Mode | mode | ||
) |
Definition at line 298 of file tlb.cc.
References gem5::ArmISA::asid, gem5::ArmISA::e, gem5::RiscvISA::getVPNFromVAddr(), gem5::ArmISA::mask, gem5::ArmISA::mode, and gem5::MipsISA::vaddr.
Insert an entry into the TLB.
vpn | The virtual page number extracted from the address. It is shifted based on the page size. We assume the smallest defined page size and remove the upper bits of the virtual address that are not part of the page number. |
entry | The entry to insert. |
Definition at line 152 of file tlb.cc.
References gem5::RiscvISA::TlbEntry::asid, gem5::buildKey(), DPRINTF, gem5::RiscvISA::TlbEntry::logBytes, gem5::RiscvISA::TlbEntry::lruSeq, gem5::RiscvISA::TlbEntry::paddr, gem5::RiscvISA::TlbEntry::pte, gem5::RiscvISA::TlbEntry::size(), gem5::RiscvISA::TlbEntry::trieHandle, and gem5::RiscvISA::TlbEntry::vaddr.
TlbEntry * gem5::TLB::lookup | ( | Addr | vpn, |
uint16_t | asid, | ||
BaseMMU::Mode | mode, | ||
bool | hidden | ||
) |
Perform the tlb lookup.
vpn | The virtual page number extracted from the address. It is shifted based on the page size. We assume the smallest defined page size and remove the upper bits of the virtual address that are not part of the page number. |
asid | The address space identifier as specified by satp. |
mode | The mode of the memory operation. |
hidden | If the lookup should be hidden from the statistics. |
Definition at line 115 of file tlb.cc.
References gem5::ArmISA::asid, gem5::buildKey(), DPRINTF, gem5::RiscvISA::TlbEntry::lruSeq, gem5::ArmISA::mode, gem5::RiscvISA::TlbEntry::paddr, and gem5::RiscvISA::TlbEntry::size().
Referenced by gem5::RiscvISA::Walker::startWalkWrapper().
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inlineprivate |
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private |
Definition at line 238 of file tlb.cc.
References gem5::ArmISA::asid, DPRINTF, gem5::ArmISA::tlb, and gem5::MipsISA::vaddr.
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overridevirtual |
Serialize an object.
Output an object's state into the current checkpoint section.
cp | Checkpoint state |
Reimplemented from gem5::SimObject.
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inlineoverridevirtual |
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private |
we simply set the virtual address to physical address.
Definition at line 366 of file tlb.cc.
References gem5::FullSystem, gem5::ThreadContext::getProcessPtr(), gem5::RiscvISA::MISCREG_ISA, gem5::RiscvISA::MISCREG_SATP, gem5::ArmISA::mode, gem5::NoFault, gem5::ThreadContext::readMiscReg(), gem5::ThreadContext::readMiscRegNoEffect(), and gem5::MipsISA::vaddr.
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overridevirtual |
Implements gem5::BaseTLB.
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overridevirtual |
Reimplemented from gem5::BaseTLB.
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overridevirtual |
Implements gem5::BaseTLB.
Referenced by gem5::RiscvISA::Walker::startWalkWrapper().
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overridevirtual |
Unserialize an object.
Read an object's state from the current checkpoint section.
cp | Checkpoint state |
Reimplemented from gem5::SimObject.
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BasePMAChecker* gem5::RiscvISA::TLB::pma |
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