| _drainManager | gem5::Drainable | private |
| _drainState | gem5::Drainable | mutableprivate |
| _name | gem5::Named | private |
| _objNameResolver | gem5::SimObject | privatestatic |
| _params | gem5::SimObject | protected |
| addStat(statistics::Info *info) | gem5::statistics::Group | |
| addStatGroup(const char *name, Group *block) | gem5::statistics::Group | |
| atomic(SDMAQueue *q, sdmaAtomicHeader *header, sdmaAtomic *pkt) | gem5::SDMAEngine | |
| atomicData(SDMAQueue *q, sdmaAtomicHeader *header, sdmaAtomic *pkt, uint64_t *dmaBuffer) | gem5::SDMAEngine | |
| atomicDone(SDMAQueue *q, sdmaAtomicHeader *header, sdmaAtomic *pkt, uint64_t *dmaBuffer) | gem5::SDMAEngine | |
| cacheBlockSize() const | gem5::DmaDevice | inline |
| clockDomain | gem5::Clocked | private |
| Clocked(ClockDomain &clk_domain) | gem5::Clocked | inlineprotected |
| Clocked(Clocked &)=delete | gem5::Clocked | protected |
| clockEdge(Cycles cycles=Cycles(0)) const | gem5::Clocked | inline |
| ClockedObject(const ClockedObjectParams &p) | gem5::ClockedObject | |
| clockPeriod() const | gem5::Clocked | inline |
| clockPeriodUpdated() | gem5::Clocked | inlineprotectedvirtual |
| constFill(SDMAQueue *q, sdmaConstFill *pkt, uint32_t header) | gem5::SDMAEngine | |
| constFillDone(SDMAQueue *q, sdmaConstFill *pkt, uint8_t *fill_data) | gem5::SDMAEngine | |
| copy(SDMAQueue *q, sdmaCopy *pkt) | gem5::SDMAEngine | |
| copyDone(SDMAQueue *q, sdmaCopy *pkt, uint8_t *dmaBuffer) | gem5::SDMAEngine | |
| copyReadData(SDMAQueue *q, sdmaCopy *pkt, uint8_t *dmaBuffer) | gem5::SDMAEngine | |
| cur_vmid | gem5::SDMAEngine | |
| curCycle() const | gem5::Clocked | inline |
| currentSection() | gem5::Serializable | static |
| cycle | gem5::Clocked | mutableprivate |
| cyclesToTicks(Cycles c) const | gem5::Clocked | inline |
| deallocateRLCQueues() | gem5::SDMAEngine | |
| decodeHeader(SDMAQueue *q, uint32_t data) | gem5::SDMAEngine | |
| decodeNext(SDMAQueue *q) | gem5::SDMAEngine | |
| deschedule(Event &event) | gem5::EventManager | inline |
| deschedule(Event *event) | gem5::EventManager | inline |
| DmaDevice(const Params &p) | gem5::DmaDevice | |
| DmaFnPtr typedef | gem5::DmaVirtDevice | |
| dmaPending() const | gem5::DmaDevice | inline |
| dmaPort | gem5::DmaDevice | protected |
| dmaRead(Addr addr, int size, Event *event, uint8_t *data, uint32_t sid, uint32_t ssid, Tick delay=0) | gem5::DmaDevice | inline |
| dmaRead(Addr addr, int size, Event *event, uint8_t *data, Tick delay=0) | gem5::DmaDevice | inline |
| dmaReadVirt(Addr host_addr, unsigned size, DmaCallback *cb, void *data, Tick delay=0) | gem5::DmaVirtDevice | |
| dmaVirt(DmaFnPtr dmaFn, Addr host_addr, unsigned size, DmaCallback *cb, void *data, Tick delay=0) | gem5::DmaVirtDevice | |
| DmaVirtDevice(const Params &p) | gem5::DmaVirtDevice | inline |
| dmaWrite(Addr addr, int size, Event *event, uint8_t *data, uint32_t sid, uint32_t ssid, Tick delay=0) | gem5::DmaDevice | inline |
| dmaWrite(Addr addr, int size, Event *event, uint8_t *data, Tick delay=0) | gem5::DmaDevice | inline |
| dmaWriteVirt(Addr host_addr, unsigned size, DmaCallback *b, void *data, Tick delay=0) | gem5::DmaVirtDevice | |
| dmDrain() | gem5::Drainable | private |
| dmDrainResume() | gem5::Drainable | private |
| drain() override | gem5::SimObject | inlinevirtual |
| Drainable() | gem5::Drainable | protected |
| drainResume() | gem5::Drainable | inlineprotectedvirtual |
| drainState() const | gem5::Drainable | inline |
| EventManager(EventManager &em) | gem5::EventManager | inline |
| EventManager(EventManager *em) | gem5::EventManager | inline |
| EventManager(EventQueue *eq) | gem5::EventManager | inline |
| eventq | gem5::EventManager | protected |
| eventQueue() const | gem5::EventManager | inline |
| fence(SDMAQueue *q, sdmaFence *pkt) | gem5::SDMAEngine | |
| fenceDone(SDMAQueue *q, sdmaFence *pkt) | gem5::SDMAEngine | |
| find(const char *name) | gem5::SimObject | static |
| frequency() const | gem5::Clocked | inline |
| generateCheckpointOut(const std::string &cpt_dir, std::ofstream &outstream) | gem5::Serializable | static |
| getAddrRanges() const override | gem5::SDMAEngine | virtual |
| getDeviceAddress(Addr raw_addr) | gem5::SDMAEngine | |
| getGARTAddr(Addr addr) const | gem5::SDMAEngine | |
| getGfxBase() | gem5::SDMAEngine | inline |
| getGfxDoorbell() | gem5::SDMAEngine | inline |
| getGfxDoorbellOffset() | gem5::SDMAEngine | inline |
| getGfxRptr() | gem5::SDMAEngine | inline |
| getGfxWptr() | gem5::SDMAEngine | inline |
| getId() const | gem5::SDMAEngine | inline |
| getIHClientId(int _id) | gem5::SDMAEngine | |
| getMmioBase() | gem5::SDMAEngine | inline |
| getMmioSize() | gem5::SDMAEngine | inline |
| getPageBase() | gem5::SDMAEngine | inline |
| getPageDoorbell() | gem5::SDMAEngine | inline |
| getPageDoorbellOffset() | gem5::SDMAEngine | inline |
| getPageRptr() | gem5::SDMAEngine | inline |
| getPageWptr() | gem5::SDMAEngine | inline |
| getPort(const std::string &if_name, PortID idx=InvalidPortID) override | gem5::DmaDevice | virtual |
| getProbeManager() | gem5::SimObject | |
| getSimObjectResolver() | gem5::SimObject | static |
| getStatGroups() const | gem5::statistics::Group | |
| getStats() const | gem5::statistics::Group | |
| gfx | gem5::SDMAEngine | private |
| gfxBase | gem5::SDMAEngine | private |
| gfxDoorbell | gem5::SDMAEngine | private |
| gfxDoorbellOffset | gem5::SDMAEngine | private |
| gfxIb | gem5::SDMAEngine | private |
| gfxRptr | gem5::SDMAEngine | private |
| gfxWptr | gem5::SDMAEngine | private |
| gpuDevice | gem5::SDMAEngine | private |
| Group()=delete | gem5::statistics::Group | |
| Group(const Group &)=delete | gem5::statistics::Group | |
| Group(Group *parent, const char *name=nullptr) | gem5::statistics::Group | |
| id | gem5::SDMAEngine | private |
| indirectBuffer(SDMAQueue *q, sdmaIndirectBuffer *pkt) | gem5::SDMAEngine | |
| init() override | gem5::DmaDevice | virtual |
| initState() | gem5::SimObject | virtual |
| loadState(CheckpointIn &cp) | gem5::SimObject | virtual |
| memInvalidate() | gem5::SimObject | inlinevirtual |
| memWriteback() | gem5::SimObject | inlinevirtual |
| mergedParent | gem5::statistics::Group | private |
| mergedStatGroups | gem5::statistics::Group | private |
| mergeStatGroup(Group *block) | gem5::statistics::Group | |
| mmioBase | gem5::SDMAEngine | private |
| mmioSize | gem5::SDMAEngine | private |
| name() const | gem5::Named | inlinevirtual |
| Named(const std::string &name_) | gem5::Named | inline |
| nextCycle() const | gem5::Clocked | inline |
| notifyFork() | gem5::Drainable | inlinevirtual |
| gem5::operator=(const Group &)=delete | gem5::statistics::Group | |
| gem5::Clocked::operator=(Clocked &)=delete | gem5::Clocked | protected |
| page | gem5::SDMAEngine | private |
| pageBase | gem5::SDMAEngine | private |
| pageDoorbell | gem5::SDMAEngine | private |
| pageDoorbellOffset | gem5::SDMAEngine | private |
| pageIb | gem5::SDMAEngine | private |
| pageRptr | gem5::SDMAEngine | private |
| pageWptr | gem5::SDMAEngine | private |
| Params typedef | gem5::DmaDevice | |
| params() const | gem5::SimObject | inline |
| path | gem5::Serializable | privatestatic |
| PioDevice(const Params &p) | gem5::PioDevice | |
| pioPort | gem5::PioDevice | protected |
| pollRegMem(SDMAQueue *q, sdmaPollRegMemHeader *header, sdmaPollRegMem *pkt) | gem5::SDMAEngine | |
| pollRegMemFunc(uint32_t value, uint32_t reference, uint32_t func) | gem5::SDMAEngine | |
| pollRegMemRead(SDMAQueue *q, sdmaPollRegMemHeader *header, sdmaPollRegMem *pkt, uint32_t dma_buffer, int count) | gem5::SDMAEngine | |
| powerState | gem5::ClockedObject | |
| preDumpStats() | gem5::statistics::Group | virtual |
| probeManager | gem5::SimObject | private |
| processGfx(Addr wptrOffset) | gem5::SDMAEngine | |
| processPage(Addr wptrOffset) | gem5::SDMAEngine | |
| processRLC(Addr doorbellOffset, Addr wptrOffset) | gem5::SDMAEngine | |
| processRLC0(Addr wptrOffset) | gem5::SDMAEngine | private |
| processRLC1(Addr wptrOffset) | gem5::SDMAEngine | private |
| ptePde(SDMAQueue *q, sdmaPtePde *pkt) | gem5::SDMAEngine | |
| ptePdeDone(SDMAQueue *q, sdmaPtePde *pkt, uint64_t *dmaBuffer) | gem5::SDMAEngine | |
| read(PacketPtr pkt) override | gem5::SDMAEngine | inlinevirtual |
| registerRLCQueue(Addr doorbell, Addr mqdAddr, SDMAQueueDesc *mqd) | gem5::SDMAEngine | |
| regProbeListeners() | gem5::SimObject | virtual |
| regProbePoints() | gem5::SimObject | virtual |
| regStats() | gem5::statistics::Group | virtual |
| reschedule(Event &event, Tick when, bool always=false) | gem5::EventManager | inline |
| reschedule(Event *event, Tick when, bool always=false) | gem5::EventManager | inline |
| resetClock() const | gem5::Clocked | inlineprotected |
| resetStats() | gem5::statistics::Group | virtual |
| resolveStat(std::string name) const | gem5::statistics::Group | |
| rlc0 | gem5::SDMAEngine | private |
| rlc0Ib | gem5::SDMAEngine | private |
| rlc1 | gem5::SDMAEngine | private |
| rlc1Ib | gem5::SDMAEngine | private |
| rlcInfo | gem5::SDMAEngine | private |
| schedule(Event &event, Tick when) | gem5::EventManager | inline |
| schedule(Event *event, Tick when) | gem5::EventManager | inline |
| SDMAEngine(const SDMAEngineParams &p) | gem5::SDMAEngine | |
| SDMAGfx enum value | gem5::SDMAEngine | private |
| SDMAPage enum value | gem5::SDMAEngine | private |
| SDMAType enum name | gem5::SDMAEngine | private |
| Serializable() | gem5::Serializable | |
| serialize(CheckpointOut &cp) const override | gem5::SDMAEngine | virtual |
| serializeAll(const std::string &cpt_dir) | gem5::SimObject | static |
| serializeSection(CheckpointOut &cp, const char *name) const | gem5::Serializable | |
| serializeSection(CheckpointOut &cp, const std::string &name) const | gem5::Serializable | inline |
| setCurTick(Tick newVal) | gem5::EventManager | inline |
| setGfxBaseHi(uint32_t data) | gem5::SDMAEngine | |
| setGfxBaseLo(uint32_t data) | gem5::SDMAEngine | |
| setGfxDoorbellHi(uint32_t data) | gem5::SDMAEngine | |
| setGfxDoorbellLo(uint32_t data) | gem5::SDMAEngine | |
| setGfxDoorbellOffsetHi(uint32_t data) | gem5::SDMAEngine | |
| setGfxDoorbellOffsetLo(uint32_t data) | gem5::SDMAEngine | |
| setGfxRptrHi(uint32_t data) | gem5::SDMAEngine | |
| setGfxRptrLo(uint32_t data) | gem5::SDMAEngine | |
| setGfxSize(uint32_t data) | gem5::SDMAEngine | |
| setGfxWptrHi(uint32_t data) | gem5::SDMAEngine | |
| setGfxWptrLo(uint32_t data) | gem5::SDMAEngine | |
| setGPUDevice(AMDGPUDevice *gpu_device) | gem5::SDMAEngine | |
| setId(int _id) | gem5::SDMAEngine | inline |
| setPageBaseHi(uint32_t data) | gem5::SDMAEngine | |
| setPageBaseLo(uint32_t data) | gem5::SDMAEngine | |
| setPageDoorbellHi(uint32_t data) | gem5::SDMAEngine | |
| setPageDoorbellLo(uint32_t data) | gem5::SDMAEngine | |
| setPageDoorbellOffsetHi(uint32_t data) | gem5::SDMAEngine | |
| setPageDoorbellOffsetLo(uint32_t data) | gem5::SDMAEngine | |
| setPageRptrHi(uint32_t data) | gem5::SDMAEngine | |
| setPageRptrLo(uint32_t data) | gem5::SDMAEngine | |
| setPageSize(uint32_t data) | gem5::SDMAEngine | |
| setPageWptrHi(uint32_t data) | gem5::SDMAEngine | |
| setPageWptrLo(uint32_t data) | gem5::SDMAEngine | |
| setSimObjectResolver(SimObjectResolver *resolver) | gem5::SimObject | static |
| signalDrainDone() const | gem5::Drainable | inlineprotected |
| SimObject(const Params &p) | gem5::SimObject | |
| SimObjectList typedef | gem5::SimObject | private |
| simObjectList | gem5::SimObject | privatestatic |
| srbmWrite(SDMAQueue *q, sdmaSRBMWriteHeader *header, sdmaSRBMWrite *pkt) | gem5::SDMAEngine | |
| startup() | gem5::SimObject | virtual |
| statGroups | gem5::statistics::Group | private |
| stats | gem5::statistics::Group | private |
| sys | gem5::PioDevice | protected |
| tick | gem5::Clocked | mutableprivate |
| ticksToCycles(Tick t) const | gem5::Clocked | inline |
| translate(Addr vaddr, Addr size) override | gem5::SDMAEngine | virtual |
| trap(SDMAQueue *q, sdmaTrap *pkt) | gem5::SDMAEngine | |
| unregisterRLCQueue(Addr doorbell) | gem5::SDMAEngine | |
| unserialize(CheckpointIn &cp) override | gem5::SDMAEngine | virtual |
| unserializeSection(CheckpointIn &cp, const char *name) | gem5::Serializable | |
| unserializeSection(CheckpointIn &cp, const std::string &name) | gem5::Serializable | inline |
| update() const | gem5::Clocked | inlineprivate |
| updateClockPeriod() | gem5::Clocked | inline |
| voltage() const | gem5::Clocked | inline |
| wakeupEventQueue(Tick when=(Tick) -1) | gem5::EventManager | inline |
| walker | gem5::SDMAEngine | private |
| write(PacketPtr pkt) override | gem5::SDMAEngine | inlinevirtual |
| write(SDMAQueue *q, sdmaWrite *pkt) | gem5::SDMAEngine | |
| writeDone(SDMAQueue *q, sdmaWrite *pkt, uint32_t *dmaBuffer) | gem5::SDMAEngine | |
| writeMMIO(PacketPtr pkt, Addr mmio_offset) | gem5::SDMAEngine | |
| writeReadData(SDMAQueue *q, sdmaWrite *pkt, uint32_t *dmaBuffer) | gem5::SDMAEngine | |
| ~Clocked() | gem5::Clocked | inlineprotectedvirtual |
| ~DmaDevice()=default | gem5::DmaDevice | virtual |
| ~DmaVirtDevice() | gem5::DmaVirtDevice | inlinevirtual |
| ~Drainable() | gem5::Drainable | protectedvirtual |
| ~Group() | gem5::statistics::Group | virtual |
| ~Named()=default | gem5::Named | virtual |
| ~PioDevice() | gem5::PioDevice | virtual |
| ~Serializable() | gem5::Serializable | virtual |
| ~SimObject() | gem5::SimObject | virtual |