gem5  v21.1.0.2
gem5::X86ISA::GpuTLB Member List

This is the complete list of members for gem5::X86ISA::GpuTLB, including all inherited members.

_drainManagergem5::Drainableprivate
_drainStategem5::Drainablemutableprivate
_namegem5::Namedprivate
_objNameResolvergem5::SimObjectprivatestatic
_paramsgem5::SimObjectprotected
accessDistancegem5::X86ISA::GpuTLBprotected
AccessPatternTable typedefgem5::X86ISA::GpuTLB
addStat(statistics::Info *info)gem5::statistics::Group
addStatGroup(const char *name, Group *block)gem5::statistics::Group
allocationPolicygem5::X86ISA::GpuTLBprotected
assocgem5::X86ISA::GpuTLBprotected
cleanup()gem5::X86ISA::GpuTLB
cleanupEventgem5::X86ISA::GpuTLB
cleanupQueuegem5::X86ISA::GpuTLB
clockDomaingem5::Clockedprivate
Clocked(ClockDomain &clk_domain)gem5::Clockedinlineprotected
Clocked(Clocked &)=deletegem5::Clockedprotected
clockEdge(Cycles cycles=Cycles(0)) constgem5::Clockedinline
ClockedObject(const ClockedObjectParams &p)gem5::ClockedObject
clockPeriod() constgem5::Clockedinline
clockPeriodUpdated()gem5::Clockedinlineprotectedvirtual
configAddressgem5::X86ISA::GpuTLBprotected
cpuSidePortgem5::X86ISA::GpuTLB
curCycle() constgem5::Clockedinline
currentSection()gem5::Serializablestatic
cyclegem5::Clockedmutableprivate
cyclesToTicks(Cycles c) constgem5::Clockedinline
demapPage(Addr va, uint64_t asn)gem5::X86ISA::GpuTLB
deschedule(Event &event)gem5::EventManagerinline
deschedule(Event *event)gem5::EventManagerinline
dmDrain()gem5::Drainableprivate
dmDrainResume()gem5::Drainableprivate
doMmuRegRead(ThreadContext *tc, Packet *pkt)gem5::X86ISA::GpuTLB
doMmuRegWrite(ThreadContext *tc, Packet *pkt)gem5::X86ISA::GpuTLB
drain() overridegem5::SimObjectinlinevirtual
Drainable()gem5::Drainableprotected
drainResume()gem5::Drainableinlineprotectedvirtual
drainState() constgem5::Drainableinline
dumpAll()gem5::X86ISA::GpuTLB
entryListgem5::X86ISA::GpuTLBprotected
EntryList typedefgem5::X86ISA::GpuTLBprotected
EventManager(EventManager &em)gem5::EventManagerinline
EventManager(EventManager *em)gem5::EventManagerinline
EventManager(EventQueue *eq)gem5::EventManagerinline
eventqgem5::EventManagerprotected
eventQueue() constgem5::EventManagerinline
exitCallback()gem5::X86ISA::GpuTLB
exitEventgem5::X86ISA::GpuTLB
FAgem5::X86ISA::GpuTLBprotected
find(const char *name)gem5::SimObjectstatic
freeListgem5::X86ISA::GpuTLBprotected
frequency() constgem5::Clockedinline
generateCheckpointOut(const std::string &cpt_dir, std::ofstream &outstream)gem5::Serializablestatic
getPort(const std::string &if_name, PortID idx=InvalidPortID) overridegem5::X86ISA::GpuTLBvirtual
getProbeManager()gem5::SimObject
getSimObjectResolver()gem5::SimObjectstatic
getStatGroups() constgem5::statistics::Group
getStats() constgem5::statistics::Group
getWalker()gem5::X86ISA::GpuTLB
GpuTLB(const Params &p)gem5::X86ISA::GpuTLB
Group()=deletegem5::statistics::Group
Group(const Group &)=deletegem5::statistics::Group
Group(Group *parent, const char *name=nullptr)gem5::statistics::Group
handleFuncTranslationReturn(PacketPtr pkt, tlbOutcome outcome)gem5::X86ISA::GpuTLB
handleTranslationReturn(Addr addr, tlbOutcome outcome, PacketPtr pkt)gem5::X86ISA::GpuTLB
hasMemSidePortgem5::X86ISA::GpuTLBprotected
hitLatencygem5::X86ISA::GpuTLB
init()gem5::SimObjectvirtual
initState()gem5::SimObjectvirtual
insert(Addr vpn, TlbEntry &entry)gem5::X86ISA::GpuTLB
invalidateAll()gem5::X86ISA::GpuTLB
invalidateNonGlobal()gem5::X86ISA::GpuTLB
issueTLBLookup(PacketPtr pkt)gem5::X86ISA::GpuTLB
issueTranslation()gem5::X86ISA::GpuTLB
loadState(CheckpointIn &cp)gem5::SimObjectvirtual
lookup(Addr va, bool update_lru=true)gem5::X86ISA::GpuTLB
lookupIt(Addr va, bool update_lru=true)gem5::X86ISA::GpuTLBprotected
maxCoalescedReqsgem5::X86ISA::GpuTLB
memInvalidate()gem5::SimObjectinlinevirtual
memSidePortgem5::X86ISA::GpuTLB
memWriteback()gem5::SimObjectinlinevirtual
mergedParentgem5::statistics::Groupprivate
mergedStatGroupsgem5::statistics::Groupprivate
mergeStatGroup(Group *block)gem5::statistics::Group
MISS_RETURN enum valuegem5::X86ISA::GpuTLB
missLatency1gem5::X86ISA::GpuTLB
missLatency2gem5::X86ISA::GpuTLB
Mode typedefgem5::X86ISA::GpuTLB
name() constgem5::Namedinlinevirtual
Named(const std::string &name_)gem5::Namedinline
nextCycle() constgem5::Clockedinline
notifyFork()gem5::Drainableinlinevirtual
numSetsgem5::X86ISA::GpuTLBprotected
gem5::operator=(const Group &)=deletegem5::statistics::Group
gem5::Clocked::operator=(Clocked &)=deletegem5::Clockedprotected
outstandingReqsgem5::X86ISA::GpuTLB
PAGE_WALK enum valuegem5::X86ISA::GpuTLB
pagingProtectionChecks(ThreadContext *tc, PacketPtr pkt, TlbEntry *tlb_entry, Mode mode)gem5::X86ISA::GpuTLB
params() constgem5::SimObjectinline
Params typedefgem5::X86ISA::GpuTLB
pathgem5::Serializableprivatestatic
powerStategem5::ClockedObject
preDumpStats()gem5::statistics::Groupvirtual
printAccessPattern()gem5::X86ISA::GpuTLB
probeManagergem5::SimObjectprivate
regProbeListeners()gem5::SimObjectvirtual
regProbePoints()gem5::SimObjectvirtual
regStats()gem5::statistics::Groupvirtual
reschedule(Event &event, Tick when, bool always=false)gem5::EventManagerinline
reschedule(Event *event, Tick when, bool always=false)gem5::EventManagerinline
resetClock() constgem5::Clockedinlineprotected
resetStats()gem5::statistics::Groupvirtual
resolveStat(std::string name) constgem5::statistics::Group
schedule(Event &event, Tick when)gem5::EventManagerinline
schedule(Event *event, Tick when)gem5::EventManagerinline
Serializable()gem5::Serializable
serialize(CheckpointOut &cp) const overridegem5::X86ISA::GpuTLBvirtual
serializeAll(const std::string &cpt_dir)gem5::SimObjectstatic
serializeSection(CheckpointOut &cp, const char *name) constgem5::Serializable
serializeSection(CheckpointOut &cp, const std::string &name) constgem5::Serializableinline
setConfigAddress(uint32_t addr)gem5::X86ISA::GpuTLB
setCurTick(Tick newVal)gem5::EventManagerinline
setMaskgem5::X86ISA::GpuTLBprotected
setSimObjectResolver(SimObjectResolver *resolver)gem5::SimObjectstatic
signalDrainDone() constgem5::Drainableinlineprotected
SimObject(const Params &p)gem5::SimObject
SimObjectList typedefgem5::SimObjectprivate
simObjectListgem5::SimObjectprivatestatic
sizegem5::X86ISA::GpuTLBprotected
startup()gem5::SimObjectvirtual
statGroupsgem5::statistics::Groupprivate
statsgem5::X86ISA::GpuTLBprotected
tickgem5::Clockedmutableprivate
ticksToCycles(Tick t) constgem5::Clockedinline
tlbgem5::X86ISA::GpuTLBprotected
TLB_HIT enum valuegem5::X86ISA::GpuTLB
TLB_MISS enum valuegem5::X86ISA::GpuTLB
TLBFootprintgem5::X86ISA::GpuTLB
tlbLookup(const RequestPtr &req, ThreadContext *tc, bool update_stats)gem5::X86ISA::GpuTLB
tlbOutcome enum namegem5::X86ISA::GpuTLB
translate(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode, bool &delayedResponse, bool timing, int &latency)gem5::X86ISA::GpuTLBprotected
translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode, int &latency)gem5::X86ISA::GpuTLB
translateInt(bool read, const RequestPtr &req, ThreadContext *tc)gem5::X86ISA::GpuTLBprotected
translateTiming(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode, int &latency)gem5::X86ISA::GpuTLB
translationReturn(Addr virtPageAddr, tlbOutcome outcome, PacketPtr pkt)gem5::X86ISA::GpuTLB
translationReturnEventgem5::X86ISA::GpuTLB
unserialize(CheckpointIn &cp) overridegem5::X86ISA::GpuTLBvirtual
unserializeSection(CheckpointIn &cp, const char *name)gem5::Serializable
unserializeSection(CheckpointIn &cp, const std::string &name)gem5::Serializableinline
update() constgem5::Clockedinlineprivate
updateClockPeriod()gem5::Clockedinline
updatePageFootprint(Addr virt_page_addr)gem5::X86ISA::GpuTLB
updatePhysAddresses(Addr virt_page_addr, TlbEntry *tlb_entry, Addr phys_page_addr)gem5::X86ISA::GpuTLB
voltage() constgem5::Clockedinline
wakeupEventQueue(Tick when=(Tick) -1)gem5::EventManagerinline
Walker classgem5::X86ISA::GpuTLBfriend
walkergem5::X86ISA::GpuTLBprotected
~Clocked()gem5::Clockedinlineprotectedvirtual
~Drainable()gem5::Drainableprotectedvirtual
~GpuTLB()gem5::X86ISA::GpuTLB
~Group()gem5::statistics::Groupvirtual
~Named()=defaultgem5::Namedvirtual
~Serializable()gem5::Serializablevirtual
~SimObject()gem5::SimObjectvirtual

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