| _drainManager | gem5::Drainable | private |
| _drainState | gem5::Drainable | mutableprivate |
| _name | gem5::Named | private |
| _objNameResolver | gem5::SimObject | privatestatic |
| _params | gem5::SimObject | protected |
| accessDistance | gem5::X86ISA::GpuTLB | protected |
| AccessPatternTable typedef | gem5::X86ISA::GpuTLB | |
| addStat(statistics::Info *info) | gem5::statistics::Group | |
| addStatGroup(const char *name, Group *block) | gem5::statistics::Group | |
| allocationPolicy | gem5::X86ISA::GpuTLB | protected |
| assoc | gem5::X86ISA::GpuTLB | protected |
| cleanup() | gem5::X86ISA::GpuTLB | |
| cleanupEvent | gem5::X86ISA::GpuTLB | |
| cleanupQueue | gem5::X86ISA::GpuTLB | |
| clockDomain | gem5::Clocked | private |
| Clocked(ClockDomain &clk_domain) | gem5::Clocked | inlineprotected |
| Clocked(Clocked &)=delete | gem5::Clocked | protected |
| clockEdge(Cycles cycles=Cycles(0)) const | gem5::Clocked | inline |
| ClockedObject(const ClockedObjectParams &p) | gem5::ClockedObject | |
| clockPeriod() const | gem5::Clocked | inline |
| clockPeriodUpdated() | gem5::Clocked | inlineprotectedvirtual |
| configAddress | gem5::X86ISA::GpuTLB | protected |
| cpuSidePort | gem5::X86ISA::GpuTLB | |
| curCycle() const | gem5::Clocked | inline |
| currentSection() | gem5::Serializable | static |
| cycle | gem5::Clocked | mutableprivate |
| cyclesToTicks(Cycles c) const | gem5::Clocked | inline |
| demapPage(Addr va, uint64_t asn) | gem5::X86ISA::GpuTLB | |
| deschedule(Event &event) | gem5::EventManager | inline |
| deschedule(Event *event) | gem5::EventManager | inline |
| dmDrain() | gem5::Drainable | private |
| dmDrainResume() | gem5::Drainable | private |
| doMmuRegRead(ThreadContext *tc, Packet *pkt) | gem5::X86ISA::GpuTLB | |
| doMmuRegWrite(ThreadContext *tc, Packet *pkt) | gem5::X86ISA::GpuTLB | |
| drain() override | gem5::SimObject | inlinevirtual |
| Drainable() | gem5::Drainable | protected |
| drainResume() | gem5::Drainable | inlineprotectedvirtual |
| drainState() const | gem5::Drainable | inline |
| dumpAll() | gem5::X86ISA::GpuTLB | |
| EntryList typedef | gem5::X86ISA::GpuTLB | protected |
| entryList | gem5::X86ISA::GpuTLB | protected |
| EventManager(EventManager &em) | gem5::EventManager | inline |
| EventManager(EventManager *em) | gem5::EventManager | inline |
| EventManager(EventQueue *eq) | gem5::EventManager | inline |
| eventq | gem5::EventManager | protected |
| eventQueue() const | gem5::EventManager | inline |
| exitCallback() | gem5::X86ISA::GpuTLB | |
| exitEvent | gem5::X86ISA::GpuTLB | |
| FA | gem5::X86ISA::GpuTLB | protected |
| find(const char *name) | gem5::SimObject | static |
| freeList | gem5::X86ISA::GpuTLB | protected |
| frequency() const | gem5::Clocked | inline |
| generateCheckpointOut(const std::string &cpt_dir, std::ofstream &outstream) | gem5::Serializable | static |
| getPort(const std::string &if_name, PortID idx=InvalidPortID) override | gem5::X86ISA::GpuTLB | virtual |
| getProbeManager() | gem5::SimObject | |
| getSimObjectResolver() | gem5::SimObject | static |
| getStatGroups() const | gem5::statistics::Group | |
| getStats() const | gem5::statistics::Group | |
| getWalker() | gem5::X86ISA::GpuTLB | |
| GpuTLB(const Params &p) | gem5::X86ISA::GpuTLB | |
| Group()=delete | gem5::statistics::Group | |
| Group(const Group &)=delete | gem5::statistics::Group | |
| Group(Group *parent, const char *name=nullptr) | gem5::statistics::Group | |
| handleFuncTranslationReturn(PacketPtr pkt, tlbOutcome outcome) | gem5::X86ISA::GpuTLB | |
| handleTranslationReturn(Addr addr, tlbOutcome outcome, PacketPtr pkt) | gem5::X86ISA::GpuTLB | |
| hasMemSidePort | gem5::X86ISA::GpuTLB | protected |
| hitLatency | gem5::X86ISA::GpuTLB | |
| init() | gem5::SimObject | virtual |
| initState() | gem5::SimObject | virtual |
| insert(Addr vpn, TlbEntry &entry) | gem5::X86ISA::GpuTLB | |
| invalidateAll() | gem5::X86ISA::GpuTLB | |
| invalidateNonGlobal() | gem5::X86ISA::GpuTLB | |
| issueTLBLookup(PacketPtr pkt) | gem5::X86ISA::GpuTLB | |
| issueTranslation() | gem5::X86ISA::GpuTLB | |
| loadState(CheckpointIn &cp) | gem5::SimObject | virtual |
| lookup(Addr va, bool update_lru=true) | gem5::X86ISA::GpuTLB | |
| lookupIt(Addr va, bool update_lru=true) | gem5::X86ISA::GpuTLB | protected |
| maxCoalescedReqs | gem5::X86ISA::GpuTLB | |
| memInvalidate() | gem5::SimObject | inlinevirtual |
| memSidePort | gem5::X86ISA::GpuTLB | |
| memWriteback() | gem5::SimObject | inlinevirtual |
| mergedParent | gem5::statistics::Group | private |
| mergedStatGroups | gem5::statistics::Group | private |
| mergeStatGroup(Group *block) | gem5::statistics::Group | |
| MISS_RETURN enum value | gem5::X86ISA::GpuTLB | |
| missLatency1 | gem5::X86ISA::GpuTLB | |
| missLatency2 | gem5::X86ISA::GpuTLB | |
| Mode typedef | gem5::X86ISA::GpuTLB | |
| name() const | gem5::Named | inlinevirtual |
| Named(const std::string &name_) | gem5::Named | inline |
| nextCycle() const | gem5::Clocked | inline |
| notifyFork() | gem5::Drainable | inlinevirtual |
| numSets | gem5::X86ISA::GpuTLB | protected |
| gem5::operator=(const Group &)=delete | gem5::statistics::Group | |
| gem5::Clocked::operator=(Clocked &)=delete | gem5::Clocked | protected |
| outstandingReqs | gem5::X86ISA::GpuTLB | |
| PAGE_WALK enum value | gem5::X86ISA::GpuTLB | |
| pagingProtectionChecks(ThreadContext *tc, PacketPtr pkt, TlbEntry *tlb_entry, Mode mode) | gem5::X86ISA::GpuTLB | |
| Params typedef | gem5::X86ISA::GpuTLB | |
| params() const | gem5::SimObject | inline |
| path | gem5::Serializable | privatestatic |
| powerState | gem5::ClockedObject | |
| preDumpStats() | gem5::statistics::Group | virtual |
| printAccessPattern() | gem5::X86ISA::GpuTLB | |
| probeManager | gem5::SimObject | private |
| regProbeListeners() | gem5::SimObject | virtual |
| regProbePoints() | gem5::SimObject | virtual |
| regStats() | gem5::statistics::Group | virtual |
| reschedule(Event &event, Tick when, bool always=false) | gem5::EventManager | inline |
| reschedule(Event *event, Tick when, bool always=false) | gem5::EventManager | inline |
| resetClock() const | gem5::Clocked | inlineprotected |
| resetStats() | gem5::statistics::Group | virtual |
| resolveStat(std::string name) const | gem5::statistics::Group | |
| schedule(Event &event, Tick when) | gem5::EventManager | inline |
| schedule(Event *event, Tick when) | gem5::EventManager | inline |
| Serializable() | gem5::Serializable | |
| serialize(CheckpointOut &cp) const override | gem5::X86ISA::GpuTLB | virtual |
| serializeAll(const std::string &cpt_dir) | gem5::SimObject | static |
| serializeSection(CheckpointOut &cp, const char *name) const | gem5::Serializable | |
| serializeSection(CheckpointOut &cp, const std::string &name) const | gem5::Serializable | inline |
| setConfigAddress(uint32_t addr) | gem5::X86ISA::GpuTLB | |
| setCurTick(Tick newVal) | gem5::EventManager | inline |
| setMask | gem5::X86ISA::GpuTLB | protected |
| setSimObjectResolver(SimObjectResolver *resolver) | gem5::SimObject | static |
| signalDrainDone() const | gem5::Drainable | inlineprotected |
| SimObject(const Params &p) | gem5::SimObject | |
| simObjectList | gem5::SimObject | privatestatic |
| SimObjectList typedef | gem5::SimObject | private |
| size | gem5::X86ISA::GpuTLB | protected |
| startup() | gem5::SimObject | virtual |
| statGroups | gem5::statistics::Group | private |
| stats | gem5::X86ISA::GpuTLB | protected |
| tick | gem5::Clocked | mutableprivate |
| ticksToCycles(Tick t) const | gem5::Clocked | inline |
| tlb | gem5::X86ISA::GpuTLB | protected |
| TLB_HIT enum value | gem5::X86ISA::GpuTLB | |
| TLB_MISS enum value | gem5::X86ISA::GpuTLB | |
| TLBFootprint | gem5::X86ISA::GpuTLB | |
| tlbLookup(const RequestPtr &req, ThreadContext *tc, bool update_stats) | gem5::X86ISA::GpuTLB | |
| tlbOutcome enum name | gem5::X86ISA::GpuTLB | |
| translate(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode, bool &delayedResponse, bool timing, int &latency) | gem5::X86ISA::GpuTLB | protected |
| translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode, int &latency) | gem5::X86ISA::GpuTLB | |
| translateInt(bool read, const RequestPtr &req, ThreadContext *tc) | gem5::X86ISA::GpuTLB | protected |
| translateTiming(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode, int &latency) | gem5::X86ISA::GpuTLB | |
| translationReturn(Addr virtPageAddr, tlbOutcome outcome, PacketPtr pkt) | gem5::X86ISA::GpuTLB | |
| translationReturnEvent | gem5::X86ISA::GpuTLB | |
| unserialize(CheckpointIn &cp) override | gem5::X86ISA::GpuTLB | virtual |
| unserializeSection(CheckpointIn &cp, const char *name) | gem5::Serializable | |
| unserializeSection(CheckpointIn &cp, const std::string &name) | gem5::Serializable | inline |
| update() const | gem5::Clocked | inlineprivate |
| updateClockPeriod() | gem5::Clocked | inline |
| updatePageFootprint(Addr virt_page_addr) | gem5::X86ISA::GpuTLB | |
| updatePhysAddresses(Addr virt_page_addr, TlbEntry *tlb_entry, Addr phys_page_addr) | gem5::X86ISA::GpuTLB | |
| voltage() const | gem5::Clocked | inline |
| wakeupEventQueue(Tick when=(Tick) -1) | gem5::EventManager | inline |
| walker | gem5::X86ISA::GpuTLB | protected |
| Walker class | gem5::X86ISA::GpuTLB | friend |
| ~Clocked() | gem5::Clocked | inlineprotectedvirtual |
| ~Drainable() | gem5::Drainable | protectedvirtual |
| ~GpuTLB() | gem5::X86ISA::GpuTLB | |
| ~Group() | gem5::statistics::Group | virtual |
| ~Named()=default | gem5::Named | virtual |
| ~Serializable() | gem5::Serializable | virtual |
| ~SimObject() | gem5::SimObject | virtual |