#include <tlb.hh>

Inheritance diagram for gem5::X86ISA::GpuTLB:

Classes
struct	AccessInfo
	This hash map will use the virtual page address as a key and will keep track of total number of accesses per page. More...

class	CpuSidePort

struct	GpuTLBStats

class	MemSidePort
	MemSidePort is the TLB Port closer to the memory side If this is a last level TLB then this port will not be connected. More...

class	TLBEvent

class	Translation

Public Types
enum	tlbOutcome { TLB_HIT , TLB_MISS , PAGE_WALK , MISS_RETURN }

typedef X86GPUTLBParams	Params

typedef enum BaseMMU::Mode	Mode

typedef std::unordered_map< Addr, AccessInfo >	AccessPatternTable

Public Types inherited from gem5::ClockedObject
using	Params = ClockedObjectParams
	Parameters of ClockedObject. More...

Public Types inherited from gem5::SimObject
typedef SimObjectParams	Params

Public Member Functions
	GpuTLB (const Params &p)

	~GpuTLB ()

void	dumpAll ()

TlbEntry *	lookup (Addr va, bool update_lru=true)

void	setConfigAddress (uint32_t addr)

Walker *	getWalker ()

void	invalidateAll ()

void	invalidateNonGlobal ()

void	demapPage (Addr va, uint64_t asn)

void	updatePageFootprint (Addr virt_page_addr)

void	printAccessPattern ()

Fault	translateAtomic (const RequestPtr &req, ThreadContext *tc, Mode mode, int &latency)

void	translateTiming (const RequestPtr &req, ThreadContext tc, Translation translation, Mode mode, int &latency)

Tick	doMmuRegRead (ThreadContext tc, Packet pkt)

Tick	doMmuRegWrite (ThreadContext tc, Packet pkt)

TlbEntry *	insert (Addr vpn, TlbEntry &entry)

virtual void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...

virtual void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...

void	issueTranslation ()

bool	tlbLookup (const RequestPtr &req, ThreadContext *tc, bool update_stats)
	TLB_lookup will only perform a TLB lookup returning true on a TLB hit and false on a TLB miss. More...

void	handleTranslationReturn (Addr addr, tlbOutcome outcome, PacketPtr pkt)
	handleTranslationReturn is called on a TLB hit, when a TLB miss returns or when a page fault returns. More...

void	handleFuncTranslationReturn (PacketPtr pkt, tlbOutcome outcome)
	handleFuncTranslationReturn is called on a TLB hit, when a TLB miss returns or when a page fault returns. More...

void	pagingProtectionChecks (ThreadContext tc, PacketPtr pkt, TlbEntry tlb_entry, Mode mode)
	Do Paging protection checks. More...

void	updatePhysAddresses (Addr virt_page_addr, TlbEntry *tlb_entry, Addr phys_page_addr)

void	issueTLBLookup (PacketPtr pkt)
	Do the TLB lookup for this coalesced request and schedule another event <TLB access latency> cycles later. More...

Port &	getPort (const std::string &if_name, PortID idx=InvalidPortID) override
	Get a port with a given name and index. More...

void	translationReturn (Addr virtPageAddr, tlbOutcome outcome, PacketPtr pkt)
	A TLBEvent is scheduled after the TLB lookup and helps us take the appropriate actions: (e.g., update TLB on a hit, send request to lower level TLB on a miss, or start a page walk if this was the last-level TLB). More...

void	cleanup ()

void	exitCallback ()

Public Member Functions inherited from gem5::ClockedObject
	ClockedObject (const ClockedObjectParams &p)

void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...

void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...

Public Member Functions inherited from gem5::SimObject
const Params &	params () const

	SimObject (const Params &p)

virtual	~SimObject ()

virtual void	init ()
	init() is called after all C++ SimObjects have been created and all ports are connected. More...

virtual void	loadState (CheckpointIn &cp)
	loadState() is called on each SimObject when restoring from a checkpoint. More...

virtual void	initState ()
	initState() is called on each SimObject when not restoring from a checkpoint. More...

virtual void	regProbePoints ()
	Register probe points for this object. More...

virtual void	regProbeListeners ()
	Register probe listeners for this object. More...

ProbeManager *	getProbeManager ()
	Get the probe manager for this object. More...

virtual void	startup ()
	startup() is the final initialization call before simulation. More...

DrainState	drain () override
	Provide a default implementation of the drain interface for objects that don't need draining. More...

virtual void	memWriteback ()
	Write back dirty buffers to memory using functional writes. More...

virtual void	memInvalidate ()
	Invalidate the contents of memory buffers. More...

void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...

void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...

Public Member Functions inherited from gem5::EventManager
EventQueue *	eventQueue () const

void	schedule (Event &event, Tick when)

void	deschedule (Event &event)

void	reschedule (Event &event, Tick when, bool always=false)

void	schedule (Event *event, Tick when)

void	deschedule (Event *event)

void	reschedule (Event *event, Tick when, bool always=false)

void	wakeupEventQueue (Tick when=(Tick) -1)
	This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers. More...

void	setCurTick (Tick newVal)

	EventManager (EventManager &em)
	Event manger manages events in the event queue. More...

	EventManager (EventManager *em)

	EventManager (EventQueue *eq)

Public Member Functions inherited from gem5::Serializable
	Serializable ()

virtual	~Serializable ()

void	serializeSection (CheckpointOut &cp, const char *name) const
	Serialize an object into a new section. More...

void	serializeSection (CheckpointOut &cp, const std::string &name) const

void	unserializeSection (CheckpointIn &cp, const char *name)
	Unserialize an a child object. More...

void	unserializeSection (CheckpointIn &cp, const std::string &name)

Public Member Functions inherited from gem5::Drainable
DrainState	drainState () const
	Return the current drain state of an object. More...

virtual void	notifyFork ()
	Notify a child process of a fork. More...

Public Member Functions inherited from gem5::statistics::Group
	Group (Group parent, const char name=nullptr)
	Construct a new statistics group. More...

virtual	~Group ()

virtual void	regStats ()
	Callback to set stat parameters. More...

virtual void	resetStats ()
	Callback to reset stats. More...

virtual void	preDumpStats ()
	Callback before stats are dumped. More...

void	addStat (statistics::Info *info)
	Register a stat with this group. More...

const std::map< std::string, Group * > &	getStatGroups () const
	Get all child groups associated with this object. More...

const std::vector< Info * > &	getStats () const
	Get all stats associated with this object. More...

void	addStatGroup (const char name, Group block)
	Add a stat block as a child of this block. More...

const Info *	resolveStat (std::string name) const
	Resolve a stat by its name within this group. More...

void	mergeStatGroup (Group *block)
	Merge the contents (stats & children) of a block to this block. More...

	Group ()=delete

	Group (const Group &)=delete

Group &	operator= (const Group &)=delete

Public Member Functions inherited from gem5::Named
	Named (const std::string &name_)

virtual	~Named ()=default

virtual std::string	name () const

Public Member Functions inherited from gem5::Clocked
void	updateClockPeriod ()
	Update the tick to the current tick. More...

Tick	clockEdge (Cycles cycles=Cycles(0)) const
	Determine the tick when a cycle begins, by default the current one, but the argument also enables the caller to determine a future cycle. More...

Cycles	curCycle () const
	Determine the current cycle, corresponding to a tick aligned to a clock edge. More...

Tick	nextCycle () const
	Based on the clock of the object, determine the start tick of the first cycle that is at least one cycle in the future. More...

uint64_t	frequency () const

Tick	clockPeriod () const

double	voltage () const

Cycles	ticksToCycles (Tick t) const

Tick	cyclesToTicks (Cycles c) const

Public Attributes
int	hitLatency

int	missLatency1

int	missLatency2

std::vector< CpuSidePort * >	cpuSidePort

std::vector< MemSidePort * >	memSidePort

int	maxCoalescedReqs

int	outstandingReqs

std::unordered_map< Addr, TLBEvent * >	translationReturnEvent

std::queue< Addr >	cleanupQueue

EventFunctionWrapper	cleanupEvent

AccessPatternTable	TLBFootprint

EventFunctionWrapper	exitEvent

Public Attributes inherited from gem5::ClockedObject
PowerState *	powerState

Protected Types
typedef std::list< TlbEntry * >	EntryList

Protected Member Functions
EntryList::iterator	lookupIt (Addr va, bool update_lru=true)

Fault	translateInt (bool read, const RequestPtr &req, ThreadContext *tc)

Fault	translate (const RequestPtr &req, ThreadContext tc, Translation translation, Mode mode, bool &delayedResponse, bool timing, int &latency)

Protected Member Functions inherited from gem5::Drainable
	Drainable ()

virtual	~Drainable ()

virtual void	drainResume ()
	Resume execution after a successful drain. More...

void	signalDrainDone () const
	Signal that an object is drained. More...

Protected Member Functions inherited from gem5::Clocked
	Clocked (ClockDomain &clk_domain)
	Create a clocked object and set the clock domain based on the parameters. More...

	Clocked (Clocked &)=delete

Clocked &	operator= (Clocked &)=delete

virtual	~Clocked ()
	Virtual destructor due to inheritance. More...

void	resetClock () const
	Reset the object's clock using the current global tick value. More...

virtual void	clockPeriodUpdated ()
	A hook subclasses can implement so they can do any extra work that's needed when the clock rate is changed. More...

Protected Attributes
uint32_t	configAddress

Walker *	walker

int	size

int	assoc

int	numSets

bool	FA
	true if this is a fully-associative TLB More...

Addr	setMask

bool	allocationPolicy
	Allocation Policy: true if we always allocate on a hit, false otherwise. More...

bool	hasMemSidePort
	if true, then this is not the last level TLB More...

bool	accessDistance
	Print out accessDistance stats. More...

std::vector< TlbEntry >	tlb

std::vector< EntryList >	freeList

std::vector< EntryList >	entryList
	An entryList per set is the equivalent of an LRU stack; it's used to guide replacement decisions. More...

gem5::X86ISA::GpuTLB::GpuTLBStats	stats

Protected Attributes inherited from gem5::SimObject
const SimObjectParams &	_params
	Cached copy of the object parameters. More...

Protected Attributes inherited from gem5::EventManager
EventQueue *	eventq
	A pointer to this object's event queue. More...

Friends
class	Walker

Additional Inherited Members
Static Public Member Functions inherited from gem5::SimObject
static void	serializeAll (const std::string &cpt_dir)
	Create a checkpoint by serializing all SimObjects in the system. More...

static SimObject *	find (const char *name)
	Find the SimObject with the given name and return a pointer to it. More...

static void	setSimObjectResolver (SimObjectResolver *resolver)
	There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More...

static SimObjectResolver *	getSimObjectResolver ()
	There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More...

Static Public Member Functions inherited from gem5::Serializable
static const std::string &	currentSection ()
	Gets the fully-qualified name of the active section. More...

static void	generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream)
	Generate a checkpoint file so that the serialization can be routed to it. More...

Detailed Description

Definition at line 65 of file tlb.hh.

Member Typedef Documentation

◆ AccessPatternTable

typedef std::unordered_map<Addr, AccessInfo> gem5::X86ISA::GpuTLB::AccessPatternTable

Definition at line 345 of file tlb.hh.

◆ EntryList

typedef std::list<TlbEntry*> gem5::X86ISA::GpuTLB::EntryList

protected

Definition at line 70 of file tlb.hh.

◆ Mode

typedef enum BaseMMU::Mode gem5::X86ISA::GpuTLB::Mode

Definition at line 77 of file tlb.hh.

◆ Params

typedef X86GPUTLBParams gem5::X86ISA::GpuTLB::Params

Definition at line 75 of file tlb.hh.

Member Enumeration Documentation

◆ tlbOutcome

enum gem5::X86ISA::GpuTLB::tlbOutcome

Enumerator
TLB_HIT
TLB_MISS
PAGE_WALK
MISS_RETURN

Definition at line 194 of file tlb.hh.

Constructor & Destructor Documentation

◆ GpuTLB()

gem5::X86ISA::GpuTLB::GpuTLB ( const Params & p )

Warning: : the set-associative version assumes you have a fixed page size of 4KB. If the page size is greather than 4KB (as defined in the X86ISA::PageBytes), then there are various issues w/ the current implementation (you'd have the same 8KB page being replicated in different sets etc)

Definition at line 67 of file tlb.cc.

References cleanup().

◆ ~GpuTLB()

gem5::X86ISA::GpuTLB::~GpuTLB ( )

Definition at line 131 of file tlb.cc.

References translationReturnEvent.

Member Function Documentation

◆ cleanup()

void gem5::X86ISA::GpuTLB::cleanup ( )

the higher level coalescer should retry if it has any pending requests.

Definition at line 1274 of file tlb.cc.

References cleanupQueue, cpuSidePort, gem5::ArmISA::i, outstandingReqs, and translationReturnEvent.

Referenced by GpuTLB().

◆ demapPage()

void gem5::X86ISA::GpuTLB::demapPage	(	Addr	va,
		uint64_t	asn
	)

Definition at line 267 of file tlb.cc.

References entryList, freeList, lookupIt(), gem5::X86ISA::PageShift, gem5::ArmISA::set, setMask, and gem5::ArmISA::va.

◆ doMmuRegRead()

Tick gem5::X86ISA::GpuTLB::doMmuRegRead	(	ThreadContext *	tc,
		Packet *	pkt
	)

◆ doMmuRegWrite()

Tick gem5::X86ISA::GpuTLB::doMmuRegWrite	(	ThreadContext *	tc,
		Packet *	pkt
	)

◆ dumpAll()

void gem5::X86ISA::GpuTLB::dumpAll ( )

◆ exitCallback()

void gem5::X86ISA::GpuTLB::exitCallback ( )

Definition at line 1333 of file tlb.cc.

References accessDistance, gem5::X86ISA::GpuTLB::GpuTLBStats::avgReuseDistance, gem5::OutputDirectory::create(), gem5::ArmISA::i, gem5::Named::name(), gem5::simout, stats, gem5::OutputStream::stream(), and TLBFootprint.

◆ getPort()

Port & gem5::X86ISA::GpuTLB::getPort	(	const std::string &	if_name,
		PortID	idx = `InvalidPortID`
	)

overridevirtual

Get a port with a given name and index.

This is used at binding time and returns a reference to a protocol-agnostic port.

gem5 has a request and response port interface. All memory objects are connected together via ports. These ports provide a rigid interface between these memory objects. These ports implement three different memory system modes: timing, atomic, and functional. The most important mode is the timing mode and here timing mode is used for conducting cycle-level timing experiments. The other modes are only used in special circumstances and should not be used to conduct cycle-level timing experiments. The other modes are only used in special circumstances. These ports allow SimObjects to communicate with each other.

Parameters

if_name	Port name
idx	Index in the case of a VectorPort

Returns: A reference to the given port

Reimplemented from gem5::SimObject.

Definition at line 138 of file tlb.cc.

References cpuSidePort, hasMemSidePort, memSidePort, and panic.

◆ getWalker()

Walker * gem5::X86ISA::GpuTLB::getWalker ( )

Definition at line 639 of file tlb.cc.

References walker.

◆ handleFuncTranslationReturn()

void gem5::X86ISA::GpuTLB::handleFuncTranslationReturn	(	PacketPtr	pkt,
		tlbOutcome	tlb_outcome
	)

handleFuncTranslationReturn is called on a TLB hit, when a TLB miss returns or when a page fault returns.

It updates LRU, inserts the TLB entry on a miss depending on the allocation policy and does the required protection checks. It does NOT create a new packet to update the packet's addr; this is done in hsail-gpu code.

We are returning either from a page walk or from a hit at a lower TLB level. The senderState should be "carrying" a pointer to the correct TLBEntry.

Do paging checks if it's a normal functional access. If it's for a prefetch, then sometimes you can try to prefetch something that won't pass protection. We don't actually want to fault becuase there is no demand access to deem this a violation. Just put it in the TLB and it will fault if indeed a future demand access touches it in violation.

This feature could be used to explore security issues around speculative memory accesses.

Definition at line 1041 of file tlb.cc.

References allocationPolicy, DPRINTF, insert(), gem5::GpuTranslationState::isPrefetch, gem5::X86ISA::mode, gem5::X86ISA::TlbEntry::paddr, gem5::X86ISA::PageBytes, pagingProtectionChecks(), gem5::Packet::req, gem5::roundDown(), gem5::Packet::senderState, gem5::X86ISA::TlbEntry::size(), gem5::GpuTranslationState::tc, TLB_HIT, gem5::GpuTranslationState::tlbEntry, gem5::GpuTranslationState::tlbMode, gem5::X86ISA::TlbEntry::uncacheable, gem5::Request::UNCACHEABLE, gem5::MipsISA::vaddr, and gem5::X86ISA::TlbEntry::vaddr.

◆ handleTranslationReturn()

void gem5::X86ISA::GpuTLB::handleTranslationReturn	(	Addr	virt_page_addr,
		tlbOutcome	tlb_outcome,
		PacketPtr	pkt
	)

handleTranslationReturn is called on a TLB hit, when a TLB miss returns or when a page fault returns.

The latter calls handelHit with TLB miss as tlbOutcome.

We are returning either from a page walk or from a hit at a lower TLB level. The senderState should be "carrying" a pointer to the correct TLBEntry.

At this point the packet carries an up-to-date tlbEntry pointer in its senderState. Next step is to do the paging protection checks.

Definition at line 787 of file tlb.cc.

References allocationPolicy, cleanupEvent, cleanupQueue, cpuSidePort, gem5::curTick(), DPRINTF, insert(), gem5::Packet::isRequest(), gem5::Packet::makeTimingResponse(), gem5::X86ISA::mode, gem5::X86ISA::TlbEntry::paddr, pagingProtectionChecks(), gem5::Packet::req, gem5::EventManager::schedule(), gem5::Event::scheduled(), gem5::Packet::senderState, gem5::X86ISA::TlbEntry::size(), gem5::GpuTranslationState::tc, TLB_HIT, gem5::GpuTranslationState::tlbEntry, gem5::GpuTranslationState::tlbMode, gem5::X86ISA::TlbEntry::uncacheable, gem5::Request::UNCACHEABLE, gem5::MipsISA::vaddr, and gem5::X86ISA::TlbEntry::vaddr.

Referenced by translationReturn().

◆ insert()

TlbEntry * gem5::X86ISA::GpuTLB::insert	(	Addr	vpn,
		TlbEntry &	entry
	)

vpn holds the virtual page address The least significant bits are simply masked

Definition at line 160 of file tlb.cc.

References entryList, freeList, gem5::X86ISA::PageShift, gem5::ArmISA::set, setMask, and gem5::X86ISA::TlbEntry::vaddr.

Referenced by handleFuncTranslationReturn(), handleTranslationReturn(), and translate().

◆ invalidateAll()

void gem5::X86ISA::GpuTLB::invalidateAll ( )

Definition at line 229 of file tlb.cc.

References DPRINTF, entryList, freeList, gem5::ArmISA::i, and numSets.

◆ invalidateNonGlobal()

void gem5::X86ISA::GpuTLB::invalidateNonGlobal ( )

Definition at line 249 of file tlb.cc.

References DPRINTF, entryList, freeList, gem5::ArmISA::i, and numSets.

◆ issueTLBLookup()

void gem5::X86ISA::GpuTLB::issueTLBLookup ( PacketPtr pkt )

Do the TLB lookup for this coalesced request and schedule another event <TLB access latency> cycles later.

Definition at line 661 of file tlb.cc.

References gem5::X86ISA::GpuTLB::GpuTLBStats::accessCycles, gem5::curTick(), gem5::Clocked::cyclesToTicks(), DPRINTF, gem5::ThreadContext::getProcessPtr(), gem5::X86ISA::GpuTLB::GpuTLBStats::globalNumTLBAccesses, gem5::X86ISA::GpuTLB::GpuTLBStats::globalNumTLBHits, gem5::X86ISA::GpuTLB::GpuTLBStats::globalNumTLBMisses, hitLatency, gem5::GpuTranslationState::hitLevel, gem5::GpuTranslationState::isPrefetch, gem5::X86ISA::GpuTLB::GpuTLBStats::localCycles, lookup(), gem5::X86ISA::p, gem5::X86ISA::TlbEntry::paddr, gem5::X86ISA::PageBytes, panic, gem5::Packet::req, gem5::GpuTranslationState::reqCnt, gem5::roundDown(), gem5::EventManager::schedule(), gem5::Packet::senderState, stats, gem5::GpuTranslationState::tc, TLB_HIT, TLB_MISS, gem5::GpuTranslationState::tlbEntry, tlbLookup(), translationReturnEvent, updatePageFootprint(), and gem5::X86ISA::TlbEntry::vaddr.

◆ issueTranslation()

void gem5::X86ISA::GpuTLB::issueTranslation ( )

◆ lookup()

TlbEntry * gem5::X86ISA::GpuTLB::lookup	(	Addr	va,
		bool	update_lru = `true`
	)

Definition at line 216 of file tlb.cc.

References entryList, lookupIt(), gem5::X86ISA::PageShift, gem5::ArmISA::set, setMask, and gem5::ArmISA::va.

Referenced by issueTLBLookup(), tlbLookup(), and translate().

◆ lookupIt()

GpuTLB::EntryList::iterator gem5::X86ISA::GpuTLB::lookupIt	(	Addr	va,
		bool	update_lru = `true`
	)

protected

Definition at line 186 of file tlb.cc.

References DPRINTF, entryList, FA, gem5::X86ISA::PageShift, gem5::ArmISA::set, setMask, and gem5::ArmISA::va.

Referenced by demapPage(), and lookup().

◆ pagingProtectionChecks()

void gem5::X86ISA::GpuTLB::pagingProtectionChecks	(	ThreadContext *	tc,
		PacketPtr	pkt,
		TlbEntry *	tlb_entry,
		Mode	mode
	)

Do Paging protection checks.

If we encounter a page fault, then an assertion is fired.

Definition at line 753 of file tlb.cc.

References gem5::X86ISA::CPL0FlagBit, gem5::X86ISA::misc_reg::Cr0, flags, gem5::X86ISA::misc_reg::M5Reg, gem5::X86ISA::mode, panic, gem5::Request::READ_MODIFY_WRITE, gem5::ThreadContext::readMiscRegNoEffect(), gem5::Packet::req, gem5::X86ISA::TlbEntry::user, gem5::X86ISA::TlbEntry::writable, and gem5::BaseMMU::Write.

Referenced by handleFuncTranslationReturn(), and handleTranslationReturn().

◆ printAccessPattern()

void gem5::X86ISA::GpuTLB::printAccessPattern ( )

◆ serialize()

void gem5::X86ISA::GpuTLB::serialize ( CheckpointOut & cp ) const

overridevirtual

Serialize an object.

Output an object's state into the current checkpoint section.

Parameters

cp	Checkpoint state

Implements gem5::Serializable.

Definition at line 646 of file tlb.cc.

◆ setConfigAddress()

void gem5::X86ISA::GpuTLB::setConfigAddress ( uint32_t addr )

Definition at line 243 of file tlb.cc.

References gem5::X86ISA::addr, and configAddress.

◆ tlbLookup()

bool gem5::X86ISA::GpuTLB::tlbLookup	(	const RequestPtr &	req,
		ThreadContext *	tc,
		bool	update_stats
	)

TLB_lookup will only perform a TLB lookup returning true on a TLB hit and false on a TLB miss.

Many of the checks about different modes have been converted to assertions, since these parts of the code are not really used. On a hit it will update the LRU stack.

Definition at line 371 of file tlb.cc.

References DPRINTF, flags, gem5::X86ISA::GpuTLB::GpuTLBStats::localNumTLBAccesses, gem5::X86ISA::GpuTLB::GpuTLBStats::localNumTLBHits, gem5::X86ISA::GpuTLB::GpuTLBStats::localNumTLBMisses, lookup(), gem5::X86ISA::misc_reg::M5Reg, gem5::X86ISA::segment_idx::Ms, gem5::ThreadContext::readMiscRegNoEffect(), gem5::X86ISA::seg, gem5::X86ISA::SegmentFlagMask, stats, and gem5::MipsISA::vaddr.

Referenced by issueTLBLookup().

◆ translate()

Fault gem5::X86ISA::GpuTLB::translate	(	const RequestPtr &	req,
		ThreadContext *	tc,
		Translation *	translation,
		Mode	mode,
		bool &	delayedResponse,
		bool	timing,
		int &	latency
	)

protected

Definition at line 420 of file tlb.cc.

References gem5::X86ISA::AddrSizeFlagMask, gem5::X86ISA::AddrSizeFlagShift, gem5::X86ISA::misc_reg::ApicBase, gem5::ArmISA::attr, gem5::X86ISA::base, gem5::VegaISA::baseAddr, gem5::ThreadContext::contextId(), gem5::X86ISA::CPL0FlagBit, gem5::X86ISA::misc_reg::Cr0, DPRINTF, gem5::X86ISA::segment_idx::Es, gem5::BaseMMU::Execute, gem5::X86ISA::expandDown, fatal, flags, gem5::FullSystem, gem5::ThreadContext::getProcessPtr(), hitLatency, gem5::X86ISA::segment_idx::Hs, gem5::X86ISA::segment_idx::Idtr, insert(), gem5::PCStateBase::instAddr(), gem5::X86ISA::limit, gem5::X86ISA::GpuTLB::GpuTLBStats::localNumTLBAccesses, gem5::X86ISA::GpuTLB::GpuTLBStats::localNumTLBHits, gem5::X86ISA::GpuTLB::GpuTLBStats::localNumTLBMisses, lookup(), gem5::X86ISA::segment_idx::Ls, gem5::X86ISA::misc_reg::M5Reg, gem5::X86ISA::mask, missLatency1, missLatency2, gem5::X86ISA::mode, gem5::X86ISA::segment_idx::Ms, gem5::NoFault, gem5::X86ISA::offset, gem5::X86ISA::p, gem5::X86ISA::TlbEntry::paddr, gem5::EmulationPageTable::Entry::paddr, gem5::X86ISA::PageBytes, gem5::ThreadContext::pcState(), gem5::BaseMMU::Read, gem5::Request::READ_MODIFY_WRITE, gem5::ThreadContext::readMiscRegNoEffect(), gem5::X86ISA::seg, gem5::X86ISA::misc_reg::segAttr(), gem5::X86ISA::misc_reg::segBase(), gem5::X86ISA::misc_reg::segLimit(), gem5::X86ISA::SegmentFlagMask, gem5::X86ISA::misc_reg::segSel(), size, gem5::X86ISA::TlbEntry::size(), stats, translateInt(), gem5::X86ISA::segment_idx::Tsg, gem5::X86ISA::TlbEntry::uncacheable, gem5::Request::UNCACHEABLE, gem5::X86ISA::TlbEntry::user, gem5::MipsISA::vaddr, warn_once, gem5::X86ISA::TlbEntry::writable, gem5::BaseMMU::Write, and gem5::X86ISA::x86LocalAPICAddress().

Referenced by translateAtomic(), and translateTiming().

◆ translateAtomic()

Fault gem5::X86ISA::GpuTLB::translateAtomic	(	const RequestPtr &	req,
		ThreadContext *	tc,
		Mode	mode,
		int &	latency
	)

Definition at line 615 of file tlb.cc.

References gem5::X86ISA::mode, and translate().

◆ translateInt()

Fault gem5::X86ISA::GpuTLB::translateInt	(	bool	read,
		const RequestPtr &	req,
		ThreadContext *	tc
	)

protected

◆ translateTiming()

void gem5::X86ISA::GpuTLB::translateTiming	(	const RequestPtr &	req,
		ThreadContext *	tc,
		Translation *	translation,
		Mode	mode,
		int &	latency
	)

Definition at line 625 of file tlb.cc.

References gem5::X86ISA::GpuTLB::Translation::finish(), gem5::X86ISA::mode, and translate().

◆ translationReturn()

void gem5::X86ISA::GpuTLB::translationReturn	(	Addr	virtPageAddr,
		tlbOutcome	outcome,
		PacketPtr	pkt
	)

A TLBEvent is scheduled after the TLB lookup and helps us take the appropriate actions: (e.g., update TLB on a hit, send request to lower level TLB on a miss, or start a page walk if this was the last-level TLB).

Here we take the appropriate actions based on the result of the TLB lookup.

There is a TLB below. Send the coalesced request. We actually send the very first packet of all the pending packets for this virtual page address.

we add an extra cycle in the return path of the translation requests in between the various TLB levels.

Definition at line 874 of file tlb.cc.

References gem5::X86ISA::GpuTLB::GpuTLBStats::accessCycles, gem5::curTick(), gem5::Clocked::cyclesToTicks(), DPRINTF, gem5::BaseMMU::Execute, gem5::ThreadContext::getProcessPtr(), handleTranslationReturn(), hasMemSidePort, gem5::GpuTranslationState::isPrefetch, gem5::X86ISA::GpuTLB::GpuTLBStats::localCycles, memSidePort, MISS_RETURN, missLatency2, gem5::X86ISA::p, gem5::EmulationPageTable::Entry::paddr, PAGE_WALK, gem5::X86ISA::GpuTLB::GpuTLBStats::pageTableCycles, panic, gem5::Packet::req, gem5::GpuTranslationState::reqCnt, gem5::EventManager::schedule(), gem5::Packet::senderState, stats, gem5::GpuTranslationState::tc, TLB_HIT, TLB_MISS, gem5::GpuTranslationState::tlbEntry, gem5::GpuTranslationState::tlbMode, translationReturnEvent, gem5::X86ISA::GpuTLB::TLBEvent::updateOutcome(), and gem5::MipsISA::vaddr.

◆ unserialize()

void gem5::X86ISA::GpuTLB::unserialize ( CheckpointIn & cp )

overridevirtual

Unserialize an object.

Read an object's state from the current checkpoint section.

Parameters

cp	Checkpoint state

Implements gem5::Serializable.

Definition at line 651 of file tlb.cc.

◆ updatePageFootprint()

void gem5::X86ISA::GpuTLB::updatePageFootprint ( Addr virt_page_addr )

Definition at line 1298 of file tlb.cc.

References accessDistance, gem5::X86ISA::GpuTLB::AccessInfo::accessesPerPage, gem5::curTick(), gem5::X86ISA::GpuTLB::AccessInfo::lastTimeAccessed, gem5::X86ISA::GpuTLB::GpuTLBStats::localNumTLBAccesses, gem5::X86ISA::GpuTLB::AccessInfo::meanDistance, gem5::X86ISA::GpuTLB::GpuTLBStats::numUniquePages, stats, gem5::X86ISA::GpuTLB::AccessInfo::sumDistance, TLBFootprint, gem5::X86ISA::GpuTLB::AccessInfo::totalReuseDistance, and gem5::statistics::ScalarBase< Derived, Stor >::value().

Referenced by issueTLBLookup().

◆ updatePhysAddresses()

void gem5::X86ISA::GpuTLB::updatePhysAddresses	(	Addr	virt_page_addr,
		TlbEntry *	tlb_entry,
		Addr	phys_page_addr
	)

Friends And Related Function Documentation

◆ Walker

friend class Walker

friend

Definition at line 68 of file tlb.hh.

Member Data Documentation

◆ accessDistance

bool gem5::X86ISA::GpuTLB::accessDistance

protected

Print out accessDistance stats.

One stat file per TLB.

Definition at line 141 of file tlb.hh.

Referenced by exitCallback(), and updatePageFootprint().

◆ allocationPolicy

bool gem5::X86ISA::GpuTLB::allocationPolicy

protected

Allocation Policy: true if we always allocate on a hit, false otherwise.

Default is true.

Definition at line 130 of file tlb.hh.

Referenced by handleFuncTranslationReturn(), and handleTranslationReturn().

◆ assoc

int gem5::X86ISA::GpuTLB::assoc

protected

Definition at line 117 of file tlb.hh.

◆ cleanupEvent

EventFunctionWrapper gem5::X86ISA::GpuTLB::cleanupEvent

Definition at line 318 of file tlb.hh.

Referenced by handleTranslationReturn().

◆ cleanupQueue

std::queue<Addr> gem5::X86ISA::GpuTLB::cleanupQueue

Definition at line 312 of file tlb.hh.

Referenced by cleanup(), and handleTranslationReturn().

◆ configAddress

uint32_t gem5::X86ISA::GpuTLB::configAddress

protected

Definition at line 72 of file tlb.hh.

Referenced by setConfigAddress(), and translateInt().

◆ cpuSidePort

std::vector<CpuSidePort*> gem5::X86ISA::GpuTLB::cpuSidePort

Definition at line 260 of file tlb.hh.

Referenced by cleanup(), getPort(), and handleTranslationReturn().

◆ entryList

std::vector<EntryList> gem5::X86ISA::GpuTLB::entryList

protected

An entryList per set is the equivalent of an LRU stack; it's used to guide replacement decisions.

The head of the list contains the MRU TLB entry of the given set. If the freeList for this set is empty, the last element of the list is evicted (i.e., dropped on the floor).

Definition at line 159 of file tlb.hh.

Referenced by demapPage(), insert(), invalidateAll(), invalidateNonGlobal(), lookup(), and lookupIt().

◆ exitEvent

EventFunctionWrapper gem5::X86ISA::GpuTLB::exitEvent

Definition at line 351 of file tlb.hh.

◆ FA

bool gem5::X86ISA::GpuTLB::FA

protected

true if this is a fully-associative TLB

Definition at line 123 of file tlb.hh.

Referenced by lookupIt().

◆ freeList

std::vector<EntryList> gem5::X86ISA::GpuTLB::freeList

protected

Definition at line 150 of file tlb.hh.

Referenced by demapPage(), insert(), invalidateAll(), and invalidateNonGlobal().

◆ hasMemSidePort

bool gem5::X86ISA::GpuTLB::hasMemSidePort

protected

if true, then this is not the last level TLB

Definition at line 135 of file tlb.hh.

Referenced by getPort(), and translationReturn().

◆ hitLatency

int gem5::X86ISA::GpuTLB::hitLatency

Definition at line 170 of file tlb.hh.

Referenced by issueTLBLookup(), and translate().

◆ maxCoalescedReqs

int gem5::X86ISA::GpuTLB::maxCoalescedReqs

Definition at line 269 of file tlb.hh.

◆ memSidePort

std::vector<MemSidePort*> gem5::X86ISA::GpuTLB::memSidePort

Definition at line 262 of file tlb.hh.

Referenced by getPort(), and translationReturn().

◆ missLatency1

int gem5::X86ISA::GpuTLB::missLatency1

Definition at line 171 of file tlb.hh.

Referenced by translate().

◆ missLatency2

int gem5::X86ISA::GpuTLB::missLatency2

Definition at line 172 of file tlb.hh.

Referenced by translate(), and translationReturn().

◆ numSets

int gem5::X86ISA::GpuTLB::numSets

protected

Definition at line 118 of file tlb.hh.

Referenced by invalidateAll(), and invalidateNonGlobal().

◆ outstandingReqs

int gem5::X86ISA::GpuTLB::outstandingReqs

Definition at line 273 of file tlb.hh.

Referenced by cleanup().

◆ setMask

Addr gem5::X86ISA::GpuTLB::setMask

protected

Definition at line 124 of file tlb.hh.

Referenced by demapPage(), insert(), lookup(), and lookupIt().

◆ size

int gem5::X86ISA::GpuTLB::size

protected

Definition at line 116 of file tlb.hh.

Referenced by translate().

◆ stats

gem5::X86ISA::GpuTLB::GpuTLBStats gem5::X86ISA::GpuTLB::stats

protected

Referenced by exitCallback(), issueTLBLookup(), tlbLookup(), translate(), translationReturn(), and updatePageFootprint().

◆ tlb

std::vector<TlbEntry> gem5::X86ISA::GpuTLB::tlb

protected

Definition at line 143 of file tlb.hh.

Referenced by gem5::X86ISA::GpuTLB::TLBEvent::process(), gem5::X86ISA::GpuTLB::CpuSidePort::recvFunctional(), gem5::X86ISA::GpuTLB::CpuSidePort::recvTimingReq(), and gem5::X86ISA::GpuTLB::MemSidePort::recvTimingResp().

◆ TLBFootprint

AccessPatternTable gem5::X86ISA::GpuTLB::TLBFootprint

Definition at line 346 of file tlb.hh.

Referenced by exitCallback(), and updatePageFootprint().

◆ translationReturnEvent

std::unordered_map<Addr, TLBEvent*> gem5::X86ISA::GpuTLB::translationReturnEvent

Definition at line 308 of file tlb.hh.

Referenced by cleanup(), issueTLBLookup(), translationReturn(), and ~GpuTLB().

◆ walker

Walker* gem5::X86ISA::GpuTLB::walker

protected

Definition at line 107 of file tlb.hh.

Referenced by getWalker().

The documentation for this class was generated from the following files:

arch/amdgpu/common/tlb.hh
arch/amdgpu/common/tlb.cc

Classes

Public Types

Public Member Functions

Public Attributes

Protected Types

Protected Member Functions

Protected Attributes

Friends

Additional Inherited Members

Detailed Description

Member Typedef Documentation

◆ AccessPatternTable

◆ EntryList

◆ Mode

◆ Params

Member Enumeration Documentation

◆ tlbOutcome

Constructor & Destructor Documentation

◆ GpuTLB()

◆ ~GpuTLB()

Member Function Documentation

◆ cleanup()

◆ demapPage()

◆ doMmuRegRead()

◆ doMmuRegWrite()

◆ dumpAll()

◆ exitCallback()

◆ getPort()

◆ getWalker()

◆ handleFuncTranslationReturn()

◆ handleTranslationReturn()

◆ insert()

◆ invalidateAll()

◆ invalidateNonGlobal()

◆ issueTLBLookup()

◆ issueTranslation()

◆ lookup()

◆ lookupIt()

◆ pagingProtectionChecks()

◆ printAccessPattern()

◆ serialize()

◆ setConfigAddress()

◆ tlbLookup()

◆ translate()

◆ translateAtomic()

◆ translateInt()

◆ translateTiming()

◆ translationReturn()

◆ unserialize()

◆ updatePageFootprint()

◆ updatePhysAddresses()

Friends And Related Function Documentation

◆ Walker

Member Data Documentation

◆ accessDistance

◆ allocationPolicy

◆ assoc

◆ cleanupEvent

◆ cleanupQueue

◆ configAddress

◆ cpuSidePort

◆ entryList

◆ exitEvent

◆ FA

◆ freeList

◆ hasMemSidePort

◆ hitLatency

◆ maxCoalescedReqs

◆ memSidePort

◆ missLatency1

◆ missLatency2

◆ numSets

◆ outstandingReqs

◆ setMask

◆ size

◆ stats

◆ tlb

◆ TLBFootprint

◆ translationReturnEvent

◆ walker