gem5  v21.1.0.2
gem5::memory::DRAMSim2 Member List

This is the complete list of members for gem5::memory::DRAMSim2, including all inherited members.

_drainManagergem5::Drainableprivate
_drainStategem5::Drainablemutableprivate
_namegem5::Namedprivate
_objNameResolvergem5::SimObjectprivatestatic
_paramsgem5::SimObjectprotected
_systemgem5::memory::AbstractMemoryprotected
AbstractMemory(const AbstractMemory &)gem5::memory::AbstractMemoryprivate
AbstractMemory(const Params &p)gem5::memory::AbstractMemory
access(PacketPtr pkt)gem5::memory::AbstractMemory
accessAndRespond(PacketPtr pkt)gem5::memory::DRAMSim2private
addLockedAddr(LockedAddr addr)gem5::memory::AbstractMemoryinline
addStat(statistics::Info *info)gem5::statistics::Group
addStatGroup(const char *name, Group *block)gem5::statistics::Group
backdoorgem5::memory::AbstractMemoryprotected
checkLockedAddrList(PacketPtr pkt)gem5::memory::AbstractMemoryprotected
clockDomaingem5::Clockedprivate
Clocked(ClockDomain &clk_domain)gem5::Clockedinlineprotected
Clocked(Clocked &)=deletegem5::Clockedprotected
clockEdge(Cycles cycles=Cycles(0)) constgem5::Clockedinline
ClockedObject(const ClockedObjectParams &p)gem5::ClockedObject
clockPeriod() constgem5::Clockedinline
clockPeriodUpdated()gem5::Clockedinlineprotectedvirtual
confTableReportedgem5::memory::AbstractMemoryprotected
curCycle() constgem5::Clockedinline
currentSection()gem5::Serializablestatic
cyclegem5::Clockedmutableprivate
cyclesToTicks(Cycles c) constgem5::Clockedinline
deschedule(Event &event)gem5::EventManagerinline
deschedule(Event *event)gem5::EventManagerinline
dmDrain()gem5::Drainableprivate
dmDrainResume()gem5::Drainableprivate
drain() overridegem5::memory::DRAMSim2virtual
Drainable()gem5::Drainableprotected
drainResume()gem5::Drainableinlineprotectedvirtual
drainState() constgem5::Drainableinline
DRAMSim2(const Params &p)gem5::memory::DRAMSim2
EventManager(EventManager &em)gem5::EventManagerinline
EventManager(EventManager *em)gem5::EventManagerinline
EventManager(EventQueue *eq)gem5::EventManagerinline
eventqgem5::EventManagerprotected
eventQueue() constgem5::EventManagerinline
find(const char *name)gem5::SimObjectstatic
frequency() constgem5::Clockedinline
functionalAccess(PacketPtr pkt)gem5::memory::AbstractMemory
generateCheckpointOut(const std::string &cpt_dir, std::ofstream &outstream)gem5::Serializablestatic
getAddrRange() constgem5::memory::AbstractMemory
getBackdoor(MemBackdoorPtr &bd_ptr)gem5::memory::AbstractMemoryinline
getLockedAddrList() constgem5::memory::AbstractMemoryinline
getPort(const std::string &if_name, PortID idx=InvalidPortID) overridegem5::memory::DRAMSim2virtual
getProbeManager()gem5::SimObject
getSimObjectResolver()gem5::SimObjectstatic
getStatGroups() constgem5::statistics::Group
getStats() constgem5::statistics::Group
Group()=deletegem5::statistics::Group
Group(const Group &)=deletegem5::statistics::Group
Group(Group *parent, const char *name=nullptr)gem5::statistics::Group
inAddrMapgem5::memory::AbstractMemoryprotected
init() overridegem5::memory::DRAMSim2virtual
initState() overridegem5::memory::AbstractMemoryvirtual
isConfReported() constgem5::memory::AbstractMemoryinline
isInAddrMap() constgem5::memory::AbstractMemoryinline
isKvmMap() constgem5::memory::AbstractMemoryinline
isNull() constgem5::memory::AbstractMemoryinline
kvmMapgem5::memory::AbstractMemoryprotected
loadState(CheckpointIn &cp)gem5::SimObjectvirtual
lockedAddrListgem5::memory::AbstractMemoryprotected
memInvalidate()gem5::SimObjectinlinevirtual
memWriteback()gem5::SimObjectinlinevirtual
mergedParentgem5::statistics::Groupprivate
mergedStatGroupsgem5::statistics::Groupprivate
mergeStatGroup(Group *block)gem5::statistics::Group
name() constgem5::Namedinlinevirtual
Named(const std::string &name_)gem5::Namedinline
nbrOutstanding() constgem5::memory::DRAMSim2private
nbrOutstandingReadsgem5::memory::DRAMSim2private
nbrOutstandingWritesgem5::memory::DRAMSim2private
nextCycle() constgem5::Clockedinline
notifyFork()gem5::Drainableinlinevirtual
operator=(const AbstractMemory &)gem5::memory::AbstractMemoryprivate
gem5::ClockedObject::operator=(const Group &)=deletegem5::statistics::Group
gem5::ClockedObject::operator=(Clocked &)=deletegem5::Clockedprotected
outstandingReadsgem5::memory::DRAMSim2private
outstandingWritesgem5::memory::DRAMSim2private
params() constgem5::SimObjectinline
PARAMS(AbstractMemory)gem5::memory::AbstractMemory
Params typedefgem5::memory::DRAMSim2
pathgem5::Serializableprivatestatic
pendingDeletegem5::memory::DRAMSim2private
pmemAddrgem5::memory::AbstractMemoryprotected
portgem5::memory::DRAMSim2private
powerStategem5::ClockedObject
preDumpStats()gem5::statistics::Groupvirtual
probeManagergem5::SimObjectprivate
rangegem5::memory::AbstractMemoryprotected
readComplete(unsigned id, uint64_t addr, uint64_t cycle)gem5::memory::DRAMSim2
recvAtomic(PacketPtr pkt)gem5::memory::DRAMSim2protected
recvFunctional(PacketPtr pkt)gem5::memory::DRAMSim2protected
recvRespRetry()gem5::memory::DRAMSim2protected
recvTimingReq(PacketPtr pkt)gem5::memory::DRAMSim2protected
regProbeListeners()gem5::SimObjectvirtual
regProbePoints()gem5::SimObjectvirtual
regStats()gem5::statistics::Groupvirtual
reschedule(Event &event, Tick when, bool always=false)gem5::EventManagerinline
reschedule(Event *event, Tick when, bool always=false)gem5::EventManagerinline
resetClock() constgem5::Clockedinlineprotected
resetStats()gem5::statistics::Groupvirtual
resolveStat(std::string name) constgem5::statistics::Group
responseQueuegem5::memory::DRAMSim2private
retryReqgem5::memory::DRAMSim2private
retryRespgem5::memory::DRAMSim2private
schedule(Event &event, Tick when)gem5::EventManagerinline
schedule(Event *event, Tick when)gem5::EventManagerinline
sendResponse()gem5::memory::DRAMSim2private
sendResponseEventgem5::memory::DRAMSim2private
Serializable()gem5::Serializable
serialize(CheckpointOut &cp) const overridegem5::ClockedObjectvirtual
serializeAll(const std::string &cpt_dir)gem5::SimObjectstatic
serializeSection(CheckpointOut &cp, const char *name) constgem5::Serializable
serializeSection(CheckpointOut &cp, const std::string &name) constgem5::Serializableinline
setBackingStore(uint8_t *pmem_addr)gem5::memory::AbstractMemory
setCurTick(Tick newVal)gem5::EventManagerinline
setSimObjectResolver(SimObjectResolver *resolver)gem5::SimObjectstatic
signalDrainDone() constgem5::Drainableinlineprotected
SimObject(const Params &p)gem5::SimObject
SimObjectList typedefgem5::SimObjectprivate
simObjectListgem5::SimObjectprivatestatic
size() constgem5::memory::AbstractMemoryinline
start() constgem5::memory::AbstractMemoryinline
startTickgem5::memory::DRAMSim2private
startup() overridegem5::memory::DRAMSim2virtual
statGroupsgem5::statistics::Groupprivate
statsgem5::memory::AbstractMemoryprotected
system() constgem5::memory::AbstractMemoryinline
system(System *sys)gem5::memory::AbstractMemoryinline
tick()gem5::memory::DRAMSim2private
tickEventgem5::memory::DRAMSim2private
ticksToCycles(Tick t) constgem5::Clockedinline
toHostAddr(Addr addr) constgem5::memory::AbstractMemoryinline
trackLoadLocked(PacketPtr pkt)gem5::memory::AbstractMemoryprotected
unserialize(CheckpointIn &cp) overridegem5::ClockedObjectvirtual
unserializeSection(CheckpointIn &cp, const char *name)gem5::Serializable
unserializeSection(CheckpointIn &cp, const std::string &name)gem5::Serializableinline
update() constgem5::Clockedinlineprivate
updateClockPeriod()gem5::Clockedinline
voltage() constgem5::Clockedinline
wakeupEventQueue(Tick when=(Tick) -1)gem5::EventManagerinline
wrappergem5::memory::DRAMSim2private
writeComplete(unsigned id, uint64_t addr, uint64_t cycle)gem5::memory::DRAMSim2
writeOK(PacketPtr pkt)gem5::memory::AbstractMemoryinlineprotected
~AbstractMemory()gem5::memory::AbstractMemoryinlinevirtual
~Clocked()gem5::Clockedinlineprotectedvirtual
~Drainable()gem5::Drainableprotectedvirtual
~Group()gem5::statistics::Groupvirtual
~Named()=defaultgem5::Namedvirtual
~Serializable()gem5::Serializablevirtual
~SimObject()gem5::SimObjectvirtual

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