#include <dramsim2.hh>

Inheritance diagram for gem5::memory::DRAMSim2:

Classes
class	MemoryPort
	The memory port has to deal with its own flow control to avoid having unbounded storage that is implicitly created in the port itself. More...

Public Types
typedef DRAMSim2Params	Params

Public Types inherited from gem5::ClockedObject
using	Params = ClockedObjectParams
	Parameters of ClockedObject.

Public Types inherited from gem5::SimObject
typedef SimObjectParams	Params

Public Member Functions
	DRAMSim2 (const Params &p)

void	readComplete (unsigned id, uint64_t addr, uint64_t cycle)
	Read completion callback.

void	writeComplete (unsigned id, uint64_t addr, uint64_t cycle)
	Write completion callback.

DrainState	drain () override
	Draining is the process of clearing out the states of SimObjects.These are the SimObjects that are partially executed or are partially in flight.

Port &	getPort (const std::string &if_name, PortID idx=InvalidPortID) override
	Get a port with a given name and index.

void	init () override
	init() is called after all C++ SimObjects have been created and all ports are connected.

void	startup () override
	startup() is the final initialization call before simulation.

Public Member Functions inherited from gem5::memory::AbstractMemory
	PARAMS (AbstractMemory)

	AbstractMemory (const Params &p)

virtual	~AbstractMemory ()

void	initState () override
	initState() is called on each SimObject when not restoring from a checkpoint.

bool	isNull () const
	See if this is a null memory that should never store data and always return zero.

void	setBackingStore (uint8_t *pmem_addr)
	Set the host memory backing store to be used by this memory controller.

void	getBackdoor (MemBackdoorPtr &bd_ptr)

const std::list< LockedAddr > &	getLockedAddrList () const
	Get the list of locked addresses to allow checkpointing.

void	addLockedAddr (LockedAddr addr)
	Add a locked address to allow for checkpointing.

System *	system () const
	read the system pointer Implemented for completeness with the setter

void	system (System *sys)
	Set the system pointer on this memory This can't be done via a python parameter because the system needs pointers to all the memories and the reverse would create a cycle in the object graph.

AddrRange	getAddrRange () const
	Get the address range.

uint8_t *	toHostAddr (Addr addr) const
	Transform a gem5 address space address into its physical counterpart in the host address space.

uint64_t	size () const
	Get the memory size.

Addr	start () const
	Get the start address.

bool	isConfReported () const
	Should this memory be passed to the kernel and part of the OS physical memory layout.

bool	isInAddrMap () const
	Some memories are used as shadow memories or should for other reasons not be part of the global address map.

bool	isKvmMap () const
	When shadow memories are in use, KVM may want to make one or the other, but cannot map both into the guest address space.

void	access (PacketPtr pkt)
	Perform an untimed memory access and update all the state (e.g.

void	functionalAccess (PacketPtr pkt)
	Perform an untimed memory read or write without changing anything but the memory itself.

Public Member Functions inherited from gem5::ClockedObject
	ClockedObject (const ClockedObjectParams &p)

void	serialize (CheckpointOut &cp) const override
	Serialize an object.

void	unserialize (CheckpointIn &cp) override
	Unserialize an object.

Public Member Functions inherited from gem5::SimObject
const Params &	params () const

	SimObject (const Params &p)

virtual	~SimObject ()

virtual void	loadState (CheckpointIn &cp)
	loadState() is called on each SimObject when restoring from a checkpoint.

virtual void	regProbePoints ()
	Register probe points for this object.

virtual void	regProbeListeners ()
	Register probe listeners for this object.

ProbeManager *	getProbeManager ()
	Get the probe manager for this object.

DrainState	drain () override
	Provide a default implementation of the drain interface for objects that don't need draining.

virtual void	memWriteback ()
	Write back dirty buffers to memory using functional writes.

virtual void	memInvalidate ()
	Invalidate the contents of memory buffers.

void	serialize (CheckpointOut &cp) const override
	Serialize an object.

void	unserialize (CheckpointIn &cp) override
	Unserialize an object.

Public Member Functions inherited from gem5::EventManager
EventQueue *	eventQueue () const

void	schedule (Event &event, Tick when)

void	deschedule (Event &event)

void	reschedule (Event &event, Tick when, bool always=false)

void	schedule (Event *event, Tick when)

void	deschedule (Event *event)

void	reschedule (Event *event, Tick when, bool always=false)

void	wakeupEventQueue (Tick when=(Tick) -1)
	This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers.

void	setCurTick (Tick newVal)

	EventManager (EventManager &em)
	Event manger manages events in the event queue.

	EventManager (EventManager *em)

	EventManager (EventQueue *eq)

Public Member Functions inherited from gem5::Serializable
	Serializable ()

virtual	~Serializable ()

void	serializeSection (CheckpointOut &cp, const char *name) const
	Serialize an object into a new section.

void	serializeSection (CheckpointOut &cp, const std::string &name) const

void	unserializeSection (CheckpointIn &cp, const char *name)
	Unserialize an a child object.

void	unserializeSection (CheckpointIn &cp, const std::string &name)

Public Member Functions inherited from gem5::Drainable
DrainState	drainState () const
	Return the current drain state of an object.

virtual void	notifyFork ()
	Notify a child process of a fork.

Public Member Functions inherited from gem5::statistics::Group
	Group (Group parent, const char name=nullptr)
	Construct a new statistics group.

virtual	~Group ()

virtual void	regStats ()
	Callback to set stat parameters.

virtual void	resetStats ()
	Callback to reset stats.

virtual void	preDumpStats ()
	Callback before stats are dumped.

void	addStat (statistics::Info *info)
	Register a stat with this group.

const std::map< std::string, Group * > &	getStatGroups () const
	Get all child groups associated with this object.

const std::vector< Info * > &	getStats () const
	Get all stats associated with this object.

void	addStatGroup (const char name, Group block)
	Add a stat block as a child of this block.

const Info *	resolveStat (std::string name) const
	Resolve a stat by its name within this group.

void	mergeStatGroup (Group *block)
	Merge the contents (stats & children) of a block to this block.

	Group ()=delete

	Group (const Group &)=delete

Group &	operator= (const Group &)=delete

Public Member Functions inherited from gem5::Named
	Named (const std::string &name_)

virtual	~Named ()=default

virtual std::string	name () const

Public Member Functions inherited from gem5::Clocked
void	updateClockPeriod ()
	Update the tick to the current tick.

Tick	clockEdge (Cycles cycles=Cycles(0)) const
	Determine the tick when a cycle begins, by default the current one, but the argument also enables the caller to determine a future cycle.

Cycles	curCycle () const
	Determine the current cycle, corresponding to a tick aligned to a clock edge.

Tick	nextCycle () const
	Based on the clock of the object, determine the start tick of the first cycle that is at least one cycle in the future.

uint64_t	frequency () const

Tick	clockPeriod () const

double	voltage () const

Cycles	ticksToCycles (Tick t) const

Tick	cyclesToTicks (Cycles c) const

Protected Member Functions
Tick	recvAtomic (PacketPtr pkt)

void	recvFunctional (PacketPtr pkt)

bool	recvTimingReq (PacketPtr pkt)

void	recvRespRetry ()

Protected Member Functions inherited from gem5::memory::AbstractMemory
bool	checkLockedAddrList (PacketPtr pkt)

void	trackLoadLocked (PacketPtr pkt)

bool	writeOK (PacketPtr pkt)

Protected Member Functions inherited from gem5::Drainable
	Drainable ()

virtual	~Drainable ()

virtual void	drainResume ()
	Resume execution after a successful drain.

void	signalDrainDone () const
	Signal that an object is drained.

Protected Member Functions inherited from gem5::Clocked
	Clocked (ClockDomain &clk_domain)
	Create a clocked object and set the clock domain based on the parameters.

	Clocked (Clocked &)=delete

Clocked &	operator= (Clocked &)=delete

virtual	~Clocked ()
	Virtual destructor due to inheritance.

void	resetClock () const
	Reset the object's clock using the current global tick value.

virtual void	clockPeriodUpdated ()
	A hook subclasses can implement so they can do any extra work that's needed when the clock rate is changed.

Private Member Functions
unsigned int	nbrOutstanding () const

void	accessAndRespond (PacketPtr pkt)
	When a packet is ready, use the "access()" method in AbstractMemory to actually create the response packet, and send it back to the outside world requestor.

void	sendResponse ()

void	tick ()
	Progress the controller one clock cycle.

Private Attributes
MemoryPort	port

DRAMSim2Wrapper	wrapper
	The actual DRAMSim2 wrapper.

bool	retryReq
	Is the connected port waiting for a retry from us.

bool	retryResp
	Are we waiting for a retry for sending a response.

Tick	startTick
	Keep track of when the wrapper is started.

std::unordered_map< Addr, std::queue< PacketPtr > >	outstandingReads
	Keep track of what packets are outstanding per address, and do so separately for reads and writes.

std::unordered_map< Addr, std::queue< PacketPtr > >	outstandingWrites

unsigned int	nbrOutstandingReads
	Count the number of outstanding transactions so that we can block any further requests until there is space in DRAMSim2 and the sending queue we need to buffer the response packets.

unsigned int	nbrOutstandingWrites

std::deque< PacketPtr >	responseQueue
	Queue to hold response packets until we can send them back.

EventFunctionWrapper	sendResponseEvent
	Event to schedule sending of responses.

EventFunctionWrapper	tickEvent
	Event to schedule clock ticks.

std::unique_ptr< Packet >	pendingDelete
	Upstream caches need this packet until true is returned, so hold it for deletion until a subsequent call.

Additional Inherited Members
Static Public Member Functions inherited from gem5::SimObject
static void	serializeAll (const std::string &cpt_dir)
	Create a checkpoint by serializing all SimObjects in the system.

static SimObject *	find (const char *name)
	Find the SimObject with the given name and return a pointer to it.

static void	setSimObjectResolver (SimObjectResolver *resolver)
	There is a single object name resolver, and it is only set when simulation is restoring from checkpoints.

static SimObjectResolver *	getSimObjectResolver ()
	There is a single object name resolver, and it is only set when simulation is restoring from checkpoints.

Static Public Member Functions inherited from gem5::Serializable
static const std::string &	currentSection ()
	Gets the fully-qualified name of the active section.

static void	generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream)
	Generate a checkpoint file so that the serialization can be routed to it.

Public Attributes inherited from gem5::ClockedObject
PowerState *	powerState

Protected Attributes inherited from gem5::memory::AbstractMemory
AddrRange	range

uint8_t *	pmemAddr

MemBackdoor	backdoor

const bool	confTableReported

const bool	inAddrMap

const bool	kvmMap

const bool	writeable

const bool	collectStats

std::list< LockedAddr >	lockedAddrList

System *	_system
	Pointer to the System object.

gem5::memory::AbstractMemory::MemStats	stats

Protected Attributes inherited from gem5::SimObject
const SimObjectParams &	_params
	Cached copy of the object parameters.

Protected Attributes inherited from gem5::EventManager
EventQueue *	eventq
	A pointer to this object's event queue.

Detailed Description

Definition at line 59 of file dramsim2.hh.

Member Typedef Documentation

◆ Params

typedef DRAMSim2Params gem5::memory::DRAMSim2::Params

Definition at line 175 of file dramsim2.hh.

Constructor & Destructor Documentation

◆ DRAMSim2()

gem5::memory::DRAMSim2::DRAMSim2 ( const Params & p )

Definition at line 53 of file dramsim2.cc.

References sendResponse().

Member Function Documentation

◆ accessAndRespond()

void gem5::memory::DRAMSim2::accessAndRespond ( PacketPtr pkt )

private

When a packet is ready, use the "access()" method in AbstractMemory to actually create the response packet, and send it back to the outside world requestor.

Parameters

pkt	The packet from the outside world

Definition at line 254 of file dramsim2.cc.

References gem5::memory::AbstractMemory::access(), gem5::curTick(), DPRINTF, gem5::Packet::getAddr(), gem5::Packet::headerDelay, gem5::Packet::isResponse(), gem5::Packet::needsResponse(), gem5::Packet::payloadDelay, pendingDelete, responseQueue, retryResp, gem5::EventManager::schedule(), gem5::Event::scheduled(), and sendResponseEvent.

Referenced by readComplete(), and recvTimingReq().

◆ drain()

DrainState gem5::memory::DRAMSim2::drain ( )

overridevirtual

Draining is the process of clearing out the states of SimObjects.These are the SimObjects that are partially executed or are partially in flight.

Draining is mostly used before forking and creating a check point.

This function notifies an object that it needs to drain its state.

If the object does not need further simulation to drain internal buffers, it returns DrainState::Drained and automatically switches to the Drained state. If the object needs more simulation, it returns DrainState::Draining and automatically enters the Draining state. Other return values are invalid.

Note: An object that has entered the Drained state can be disturbed by other objects in the system and consequently stop being drained. These perturbations are not visible in the drain state. The simulator therefore repeats the draining process until all objects return DrainState::Drained on the first call to drain().

Returns: DrainState::Drained if the object is drained at this point in time, DrainState::Draining if it needs further simulation.

Implements gem5::Drainable.

Definition at line 353 of file dramsim2.cc.

References gem5::Drained, gem5::Draining, and nbrOutstanding().

◆ getPort()

Port & gem5::memory::DRAMSim2::getPort	(	const std::string &	if_name,
		PortID	idx = InvalidPortID )

overridevirtual

Get a port with a given name and index.

This is used at binding time and returns a reference to a protocol-agnostic port.

gem5 has a request and response port interface. All memory objects are connected together via ports. These ports provide a rigid interface between these memory objects. These ports implement three different memory system modes: timing, atomic, and functional. The most important mode is the timing mode and here timing mode is used for conducting cycle-level timing experiments. The other modes are only used in special circumstances and should not be used to conduct cycle-level timing experiments. The other modes are only used in special circumstances. These ports allow SimObjects to communicate with each other.

Parameters

if_name	Port name
idx	Index in the case of a VectorPort

Returns: A reference to the given port

Reimplemented from gem5::SimObject.

Definition at line 343 of file dramsim2.cc.

References gem5::SimObject::getPort(), and port.

◆ init()

void gem5::memory::DRAMSim2::init ( )

overridevirtual

init() is called after all C++ SimObjects have been created and all ports are connected.

Initializations that are independent of unserialization but rely on a fully instantiated and connected SimObject graph should be done here.

Reimplemented from gem5::SimObject.

Definition at line 81 of file dramsim2.cc.

References gem5::memory::DRAMSim2Wrapper::burstSize(), fatal, gem5::SimObject::init(), gem5::Port::isConnected(), gem5::Named::name(), port, gem5::ResponsePort::sendRangeChange(), gem5::memory::AbstractMemory::system(), and wrapper.

◆ nbrOutstanding()

unsigned int gem5::memory::DRAMSim2::nbrOutstanding ( ) const

private

Definition at line 136 of file dramsim2.cc.

References nbrOutstandingReads, nbrOutstandingWrites, and responseQueue.

Referenced by drain(), recvTimingReq(), sendResponse(), tick(), and writeComplete().

◆ readComplete()

void gem5::memory::DRAMSim2::readComplete	(	unsigned	id,
		uint64_t	addr,
		uint64_t	cycle )

Read completion callback.

Parameters

id	Channel id of the responder
addr	Address of the request
cycle	Internal cycle count of DRAMSim2

Definition at line 290 of file dramsim2.cc.

References accessAndRespond(), gem5::X86ISA::addr, gem5::memory::DRAMSim2Wrapper::clockPeriod(), gem5::curTick(), gem5::Clocked::cycle, gem5::divCeil(), DPRINTF, nbrOutstandingReads, gem5::sim_clock::as_int::ns, outstandingReads, gem5::MipsISA::p, startTick, and wrapper.

◆ recvAtomic()

Tick gem5::memory::DRAMSim2::recvAtomic ( PacketPtr pkt )

protected

Definition at line 158 of file dramsim2.cc.

References gem5::memory::AbstractMemory::access(), and gem5::Packet::cacheResponding().

◆ recvFunctional()

void gem5::memory::DRAMSim2::recvFunctional ( PacketPtr pkt )

protected

Definition at line 167 of file dramsim2.cc.

References gem5::memory::AbstractMemory::functionalAccess(), gem5::ArmISA::i, gem5::Named::name(), gem5::Packet::popLabel(), gem5::Packet::pushLabel(), responseQueue, and gem5::Packet::trySatisfyFunctional().

◆ recvRespRetry()

void gem5::memory::DRAMSim2::recvRespRetry ( )

protected

Definition at line 244 of file dramsim2.cc.

References DPRINTF, retryResp, and sendResponse().

◆ recvTimingReq()

bool gem5::memory::DRAMSim2::recvTimingReq ( PacketPtr pkt )

protected

Definition at line 181 of file dramsim2.cc.

References accessAndRespond(), gem5::Packet::cacheResponding(), gem5::memory::DRAMSim2Wrapper::canAccept(), DPRINTF, gem5::memory::DRAMSim2Wrapper::enqueue(), gem5::Packet::getAddr(), gem5::Packet::isRead(), gem5::Packet::isWrite(), nbrOutstanding(), nbrOutstandingReads, nbrOutstandingWrites, outstandingReads, outstandingWrites, pendingDelete, gem5::memory::DRAMSim2Wrapper::queueSize(), retryReq, and wrapper.

◆ sendResponse()

void gem5::memory::DRAMSim2::sendResponse ( )

private

Definition at line 106 of file dramsim2.cc.

References gem5::curTick(), DPRINTF, nbrOutstanding(), nbrOutstandingReads, nbrOutstandingWrites, port, responseQueue, retryResp, gem5::EventManager::schedule(), gem5::Event::scheduled(), sendResponseEvent, gem5::ResponsePort::sendTimingResp(), gem5::Drainable::signalDrainDone(), and gem5::memory::AbstractMemory::size().

Referenced by DRAMSim2(), and recvRespRetry().

◆ startup()

void gem5::memory::DRAMSim2::startup ( )

overridevirtual

startup() is the final initialization call before simulation.

All state is initialized (including unserialized state, if any, such as the curTick() value), so this is the appropriate place to schedule initial event(s) for objects that need them.

Reimplemented from gem5::SimObject.

Definition at line 97 of file dramsim2.cc.

References gem5::Clocked::clockEdge(), gem5::curTick(), gem5::EventManager::schedule(), startTick, and tickEvent.

◆ tick()

void gem5::memory::DRAMSim2::tick ( )

private

Progress the controller one clock cycle.

Definition at line 142 of file dramsim2.cc.

References gem5::memory::DRAMSim2Wrapper::clockPeriod(), gem5::curTick(), nbrOutstanding(), gem5::sim_clock::as_int::ns, port, gem5::memory::DRAMSim2Wrapper::queueSize(), retryReq, gem5::EventManager::schedule(), gem5::ResponsePort::sendRetryReq(), gem5::memory::DRAMSim2Wrapper::tick(), tickEvent, and wrapper.

◆ writeComplete()

void gem5::memory::DRAMSim2::writeComplete	(	unsigned	id,
		uint64_t	addr,
		uint64_t	cycle )

Write completion callback.

Parameters

id	Channel id of the responder
addr	Address of the request
cycle	Internal cycle count of DRAMSim2

Definition at line 318 of file dramsim2.cc.

References gem5::X86ISA::addr, gem5::memory::DRAMSim2Wrapper::clockPeriod(), gem5::curTick(), gem5::Clocked::cycle, gem5::divCeil(), DPRINTF, nbrOutstanding(), nbrOutstandingWrites, gem5::sim_clock::as_int::ns, outstandingWrites, gem5::MipsISA::p, gem5::Drainable::signalDrainDone(), startTick, and wrapper.

Member Data Documentation

◆ nbrOutstandingReads

unsigned int gem5::memory::DRAMSim2::nbrOutstandingReads

private

Count the number of outstanding transactions so that we can block any further requests until there is space in DRAMSim2 and the sending queue we need to buffer the response packets.

Definition at line 129 of file dramsim2.hh.

Referenced by nbrOutstanding(), readComplete(), recvTimingReq(), and sendResponse().

◆ nbrOutstandingWrites

unsigned int gem5::memory::DRAMSim2::nbrOutstandingWrites

private

Definition at line 130 of file dramsim2.hh.

Referenced by nbrOutstanding(), recvTimingReq(), sendResponse(), and writeComplete().

◆ outstandingReads

std::unordered_map<Addr, std::queue<PacketPtr> > gem5::memory::DRAMSim2::outstandingReads

private

Keep track of what packets are outstanding per address, and do so separately for reads and writes.

This is done so that we can return the right packet on completion from DRAMSim.

Definition at line 121 of file dramsim2.hh.

Referenced by readComplete(), and recvTimingReq().

◆ outstandingWrites

std::unordered_map<Addr, std::queue<PacketPtr> > gem5::memory::DRAMSim2::outstandingWrites

private

Definition at line 122 of file dramsim2.hh.

Referenced by recvTimingReq(), and writeComplete().

◆ pendingDelete

std::unique_ptr<Packet> gem5::memory::DRAMSim2::pendingDelete

private

Upstream caches need this packet until true is returned, so hold it for deletion until a subsequent call.

Definition at line 171 of file dramsim2.hh.

Referenced by accessAndRespond(), and recvTimingReq().

◆ port

MemoryPort gem5::memory::DRAMSim2::port

private

Definition at line 93 of file dramsim2.hh.

Referenced by getPort(), init(), sendResponse(), and tick().

◆ responseQueue

std::deque<PacketPtr> gem5::memory::DRAMSim2::responseQueue

private

Queue to hold response packets until we can send them back.

This is needed as DRAMSim2 unconditionally passes responses back without any flow control.

Definition at line 137 of file dramsim2.hh.

Referenced by accessAndRespond(), nbrOutstanding(), recvFunctional(), and sendResponse().

◆ retryReq

bool gem5::memory::DRAMSim2::retryReq

private

Is the connected port waiting for a retry from us.

Definition at line 103 of file dramsim2.hh.

Referenced by recvTimingReq(), and tick().

◆ retryResp

bool gem5::memory::DRAMSim2::retryResp

private

Are we waiting for a retry for sending a response.

Definition at line 108 of file dramsim2.hh.

Referenced by accessAndRespond(), recvRespRetry(), and sendResponse().

◆ sendResponseEvent

EventFunctionWrapper gem5::memory::DRAMSim2::sendResponseEvent

private

Event to schedule sending of responses.

Definition at line 155 of file dramsim2.hh.

Referenced by accessAndRespond(), and sendResponse().

◆ startTick

Tick gem5::memory::DRAMSim2::startTick

private

Keep track of when the wrapper is started.

Definition at line 113 of file dramsim2.hh.

Referenced by readComplete(), startup(), and writeComplete().

◆ tickEvent

EventFunctionWrapper gem5::memory::DRAMSim2::tickEvent

private

Event to schedule clock ticks.

Definition at line 165 of file dramsim2.hh.

Referenced by startup(), and tick().

◆ wrapper

DRAMSim2Wrapper gem5::memory::DRAMSim2::wrapper

private

The actual DRAMSim2 wrapper.

Definition at line 98 of file dramsim2.hh.

Referenced by init(), readComplete(), recvTimingReq(), tick(), and writeComplete().

The documentation for this class was generated from the following files:

mem/dramsim2.hh
mem/dramsim2.cc

Classes

Public Types

Public Member Functions

Protected Member Functions

Private Member Functions

Private Attributes

Additional Inherited Members

Detailed Description

Member Typedef Documentation

◆ Params

Constructor & Destructor Documentation

◆ DRAMSim2()

Member Function Documentation

◆ accessAndRespond()

◆ drain()

◆ getPort()

◆ init()

◆ nbrOutstanding()

◆ readComplete()

◆ recvAtomic()

◆ recvFunctional()

◆ recvRespRetry()

◆ recvTimingReq()

◆ sendResponse()

◆ startup()

◆ tick()

◆ writeComplete()

Member Data Documentation

◆ nbrOutstandingReads

◆ nbrOutstandingWrites

◆ outstandingReads

◆ outstandingWrites

◆ pendingDelete

◆ port

◆ responseQueue

◆ retryReq

◆ retryResp

◆ sendResponseEvent

◆ startTick

◆ tickEvent

◆ wrapper