gem5  v21.1.0.2
Classes | Public Types | Public Member Functions | Protected Member Functions | Private Member Functions | Private Attributes | List of all members
gem5::memory::DRAMSim2 Class Reference

#include <dramsim2.hh>

Inheritance diagram for gem5::memory::DRAMSim2:
gem5::memory::AbstractMemory gem5::ClockedObject gem5::SimObject gem5::Clocked gem5::EventManager gem5::Serializable gem5::Drainable gem5::statistics::Group gem5::Named

Classes

class  MemoryPort
 The memory port has to deal with its own flow control to avoid having unbounded storage that is implicitly created in the port itself. More...
 

Public Types

typedef DRAMSim2Params Params
 
- Public Types inherited from gem5::ClockedObject
using Params = ClockedObjectParams
 Parameters of ClockedObject. More...
 
- Public Types inherited from gem5::SimObject
typedef SimObjectParams Params
 

Public Member Functions

 DRAMSim2 (const Params &p)
 
void readComplete (unsigned id, uint64_t addr, uint64_t cycle)
 Read completion callback. More...
 
void writeComplete (unsigned id, uint64_t addr, uint64_t cycle)
 Write completion callback. More...
 
DrainState drain () override
 Draining is the process of clearing out the states of SimObjects.These are the SimObjects that are partially executed or are partially in flight. More...
 
PortgetPort (const std::string &if_name, PortID idx=InvalidPortID) override
 Get a port with a given name and index. More...
 
void init () override
 init() is called after all C++ SimObjects have been created and all ports are connected. More...
 
void startup () override
 startup() is the final initialization call before simulation. More...
 
- Public Member Functions inherited from gem5::memory::AbstractMemory
 PARAMS (AbstractMemory)
 
 AbstractMemory (const Params &p)
 
virtual ~AbstractMemory ()
 
void initState () override
 initState() is called on each SimObject when not restoring from a checkpoint. More...
 
bool isNull () const
 See if this is a null memory that should never store data and always return zero. More...
 
void setBackingStore (uint8_t *pmem_addr)
 Set the host memory backing store to be used by this memory controller. More...
 
void getBackdoor (MemBackdoorPtr &bd_ptr)
 
const std::list< LockedAddr > & getLockedAddrList () const
 Get the list of locked addresses to allow checkpointing. More...
 
void addLockedAddr (LockedAddr addr)
 Add a locked address to allow for checkpointing. More...
 
Systemsystem () const
 read the system pointer Implemented for completeness with the setter More...
 
void system (System *sys)
 Set the system pointer on this memory This can't be done via a python parameter because the system needs pointers to all the memories and the reverse would create a cycle in the object graph. More...
 
AddrRange getAddrRange () const
 Get the address range. More...
 
uint8_t * toHostAddr (Addr addr) const
 Transform a gem5 address space address into its physical counterpart in the host address space. More...
 
uint64_t size () const
 Get the memory size. More...
 
Addr start () const
 Get the start address. More...
 
bool isConfReported () const
 Should this memory be passed to the kernel and part of the OS physical memory layout. More...
 
bool isInAddrMap () const
 Some memories are used as shadow memories or should for other reasons not be part of the global address map. More...
 
bool isKvmMap () const
 When shadow memories are in use, KVM may want to make one or the other, but cannot map both into the guest address space. More...
 
void access (PacketPtr pkt)
 Perform an untimed memory access and update all the state (e.g. More...
 
void functionalAccess (PacketPtr pkt)
 Perform an untimed memory read or write without changing anything but the memory itself. More...
 
- Public Member Functions inherited from gem5::ClockedObject
 ClockedObject (const ClockedObjectParams &p)
 
void serialize (CheckpointOut &cp) const override
 Serialize an object. More...
 
void unserialize (CheckpointIn &cp) override
 Unserialize an object. More...
 
- Public Member Functions inherited from gem5::SimObject
const Paramsparams () const
 
 SimObject (const Params &p)
 
virtual ~SimObject ()
 
virtual void loadState (CheckpointIn &cp)
 loadState() is called on each SimObject when restoring from a checkpoint. More...
 
virtual void regProbePoints ()
 Register probe points for this object. More...
 
virtual void regProbeListeners ()
 Register probe listeners for this object. More...
 
ProbeManagergetProbeManager ()
 Get the probe manager for this object. More...
 
DrainState drain () override
 Provide a default implementation of the drain interface for objects that don't need draining. More...
 
virtual void memWriteback ()
 Write back dirty buffers to memory using functional writes. More...
 
virtual void memInvalidate ()
 Invalidate the contents of memory buffers. More...
 
void serialize (CheckpointOut &cp) const override
 Serialize an object. More...
 
void unserialize (CheckpointIn &cp) override
 Unserialize an object. More...
 
- Public Member Functions inherited from gem5::EventManager
EventQueueeventQueue () const
 
void schedule (Event &event, Tick when)
 
void deschedule (Event &event)
 
void reschedule (Event &event, Tick when, bool always=false)
 
void schedule (Event *event, Tick when)
 
void deschedule (Event *event)
 
void reschedule (Event *event, Tick when, bool always=false)
 
void wakeupEventQueue (Tick when=(Tick) -1)
 This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers. More...
 
void setCurTick (Tick newVal)
 
 EventManager (EventManager &em)
 Event manger manages events in the event queue. More...
 
 EventManager (EventManager *em)
 
 EventManager (EventQueue *eq)
 
- Public Member Functions inherited from gem5::Serializable
 Serializable ()
 
virtual ~Serializable ()
 
void serializeSection (CheckpointOut &cp, const char *name) const
 Serialize an object into a new section. More...
 
void serializeSection (CheckpointOut &cp, const std::string &name) const
 
void unserializeSection (CheckpointIn &cp, const char *name)
 Unserialize an a child object. More...
 
void unserializeSection (CheckpointIn &cp, const std::string &name)
 
- Public Member Functions inherited from gem5::Drainable
DrainState drainState () const
 Return the current drain state of an object. More...
 
virtual void notifyFork ()
 Notify a child process of a fork. More...
 
- Public Member Functions inherited from gem5::statistics::Group
 Group (Group *parent, const char *name=nullptr)
 Construct a new statistics group. More...
 
virtual ~Group ()
 
virtual void regStats ()
 Callback to set stat parameters. More...
 
virtual void resetStats ()
 Callback to reset stats. More...
 
virtual void preDumpStats ()
 Callback before stats are dumped. More...
 
void addStat (statistics::Info *info)
 Register a stat with this group. More...
 
const std::map< std::string, Group * > & getStatGroups () const
 Get all child groups associated with this object. More...
 
const std::vector< Info * > & getStats () const
 Get all stats associated with this object. More...
 
void addStatGroup (const char *name, Group *block)
 Add a stat block as a child of this block. More...
 
const InforesolveStat (std::string name) const
 Resolve a stat by its name within this group. More...
 
void mergeStatGroup (Group *block)
 Merge the contents (stats & children) of a block to this block. More...
 
 Group ()=delete
 
 Group (const Group &)=delete
 
Groupoperator= (const Group &)=delete
 
- Public Member Functions inherited from gem5::Named
 Named (const std::string &name_)
 
virtual ~Named ()=default
 
virtual std::string name () const
 
- Public Member Functions inherited from gem5::Clocked
void updateClockPeriod ()
 Update the tick to the current tick. More...
 
Tick clockEdge (Cycles cycles=Cycles(0)) const
 Determine the tick when a cycle begins, by default the current one, but the argument also enables the caller to determine a future cycle. More...
 
Cycles curCycle () const
 Determine the current cycle, corresponding to a tick aligned to a clock edge. More...
 
Tick nextCycle () const
 Based on the clock of the object, determine the start tick of the first cycle that is at least one cycle in the future. More...
 
uint64_t frequency () const
 
Tick clockPeriod () const
 
double voltage () const
 
Cycles ticksToCycles (Tick t) const
 
Tick cyclesToTicks (Cycles c) const
 

Protected Member Functions

Tick recvAtomic (PacketPtr pkt)
 
void recvFunctional (PacketPtr pkt)
 
bool recvTimingReq (PacketPtr pkt)
 
void recvRespRetry ()
 
- Protected Member Functions inherited from gem5::memory::AbstractMemory
bool checkLockedAddrList (PacketPtr pkt)
 
void trackLoadLocked (PacketPtr pkt)
 
bool writeOK (PacketPtr pkt)
 
- Protected Member Functions inherited from gem5::Drainable
 Drainable ()
 
virtual ~Drainable ()
 
virtual void drainResume ()
 Resume execution after a successful drain. More...
 
void signalDrainDone () const
 Signal that an object is drained. More...
 
- Protected Member Functions inherited from gem5::Clocked
 Clocked (ClockDomain &clk_domain)
 Create a clocked object and set the clock domain based on the parameters. More...
 
 Clocked (Clocked &)=delete
 
Clockedoperator= (Clocked &)=delete
 
virtual ~Clocked ()
 Virtual destructor due to inheritance. More...
 
void resetClock () const
 Reset the object's clock using the current global tick value. More...
 
virtual void clockPeriodUpdated ()
 A hook subclasses can implement so they can do any extra work that's needed when the clock rate is changed. More...
 

Private Member Functions

unsigned int nbrOutstanding () const
 
void accessAndRespond (PacketPtr pkt)
 When a packet is ready, use the "access()" method in AbstractMemory to actually create the response packet, and send it back to the outside world requestor. More...
 
void sendResponse ()
 
void tick ()
 Progress the controller one clock cycle. More...
 

Private Attributes

MemoryPort port
 
DRAMSim2Wrapper wrapper
 The actual DRAMSim2 wrapper. More...
 
bool retryReq
 Is the connected port waiting for a retry from us. More...
 
bool retryResp
 Are we waiting for a retry for sending a response. More...
 
Tick startTick
 Keep track of when the wrapper is started. More...
 
std::unordered_map< Addr, std::queue< PacketPtr > > outstandingReads
 Keep track of what packets are outstanding per address, and do so separately for reads and writes. More...
 
std::unordered_map< Addr, std::queue< PacketPtr > > outstandingWrites
 
unsigned int nbrOutstandingReads
 Count the number of outstanding transactions so that we can block any further requests until there is space in DRAMSim2 and the sending queue we need to buffer the response packets. More...
 
unsigned int nbrOutstandingWrites
 
std::deque< PacketPtrresponseQueue
 Queue to hold response packets until we can send them back. More...
 
EventFunctionWrapper sendResponseEvent
 Event to schedule sending of responses. More...
 
EventFunctionWrapper tickEvent
 Event to schedule clock ticks. More...
 
std::unique_ptr< PacketpendingDelete
 Upstream caches need this packet until true is returned, so hold it for deletion until a subsequent call. More...
 

Additional Inherited Members

- Static Public Member Functions inherited from gem5::SimObject
static void serializeAll (const std::string &cpt_dir)
 Create a checkpoint by serializing all SimObjects in the system. More...
 
static SimObjectfind (const char *name)
 Find the SimObject with the given name and return a pointer to it. More...
 
static void setSimObjectResolver (SimObjectResolver *resolver)
 There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More...
 
static SimObjectResolvergetSimObjectResolver ()
 There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More...
 
- Static Public Member Functions inherited from gem5::Serializable
static const std::string & currentSection ()
 Gets the fully-qualified name of the active section. More...
 
static void generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream)
 Generate a checkpoint file so that the serialization can be routed to it. More...
 
- Public Attributes inherited from gem5::ClockedObject
PowerStatepowerState
 
- Protected Attributes inherited from gem5::memory::AbstractMemory
AddrRange range
 
uint8_t * pmemAddr
 
MemBackdoor backdoor
 
const bool confTableReported
 
const bool inAddrMap
 
const bool kvmMap
 
std::list< LockedAddrlockedAddrList
 
System_system
 Pointer to the System object. More...
 
gem5::memory::AbstractMemory::MemStats stats
 
- Protected Attributes inherited from gem5::SimObject
const SimObjectParams & _params
 Cached copy of the object parameters. More...
 
- Protected Attributes inherited from gem5::EventManager
EventQueueeventq
 A pointer to this object's event queue. More...
 

Detailed Description

Definition at line 59 of file dramsim2.hh.

Member Typedef Documentation

◆ Params

typedef DRAMSim2Params gem5::memory::DRAMSim2::Params

Definition at line 175 of file dramsim2.hh.

Constructor & Destructor Documentation

◆ DRAMSim2()

gem5::memory::DRAMSim2::DRAMSim2 ( const Params p)

Definition at line 53 of file dramsim2.cc.

References sendResponse().

Member Function Documentation

◆ accessAndRespond()

void gem5::memory::DRAMSim2::accessAndRespond ( PacketPtr  pkt)
private

When a packet is ready, use the "access()" method in AbstractMemory to actually create the response packet, and send it back to the outside world requestor.

Parameters
pktThe packet from the outside world

Definition at line 254 of file dramsim2.cc.

References gem5::memory::AbstractMemory::access(), gem5::curTick(), DPRINTF, gem5::Packet::getAddr(), gem5::Packet::headerDelay, gem5::Packet::isResponse(), gem5::Packet::needsResponse(), gem5::Packet::payloadDelay, pendingDelete, responseQueue, retryResp, gem5::EventManager::schedule(), gem5::Event::scheduled(), and sendResponseEvent.

Referenced by readComplete(), and recvTimingReq().

◆ drain()

DrainState gem5::memory::DRAMSim2::drain ( )
overridevirtual

Draining is the process of clearing out the states of SimObjects.These are the SimObjects that are partially executed or are partially in flight.

Draining is mostly used before forking and creating a check point.

This function notifies an object that it needs to drain its state.

If the object does not need further simulation to drain internal buffers, it returns DrainState::Drained and automatically switches to the Drained state. If the object needs more simulation, it returns DrainState::Draining and automatically enters the Draining state. Other return values are invalid.

Note
An object that has entered the Drained state can be disturbed by other objects in the system and consequently stop being drained. These perturbations are not visible in the drain state. The simulator therefore repeats the draining process until all objects return DrainState::Drained on the first call to drain().
Returns
DrainState::Drained if the object is drained at this point in time, DrainState::Draining if it needs further simulation.

Implements gem5::Drainable.

Definition at line 353 of file dramsim2.cc.

References gem5::Drained, gem5::Draining, and nbrOutstanding().

◆ getPort()

Port & gem5::memory::DRAMSim2::getPort ( const std::string &  if_name,
PortID  idx = InvalidPortID 
)
overridevirtual

Get a port with a given name and index.

This is used at binding time and returns a reference to a protocol-agnostic port.

gem5 has a request and response port interface. All memory objects are connected together via ports. These ports provide a rigid interface between these memory objects. These ports implement three different memory system modes: timing, atomic, and functional. The most important mode is the timing mode and here timing mode is used for conducting cycle-level timing experiments. The other modes are only used in special circumstances and should not be used to conduct cycle-level timing experiments. The other modes are only used in special circumstances. These ports allow SimObjects to communicate with each other.

Parameters
if_namePort name
idxIndex in the case of a VectorPort
Returns
A reference to the given port

Reimplemented from gem5::SimObject.

Definition at line 343 of file dramsim2.cc.

References gem5::SimObject::getPort(), and port.

◆ init()

void gem5::memory::DRAMSim2::init ( )
overridevirtual

init() is called after all C++ SimObjects have been created and all ports are connected.

Initializations that are independent of unserialization but rely on a fully instantiated and connected SimObject graph should be done here.

Reimplemented from gem5::SimObject.

Definition at line 81 of file dramsim2.cc.

References gem5::memory::DRAMSim2Wrapper::burstSize(), fatal, gem5::SimObject::init(), gem5::Port::isConnected(), gem5::Named::name(), port, gem5::ResponsePort::sendRangeChange(), gem5::memory::AbstractMemory::system(), and wrapper.

◆ nbrOutstanding()

unsigned int gem5::memory::DRAMSim2::nbrOutstanding ( ) const
private

◆ readComplete()

void gem5::memory::DRAMSim2::readComplete ( unsigned  id,
uint64_t  addr,
uint64_t  cycle 
)

Read completion callback.

Parameters
idChannel id of the responder
addrAddress of the request
cycleInternal cycle count of DRAMSim2

Definition at line 290 of file dramsim2.cc.

References accessAndRespond(), gem5::X86ISA::addr, gem5::memory::DRAMSim2Wrapper::clockPeriod(), gem5::curTick(), gem5::Clocked::cycle, gem5::divCeil(), DPRINTF, nbrOutstandingReads, gem5::sim_clock::as_int::ns, outstandingReads, gem5::MipsISA::p, startTick, and wrapper.

◆ recvAtomic()

Tick gem5::memory::DRAMSim2::recvAtomic ( PacketPtr  pkt)
protected

◆ recvFunctional()

void gem5::memory::DRAMSim2::recvFunctional ( PacketPtr  pkt)
protected

◆ recvRespRetry()

void gem5::memory::DRAMSim2::recvRespRetry ( )
protected

Definition at line 244 of file dramsim2.cc.

References DPRINTF, retryResp, and sendResponse().

◆ recvTimingReq()

bool gem5::memory::DRAMSim2::recvTimingReq ( PacketPtr  pkt)
protected

◆ sendResponse()

void gem5::memory::DRAMSim2::sendResponse ( )
private

◆ startup()

void gem5::memory::DRAMSim2::startup ( )
overridevirtual

startup() is the final initialization call before simulation.

All state is initialized (including unserialized state, if any, such as the curTick() value), so this is the appropriate place to schedule initial event(s) for objects that need them.

Reimplemented from gem5::SimObject.

Definition at line 97 of file dramsim2.cc.

References gem5::Clocked::clockEdge(), gem5::curTick(), gem5::EventManager::schedule(), startTick, and tickEvent.

◆ tick()

void gem5::memory::DRAMSim2::tick ( )
private

◆ writeComplete()

void gem5::memory::DRAMSim2::writeComplete ( unsigned  id,
uint64_t  addr,
uint64_t  cycle 
)

Write completion callback.

Parameters
idChannel id of the responder
addrAddress of the request
cycleInternal cycle count of DRAMSim2

Definition at line 318 of file dramsim2.cc.

References gem5::X86ISA::addr, gem5::memory::DRAMSim2Wrapper::clockPeriod(), gem5::curTick(), gem5::Clocked::cycle, gem5::divCeil(), DPRINTF, nbrOutstanding(), nbrOutstandingWrites, gem5::sim_clock::as_int::ns, outstandingWrites, gem5::MipsISA::p, gem5::Drainable::signalDrainDone(), startTick, and wrapper.

Member Data Documentation

◆ nbrOutstandingReads

unsigned int gem5::memory::DRAMSim2::nbrOutstandingReads
private

Count the number of outstanding transactions so that we can block any further requests until there is space in DRAMSim2 and the sending queue we need to buffer the response packets.

Definition at line 129 of file dramsim2.hh.

Referenced by nbrOutstanding(), readComplete(), recvTimingReq(), and sendResponse().

◆ nbrOutstandingWrites

unsigned int gem5::memory::DRAMSim2::nbrOutstandingWrites
private

Definition at line 130 of file dramsim2.hh.

Referenced by nbrOutstanding(), recvTimingReq(), sendResponse(), and writeComplete().

◆ outstandingReads

std::unordered_map<Addr, std::queue<PacketPtr> > gem5::memory::DRAMSim2::outstandingReads
private

Keep track of what packets are outstanding per address, and do so separately for reads and writes.

This is done so that we can return the right packet on completion from DRAMSim.

Definition at line 121 of file dramsim2.hh.

Referenced by readComplete(), and recvTimingReq().

◆ outstandingWrites

std::unordered_map<Addr, std::queue<PacketPtr> > gem5::memory::DRAMSim2::outstandingWrites
private

Definition at line 122 of file dramsim2.hh.

Referenced by recvTimingReq(), and writeComplete().

◆ pendingDelete

std::unique_ptr<Packet> gem5::memory::DRAMSim2::pendingDelete
private

Upstream caches need this packet until true is returned, so hold it for deletion until a subsequent call.

Definition at line 171 of file dramsim2.hh.

Referenced by accessAndRespond(), and recvTimingReq().

◆ port

MemoryPort gem5::memory::DRAMSim2::port
private

Definition at line 93 of file dramsim2.hh.

Referenced by getPort(), init(), sendResponse(), and tick().

◆ responseQueue

std::deque<PacketPtr> gem5::memory::DRAMSim2::responseQueue
private

Queue to hold response packets until we can send them back.

This is needed as DRAMSim2 unconditionally passes responses back without any flow control.

Definition at line 137 of file dramsim2.hh.

Referenced by accessAndRespond(), nbrOutstanding(), recvFunctional(), and sendResponse().

◆ retryReq

bool gem5::memory::DRAMSim2::retryReq
private

Is the connected port waiting for a retry from us.

Definition at line 103 of file dramsim2.hh.

Referenced by recvTimingReq(), and tick().

◆ retryResp

bool gem5::memory::DRAMSim2::retryResp
private

Are we waiting for a retry for sending a response.

Definition at line 108 of file dramsim2.hh.

Referenced by accessAndRespond(), recvRespRetry(), and sendResponse().

◆ sendResponseEvent

EventFunctionWrapper gem5::memory::DRAMSim2::sendResponseEvent
private

Event to schedule sending of responses.

Definition at line 155 of file dramsim2.hh.

Referenced by accessAndRespond(), and sendResponse().

◆ startTick

Tick gem5::memory::DRAMSim2::startTick
private

Keep track of when the wrapper is started.

Definition at line 113 of file dramsim2.hh.

Referenced by readComplete(), startup(), and writeComplete().

◆ tickEvent

EventFunctionWrapper gem5::memory::DRAMSim2::tickEvent
private

Event to schedule clock ticks.

Definition at line 165 of file dramsim2.hh.

Referenced by startup(), and tick().

◆ wrapper

DRAMSim2Wrapper gem5::memory::DRAMSim2::wrapper
private

The actual DRAMSim2 wrapper.

Definition at line 98 of file dramsim2.hh.

Referenced by init(), readComplete(), recvTimingReq(), tick(), and writeComplete().


The documentation for this class was generated from the following files:

Generated on Tue Sep 21 2021 12:31:27 for gem5 by doxygen 1.8.17