| _busAddr | gem5::PciDevice | protected |
| _drainManager | gem5::Drainable | private |
| _drainState | gem5::Drainable | mutableprivate |
| _name | gem5::Named | private |
| _objNameResolver | gem5::SimObject | privatestatic |
| _params | gem5::SimObject | protected |
| addStat(statistics::Info *info) | gem5::statistics::Group | |
| addStatGroup(const char *name, Group *block) | gem5::statistics::Group | |
| BARs | gem5::PciDevice | protected |
| Base(const Params &p) | gem5::sinic::Base | |
| busAddr() const | gem5::PciDevice | inline |
| cacheBlockSize() const | gem5::DmaDevice | inline |
| clockDomain | gem5::Clocked | private |
| Clocked(ClockDomain &clk_domain) | gem5::Clocked | inlineprotected |
| Clocked(Clocked &)=delete | gem5::Clocked | protected |
| clockEdge(Cycles cycles=Cycles(0)) const | gem5::Clocked | inline |
| ClockedObject(const ClockedObjectParams &p) | gem5::ClockedObject | |
| clockPeriod() const | gem5::Clocked | inline |
| clockPeriodUpdated() | gem5::Clocked | inlineprotectedvirtual |
| config | gem5::PciDevice | protected |
| configDelay | gem5::PciDevice | protected |
| cpuInterrupt() | gem5::sinic::Base | protected |
| cpuIntrAck() | gem5::sinic::Base | inlineprotected |
| cpuIntrClear() | gem5::sinic::Base | protected |
| cpuIntrEnable | gem5::sinic::Base | protected |
| cpuIntrPending() const | gem5::sinic::Base | protected |
| cpuIntrPost(Tick when) | gem5::sinic::Base | protected |
| cpuPendingIntr | gem5::sinic::Base | protected |
| curCycle() const | gem5::Clocked | inline |
| currentSection() | gem5::Serializable | static |
| cycle | gem5::Clocked | mutableprivate |
| cyclesToTicks(Cycles c) const | gem5::Clocked | inline |
| deschedule(Event &event) | gem5::EventManager | inline |
| deschedule(Event *event) | gem5::EventManager | inline |
| DmaDevice(const Params &p) | gem5::DmaDevice | |
| dmaPending() const | gem5::DmaDevice | inline |
| dmaPort | gem5::DmaDevice | protected |
| dmaRead(Addr addr, int size, Event *event, uint8_t *data, uint32_t sid, uint32_t ssid, Tick delay=0) | gem5::DmaDevice | inline |
| dmaRead(Addr addr, int size, Event *event, uint8_t *data, Tick delay=0) | gem5::DmaDevice | inline |
| dmaWrite(Addr addr, int size, Event *event, uint8_t *data, uint32_t sid, uint32_t ssid, Tick delay=0) | gem5::DmaDevice | inline |
| dmaWrite(Addr addr, int size, Event *event, uint8_t *data, Tick delay=0) | gem5::DmaDevice | inline |
| dmDrain() | gem5::Drainable | private |
| dmDrainResume() | gem5::Drainable | private |
| drain() override | gem5::SimObject | inlinevirtual |
| Drainable() | gem5::Drainable | protected |
| drainResume() | gem5::Drainable | inlineprotectedvirtual |
| drainState() const | gem5::Drainable | inline |
| EtherDevBase(const Params ¶ms) | gem5::EtherDevBase | inline |
| EtherDevice(const Params ¶ms) | gem5::EtherDevice | inline |
| etherDeviceStats | gem5::EtherDevice | protected |
| EventManager(EventManager &em) | gem5::EventManager | inline |
| EventManager(EventManager *em) | gem5::EventManager | inline |
| EventManager(EventQueue *eq) | gem5::EventManager | inline |
| eventq | gem5::EventManager | protected |
| eventQueue() const | gem5::EventManager | inline |
| find(const char *name) | gem5::SimObject | static |
| frequency() const | gem5::Clocked | inline |
| generateCheckpointOut(const std::string &cpt_dir, std::ofstream &outstream) | gem5::Serializable | static |
| getAddrRanges() const override | gem5::PciDevice | virtual |
| getBAR(Addr addr, int &num, Addr &offs) | gem5::PciDevice | inlineprotected |
| getPort(const std::string &if_name, PortID idx=InvalidPortID) override | gem5::DmaDevice | virtual |
| getProbeManager() | gem5::SimObject | |
| getSimObjectResolver() | gem5::SimObject | static |
| getStatGroups() const | gem5::statistics::Group | |
| getStats() const | gem5::statistics::Group | |
| Group()=delete | gem5::statistics::Group | |
| Group(const Group &)=delete | gem5::statistics::Group | |
| Group(Group *parent, const char *name=nullptr) | gem5::statistics::Group | |
| hostInterface | gem5::PciDevice | protected |
| init() override | gem5::DmaDevice | virtual |
| initState() | gem5::SimObject | virtual |
| interface | gem5::sinic::Base | protected |
| interruptLine() const | gem5::PciDevice | inline |
| intrClear() | gem5::PciDevice | inline |
| intrDelay | gem5::sinic::Base | protected |
| intrEvent | gem5::sinic::Base | protected |
| intrPost() | gem5::PciDevice | inline |
| intrTick | gem5::sinic::Base | protected |
| loadState(CheckpointIn &cp) | gem5::SimObject | virtual |
| memInvalidate() | gem5::SimObject | inlinevirtual |
| memWriteback() | gem5::SimObject | inlinevirtual |
| mergedParent | gem5::statistics::Group | private |
| mergedStatGroups | gem5::statistics::Group | private |
| mergeStatGroup(Group *block) | gem5::statistics::Group | |
| msicap | gem5::PciDevice | protected |
| MSICAP_BASE | gem5::PciDevice | protected |
| msix_pba | gem5::PciDevice | protected |
| MSIX_PBA_END | gem5::PciDevice | protected |
| MSIX_PBA_OFFSET | gem5::PciDevice | protected |
| msix_table | gem5::PciDevice | protected |
| MSIX_TABLE_END | gem5::PciDevice | protected |
| MSIX_TABLE_OFFSET | gem5::PciDevice | protected |
| msixcap | gem5::PciDevice | protected |
| MSIXCAP_BASE | gem5::PciDevice | protected |
| MSIXCAP_ID_OFFSET | gem5::PciDevice | protected |
| MSIXCAP_MPBA_OFFSET | gem5::PciDevice | protected |
| MSIXCAP_MTAB_OFFSET | gem5::PciDevice | protected |
| MSIXCAP_MXC_OFFSET | gem5::PciDevice | protected |
| name() const | gem5::Named | inlinevirtual |
| Named(const std::string &name_) | gem5::Named | inline |
| nextCycle() const | gem5::Clocked | inline |
| notifyFork() | gem5::Drainable | inlinevirtual |
| gem5::operator=(const Group &)=delete | gem5::statistics::Group | |
| gem5::Clocked::operator=(Clocked &)=delete | gem5::Clocked | protected |
| PARAMS(Sinic) | gem5::sinic::Base | |
| Params typedef | gem5::EtherDevBase | |
| params() const | gem5::SimObject | inline |
| path | gem5::Serializable | privatestatic |
| PciDevice(const PciDeviceParams ¶ms) | gem5::PciDevice | |
| pciToDma(Addr pci_addr) const | gem5::PciDevice | inline |
| pioDelay | gem5::PciDevice | protected |
| PioDevice(const Params &p) | gem5::PioDevice | |
| pioPort | gem5::PioDevice | protected |
| pmcap | gem5::PciDevice | protected |
| PMCAP_BASE | gem5::PciDevice | protected |
| PMCAP_ID_OFFSET | gem5::PciDevice | protected |
| PMCAP_PC_OFFSET | gem5::PciDevice | protected |
| PMCAP_PMCS_OFFSET | gem5::PciDevice | protected |
| powerState | gem5::ClockedObject | |
| preDumpStats() | gem5::statistics::Group | virtual |
| probeManager | gem5::SimObject | private |
| pxcap | gem5::PciDevice | protected |
| PXCAP_BASE | gem5::PciDevice | protected |
| read(PacketPtr pkt)=0 | gem5::PioDevice | protectedpure virtual |
| readConfig(PacketPtr pkt) | gem5::PciDevice | virtual |
| regProbeListeners() | gem5::SimObject | virtual |
| regProbePoints() | gem5::SimObject | virtual |
| regStats() | gem5::statistics::Group | virtual |
| reschedule(Event &event, Tick when, bool always=false) | gem5::EventManager | inline |
| reschedule(Event *event, Tick when, bool always=false) | gem5::EventManager | inline |
| resetClock() const | gem5::Clocked | inlineprotected |
| resetStats() | gem5::statistics::Group | virtual |
| resolveStat(std::string name) const | gem5::statistics::Group | |
| rxEnable | gem5::sinic::Base | protected |
| schedule(Event &event, Tick when) | gem5::EventManager | inline |
| schedule(Event *event, Tick when) | gem5::EventManager | inline |
| Serializable() | gem5::Serializable | |
| serialize(CheckpointOut &cp) const override | gem5::sinic::Base | virtual |
| serializeAll(const std::string &cpt_dir) | gem5::SimObject | static |
| serializeSection(CheckpointOut &cp, const char *name) const | gem5::Serializable | |
| serializeSection(CheckpointOut &cp, const std::string &name) const | gem5::Serializable | inline |
| setCurTick(Tick newVal) | gem5::EventManager | inline |
| setSimObjectResolver(SimObjectResolver *resolver) | gem5::SimObject | static |
| signalDrainDone() const | gem5::Drainable | inlineprotected |
| SimObject(const Params &p) | gem5::SimObject | |
| SimObjectList typedef | gem5::SimObject | private |
| simObjectList | gem5::SimObject | privatestatic |
| startup() | gem5::SimObject | virtual |
| statGroups | gem5::statistics::Group | private |
| stats | gem5::statistics::Group | private |
| sys | gem5::PioDevice | protected |
| tick | gem5::Clocked | mutableprivate |
| ticksToCycles(Tick t) const | gem5::Clocked | inline |
| txEnable | gem5::sinic::Base | protected |
| unserialize(CheckpointIn &cp) override | gem5::sinic::Base | virtual |
| unserializeSection(CheckpointIn &cp, const char *name) | gem5::Serializable | |
| unserializeSection(CheckpointIn &cp, const std::string &name) | gem5::Serializable | inline |
| update() const | gem5::Clocked | inlineprivate |
| updateClockPeriod() | gem5::Clocked | inline |
| voltage() const | gem5::Clocked | inline |
| wakeupEventQueue(Tick when=(Tick) -1) | gem5::EventManager | inline |
| write(PacketPtr pkt)=0 | gem5::PioDevice | protectedpure virtual |
| writeConfig(PacketPtr pkt) | gem5::PciDevice | virtual |
| ~Clocked() | gem5::Clocked | inlineprotectedvirtual |
| ~DmaDevice()=default | gem5::DmaDevice | virtual |
| ~Drainable() | gem5::Drainable | protectedvirtual |
| ~Group() | gem5::statistics::Group | virtual |
| ~Named()=default | gem5::Named | virtual |
| ~PioDevice() | gem5::PioDevice | virtual |
| ~Serializable() | gem5::Serializable | virtual |
| ~SimObject() | gem5::SimObject | virtual |