32 #ifndef __GPU_COMPUTE_OPERAND_INFO_HH__
33 #define __GPU_COMPUTE_OPERAND_INFO_HH__
35 #include "arch/gpu_registers.hh"
37 #include "config/the_gpu_isa.hh"
47 bool vector_reg,
bool imm)
const int _size
Size of the operand in bytes.
const std::vector< int > & physIndices() const
std::vector< int > _physIndices
bool isFlatScratch() const
std::vector< int > & bankReadCounts() const
int physIdx(int reg_num=0) const
void setVirtToPhysMapping(std::vector< int > v, std::vector< int > p)
const int _numDWords
Size of operand in DWords.
int registerIndex(int numScalarRegs) const
std::vector< int > _virtIndices
OperandInfo(int opSelectorVal, int size, bool src, bool scalar_reg, bool vector_reg, bool imm)
const int _opSelectorVal
Value of the operand as used in registers.cc functions.
std::vector< int > _bankReadCounts
The number of reads this operand will make to each bank.
const std::vector< int > & virtIndices() const
int rawRegisterIndex() const
gem5::Flags< FlagsType > Flags
int virtIdx(int reg_num=0) const
We typically only need the first virtual register for the operand regardless of its size.
void set(Type mask)
Set all flag's bits matching the given mask.
bool isSet(Type mask) const
Verifies whether any bit matching the given mask is set.
bool isFlatScratchReg(int opIdx)
int opSelectorToRegIdx(int opIdx, int numScalarRegs)
bool isExecMask(int opIdx)
bool isPosConstVal(int opIdx)
bool isConstVal(int opIdx)
bool isLiteral(int opIdx)
const int RegSizeDWords
Size of a single-precision register in DWords.
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....