gem5  v22.0.0.1
operand_info.hh
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31 
32 #ifndef __GPU_COMPUTE_OPERAND_INFO_HH__
33 #define __GPU_COMPUTE_OPERAND_INFO_HH__
34 
35 #include "arch/gpu_registers.hh"
36 #include "base/flags.hh"
37 #include "config/the_gpu_isa.hh"
38 
39 namespace gem5
40 {
41 
43 {
44  public:
45  OperandInfo() = delete;
46  OperandInfo(int opSelectorVal, int size, bool src, bool scalar_reg,
47  bool vector_reg, bool imm)
48  : _opSelectorVal(opSelectorVal), _size(size),
49  _numDWords(size <= 4 ? 1 : size / 4)
50  {
51  if (src)
52  flags.set(SRC);
53  if (scalar_reg)
55  if (vector_reg)
57  if (imm)
59  if (TheGpuISA::isVccReg(opSelectorVal))
60  flags.set(VCC);
61  if (TheGpuISA::isExecMask(opSelectorVal))
62  flags.set(EXEC);
63  if (TheGpuISA::isFlatScratchReg(opSelectorVal))
64  flags.set(FLAT);
65  if (TheGpuISA::isLiteral(opSelectorVal))
66  flags.set(LITERAL);
67  if (TheGpuISA::isConstVal(opSelectorVal))
69  if (TheGpuISA::isPosConstVal(opSelectorVal))
71  }
72 
74  int sizeInDWords() const { return _numDWords; }
75 
76  int size() const { return _size; }
77  // Certain opIdx's get changed in calls to opSelectorToRegIdx
78  // This avoids that by returning the exact value
79  int rawRegisterIndex() const { return _opSelectorVal; }
80 
81  int
82  registerIndex(int numScalarRegs) const
83  {
84  // Some regs (i.e. VSRC, VDST) are explicitly declared as vectors
85  // as opposed to checking if it's a vector through a function call, so
86  // they don't have an offset applied and can be returned immediately
88  return _opSelectorVal;
89  return TheGpuISA::opSelectorToRegIdx(_opSelectorVal, numScalarRegs);
90  }
91  bool isSrc() const { return flags.isSet(SRC); }
92  bool isDst() const { return !flags.isSet(SRC); }
93  bool isImm() const { return flags.isSet(IMMEDIATE); }
94  bool isScalarReg() const { return flags.isSet(SCALAR_REG); }
95  bool isVectorReg() const { return flags.isSet(VECTOR_REG); }
96  bool isVcc() const { return flags.isSet(VCC); }
97  bool isExec() const { return flags.isSet(EXEC); }
98  bool isFlatScratch() const { return flags.isSet(FLAT); }
99 
100  void
102  {
103  _virtIndices = v;
104  _physIndices = p;
105 
106  assert(_virtIndices.size() == _physIndices.size());
107  assert(_numDWords == _physIndices.size());
108  }
109 
114  int virtIdx(int reg_num=0) const { return _virtIndices.at(reg_num); }
115  int physIdx(int reg_num=0) const { return _physIndices.at(reg_num); }
116 
117  const std::vector<int>&
118  virtIndices() const
119  {
120  return _virtIndices;
121  }
122 
123  const std::vector<int>&
124  physIndices() const
125  {
126  return _physIndices;
127  }
128 
131  {
132  return _bankReadCounts;
133  }
134 
135  typedef uint32_t FlagsType;
137 
138  private:
139 
140  enum : FlagsType {
141  // If the operand is a src or not
142  SRC = 0x00000001,
143 
144  // If the operand is a scalar or not
145  SCALAR_REG = 0x00000002,
146 
147  // If the operand is a vector or not
148  VECTOR_REG = 0x00000004,
149 
150  // If the operand is an immediate or not
151  IMMEDIATE = 0x00000008,
152 
153  // If the operand is a VCC register
154  VCC = 0x00000010,
155 
156  // If the operand is an EXEC register
157  EXEC = 0x00000020,
158 
159  // If the operand is a FLAT/SCRATCH register
160  FLAT = 0x00000040,
161 
162  // If the operand is a literal
163  LITERAL = 0x00000080,
164 
165  // If the operand is a constant value
166  CONSTANT = 0x00000100,
167 
168  // If the constant is positive or negative
169  POS_CONST = 0x00000200
170  };
171 
173 
177  const int _opSelectorVal;
178 
182  const int _size;
183 
187  const int _numDWords;
188 
191 
196 };
197 
198 } // namespace gem5
199 
200 #endif // __GPU_COMPUTE_OPERAND_INFO_H__
gem5::OperandInfo::FLAT
@ FLAT
Definition: operand_info.hh:160
gem5::Gcn3ISA::REG_VGPR_MIN
@ REG_VGPR_MIN
Definition: gpu_registers.hh:131
gem5::OperandInfo::SCALAR_REG
@ SCALAR_REG
Definition: operand_info.hh:145
gem5::Gcn3ISA::isPosConstVal
bool isPosConstVal(int opIdx)
Definition: registers.cc:167
gem5::OperandInfo
Definition: operand_info.hh:42
gem5::Flags::set
void set(Type mask)
Set all flag's bits matching the given mask.
Definition: flags.hh:116
gem5::OperandInfo::Flags
gem5::Flags< FlagsType > Flags
Definition: operand_info.hh:136
gem5::OperandInfo::_size
const int _size
Size of the operand in bytes.
Definition: operand_info.hh:182
gem5::OperandInfo::OperandInfo
OperandInfo(int opSelectorVal, int size, bool src, bool scalar_reg, bool vector_reg, bool imm)
Definition: operand_info.hh:46
gem5::OperandInfo::CONSTANT
@ CONSTANT
Definition: operand_info.hh:166
std::vector< int >
gem5::Gcn3ISA::isVccReg
bool isVccReg(int opIdx)
Definition: registers.cc:204
gem5::OperandInfo::virtIndices
const std::vector< int > & virtIndices() const
Definition: operand_info.hh:118
gem5::OperandInfo::isVcc
bool isVcc() const
Definition: operand_info.hh:96
gem5::Gcn3ISA::isExecMask
bool isExecMask(int opIdx)
Definition: registers.cc:198
gem5::OperandInfo::_physIndices
std::vector< int > _physIndices
Definition: operand_info.hh:190
gem5::OperandInfo::isImm
bool isImm() const
Definition: operand_info.hh:93
gem5::Flags< FlagsType >
gem5::OperandInfo::VCC
@ VCC
Definition: operand_info.hh:154
gem5::Gcn3ISA::isLiteral
bool isLiteral(int opIdx)
Definition: registers.cc:192
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::Flags::isSet
bool isSet(Type mask) const
Verifies whether any bit matching the given mask is set.
Definition: flags.hh:83
gem5::OperandInfo::FlagsType
uint32_t FlagsType
Definition: operand_info.hh:135
gem5::OperandInfo::POS_CONST
@ POS_CONST
Definition: operand_info.hh:169
gem5::Gcn3ISA::opSelectorToRegIdx
int opSelectorToRegIdx(int opIdx, int numScalarRegs)
Definition: registers.cc:122
gem5::OperandInfo::isVectorReg
bool isVectorReg() const
Definition: operand_info.hh:95
gem5::OperandInfo::IMMEDIATE
@ IMMEDIATE
Definition: operand_info.hh:151
gem5::OperandInfo::setVirtToPhysMapping
void setVirtToPhysMapping(std::vector< int > v, std::vector< int > p)
Definition: operand_info.hh:101
gem5::OperandInfo::isExec
bool isExec() const
Definition: operand_info.hh:97
gem5::OperandInfo::isFlatScratch
bool isFlatScratch() const
Definition: operand_info.hh:98
gem5::Gcn3ISA::RegSizeDWords
const int RegSizeDWords
Size of a single-precision register in DWords.
Definition: gpu_registers.hh:176
gem5::OperandInfo::sizeInDWords
int sizeInDWords() const
Definition: operand_info.hh:74
gem5::OperandInfo::LITERAL
@ LITERAL
Definition: operand_info.hh:163
gem5::OperandInfo::size
int size() const
Definition: operand_info.hh:76
gem5::OperandInfo::registerIndex
int registerIndex(int numScalarRegs) const
Definition: operand_info.hh:82
gem5::OperandInfo::_opSelectorVal
const int _opSelectorVal
Value of the operand as used in registers.cc functions.
Definition: operand_info.hh:177
flags.hh
gem5::OperandInfo::_virtIndices
std::vector< int > _virtIndices
Definition: operand_info.hh:189
gem5::VegaISA::v
Bitfield< 0 > v
Definition: pagetable.hh:65
gem5::ArmISA::imm
Bitfield< 7, 0 > imm
Definition: types.hh:132
gem5::OperandInfo::flags
Flags flags
Definition: operand_info.hh:172
gem5::OperandInfo::VECTOR_REG
@ VECTOR_REG
Definition: operand_info.hh:148
gem5::OperandInfo::EXEC
@ EXEC
Definition: operand_info.hh:157
gem5::OperandInfo::isSrc
bool isSrc() const
Definition: operand_info.hh:91
gem5::OperandInfo::SRC
@ SRC
Definition: operand_info.hh:142
gem5::OperandInfo::_bankReadCounts
std::vector< int > _bankReadCounts
The number of reads this operand will make to each bank.
Definition: operand_info.hh:195
gem5::OperandInfo::isScalarReg
bool isScalarReg() const
Definition: operand_info.hh:94
gem5::OperandInfo::rawRegisterIndex
int rawRegisterIndex() const
Definition: operand_info.hh:79
gem5::OperandInfo::_numDWords
const int _numDWords
Size of operand in DWords.
Definition: operand_info.hh:187
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::OperandInfo::virtIdx
int virtIdx(int reg_num=0) const
We typically only need the first virtual register for the operand regardless of its size.
Definition: operand_info.hh:114
gem5::OperandInfo::physIndices
const std::vector< int > & physIndices() const
Definition: operand_info.hh:124
gem5::OperandInfo::bankReadCounts
std::vector< int > & bankReadCounts() const
Definition: operand_info.hh:130
gem5::OperandInfo::isDst
bool isDst() const
Definition: operand_info.hh:92
gem5::OperandInfo::physIdx
int physIdx(int reg_num=0) const
Definition: operand_info.hh:115
gem5::OperandInfo::numRegisters
int numRegisters() const
Definition: operand_info.hh:73
gem5::Gcn3ISA::isConstVal
bool isConstVal(int opIdx)
Definition: registers.cc:185
gem5::OperandInfo::OperandInfo
OperandInfo()=delete
gem5::Gcn3ISA::isFlatScratchReg
bool isFlatScratchReg(int opIdx)
Definition: registers.cc:210

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