gem5  v21.1.0.2
pc.cc
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28 
33 #include "dev/x86/pc.hh"
34 
35 #include "arch/x86/intmessage.hh"
36 #include "arch/x86/x86_traits.hh"
37 #include "dev/x86/i82094aa.hh"
38 #include "dev/x86/i8254.hh"
39 #include "dev/x86/i8259.hh"
40 #include "dev/x86/south_bridge.hh"
41 #include "sim/system.hh"
42 
43 namespace gem5
44 {
45 
46 Pc::Pc(const Params &p) : Platform(p), southBridge(p.south_bridge)
47 {}
48 
49 void
51 {
52  assert(southBridge);
53 
54  /*
55  * Initialize the timer.
56  */
57  auto &timer = *southBridge->pit;
58  //Timer 0, mode 2, no bcd, 16 bit count
59  timer.writeControl(0x34);
60  //Timer 0, latch command
61  timer.writeControl(0x00);
62  //Write a 16 bit count of 0
63  timer.writeCounter(0, 0);
64  timer.writeCounter(0, 0);
65 
66  /*
67  * Initialize the I/O APIC.
68  */
70  X86ISA::I82094AA::RedirTableEntry entry = 0;
72  entry.vector = 0x20;
73  ioApic.writeReg(0x10, entry.bottomDW);
74  ioApic.writeReg(0x11, entry.topDW);
75  entry.deliveryMode = X86ISA::delivery_mode::Fixed;
76  entry.vector = 0x24;
77  ioApic.writeReg(0x18, entry.bottomDW);
78  ioApic.writeReg(0x19, entry.topDW);
79  entry.mask = 1;
80  entry.vector = 0x21;
81  ioApic.writeReg(0x12, entry.bottomDW);
82  ioApic.writeReg(0x13, entry.topDW);
83  entry.vector = 0x20;
84  ioApic.writeReg(0x14, entry.bottomDW);
85  ioApic.writeReg(0x15, entry.topDW);
86  entry.vector = 0x28;
87  ioApic.writeReg(0x20, entry.bottomDW);
88  ioApic.writeReg(0x21, entry.topDW);
89  entry.vector = 0x2C;
90  ioApic.writeReg(0x28, entry.bottomDW);
91  ioApic.writeReg(0x29, entry.topDW);
92  entry.vector = 0x2E;
93  ioApic.writeReg(0x2C, entry.bottomDW);
94  ioApic.writeReg(0x2D, entry.topDW);
95  entry.vector = 0x30;
96  ioApic.writeReg(0x30, entry.bottomDW);
97  ioApic.writeReg(0x31, entry.topDW);
98 
99  /*
100  * Mask the PICs. I'm presuming the BIOS/bootloader would have cleared
101  * these out and masked them before passing control to the OS.
102  */
105 }
106 
107 void
109 {
112 }
113 
114 void
116 {
117  warn_once("Don't know what interrupt to clear for console.\n");
118  //panic("Need implementation\n");
119 }
120 
121 void
122 Pc::postPciInt(int line)
123 {
125 }
126 
127 void
129 {
130  warn_once("Tried to clear PCI interrupt %d\n", line);
131 }
132 
133 } // namespace gem5
gem5::scmi::Platform
Definition: scmi_platform.hh:264
x86_traits.hh
gem5::Pc::init
void init() override
Do platform initialization stuff.
Definition: pc.cc:50
system.hh
south_bridge.hh
gem5::SouthBridge::pic1
X86ISA::I8259 * pic1
Definition: south_bridge.hh:53
warn_once
#define warn_once(...)
Definition: logging.hh:249
gem5::SouthBridge::pit
X86ISA::I8254 * pit
Definition: south_bridge.hh:52
intmessage.hh
gem5::SouthBridge::ioApic
X86ISA::I82094AA * ioApic
Definition: south_bridge.hh:57
gem5::Pc::southBridge
SouthBridge * southBridge
Definition: pc.hh:49
gem5::X86ISA::delivery_mode::Fixed
@ Fixed
Definition: intmessage.hh:60
gem5::X86ISA::I8259::maskAll
void maskAll()
Definition: i8259.hh:106
gem5::Pc::clearConsoleInt
void clearConsoleInt() override
Definition: pc.cc:115
gem5::X86ISA::I82094AA::deliveryMode
Bitfield< 10, 8 > deliveryMode
Definition: i82094aa.hh:64
pc.hh
i82094aa.hh
gem5::X86ISA::I82094AA::writeReg
void writeReg(uint8_t offset, uint32_t value)
Definition: i82094aa.cc:132
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::X86ISA::I82094AA
Definition: i82094aa.hh:49
gem5::Pc::postPciInt
void postPciInt(int line) override
Definition: pc.cc:122
gem5::X86ISA::I8254::writeControl
void writeControl(uint8_t val)
Definition: i8254.hh:114
gem5::Pc::Pc
Pc(const Params &p)
Definition: pc.cc:46
gem5::X86ISA::delivery_mode::ExtInt
@ ExtInt
Definition: intmessage.hh:66
gem5::Pc::postConsoleInt
void postConsoleInt() override
Definition: pc.cc:108
i8259.hh
gem5::SouthBridge::pic2
X86ISA::I8259 * pic2
Definition: south_bridge.hh:54
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::X86ISA::I8259::signalInterrupt
void signalInterrupt(int line)
Definition: i8259.cc:274
i8254.hh
gem5::Pc::clearPciInt
void clearPciInt(int line) override
Definition: pc.cc:128
gem5::X86ISA::I82094AA::signalInterrupt
void signalInterrupt(int line)
Definition: i82094aa.cc:182
gem5::Pc::Params
PcParams Params
Definition: pc.hh:52

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