gem5 v24.0.0.0
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#include "arch/x86/x86_traits.hh"
#include "base/bitunion.hh"
#include "base/compiler.hh"
#include "base/types.hh"
#include "dev/x86/intdev.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "mem/request.hh"
Go to the source code of this file.
Namespaces | |
namespace | gem5 |
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved. | |
namespace | gem5::X86ISA |
This is exposed globally, independent of the ISA. | |
Functions | |
gem5::X86ISA::BitUnion32 (TriggerIntMessage) Bitfield< 7 | |
gem5::X86ISA::EndBitUnion (TriggerIntMessage) namespace delivery_mode | |
static PacketPtr | gem5::X86ISA::buildIntTriggerPacket (int id, TriggerIntMessage message) |
static PacketPtr | gem5::X86ISA::buildIntAcknowledgePacket () |
Variables | |
gem5::X86ISA::destination | |
Bitfield< 15, 8 > | gem5::X86ISA::vector |
Bitfield< 18, 16 > | gem5::X86ISA::deliveryMode |
Bitfield< 19 > | gem5::X86ISA::destMode |
Bitfield< 20 > | gem5::X86ISA::level |
Bitfield< 21 > | gem5::X86ISA::trigger |
static const Addr | gem5::X86ISA::TriggerIntOffset = 0 |