gem5  v21.1.0.2
i82094aa.cc
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28 
29 #include "dev/x86/i82094aa.hh"
30 
31 #include <list>
32 
33 #include "arch/x86/interrupts.hh"
34 #include "arch/x86/intmessage.hh"
35 #include "cpu/base.hh"
36 #include "debug/I82094AA.hh"
37 #include "dev/x86/i8259.hh"
38 #include "mem/packet.hh"
39 #include "mem/packet_access.hh"
40 #include "sim/system.hh"
41 
42 namespace gem5
43 {
44 
46  : BasicPioDevice(p, 20), extIntPic(p.external_int_pic),
47  lowestPriorityOffset(0),
48  intRequestPort(name() + ".int_request", this, this, p.int_latency)
49 {
50  // This assumes there's only one I/O APIC in the system and since the apic
51  // id is stored in a 8-bit field with 0xff meaning broadcast, the id must
52  // be less than 0xff
53 
54  assert(p.apic_id < 0xff);
55  initialApicId = id = p.apic_id;
56  arbId = id;
57  regSel = 0;
58  RedirTableEntry entry = 0;
59  entry.mask = 1;
60  for (int i = 0; i < TableSize; i++) {
61  redirTable[i] = entry;
62  pinStates[i] = false;
63  }
64 
65  for (int i = 0; i < p.port_inputs_connection_count; i++)
66  inputs.push_back(new IntSinkPin<I82094AA>(
67  csprintf("%s.inputs[%d]", name(), i), i, this));
68 }
69 
70 void
72 {
73  // The io apic must register its address range with its pio port via
74  // the piodevice init() function.
76 
77  // If the request port isn't connected, we can't send interrupts anywhere.
78  panic_if(!intRequestPort.isConnected(),
79  "Int port not connected to anything!");
80 }
81 
82 Port &
83 X86ISA::I82094AA::getPort(const std::string &if_name, PortID idx)
84 {
85  if (if_name == "int_requestor")
86  return intRequestPort;
87  if (if_name == "inputs")
88  return *inputs.at(idx);
89  else
90  return BasicPioDevice::getPort(if_name, idx);
91 }
92 
93 Tick
95 {
96  assert(pkt->getSize() == 4);
97  Addr offset = pkt->getAddr() - pioAddr;
98  switch(offset) {
99  case 0:
100  pkt->setLE<uint32_t>(regSel);
101  break;
102  case 16:
103  pkt->setLE<uint32_t>(readReg(regSel));
104  break;
105  default:
106  panic("Illegal read from I/O APIC.\n");
107  }
108  pkt->makeAtomicResponse();
109  return pioDelay;
110 }
111 
112 Tick
114 {
115  assert(pkt->getSize() == 4);
116  Addr offset = pkt->getAddr() - pioAddr;
117  switch(offset) {
118  case 0:
119  regSel = pkt->getLE<uint32_t>();
120  break;
121  case 16:
122  writeReg(regSel, pkt->getLE<uint32_t>());
123  break;
124  default:
125  panic("Illegal write to I/O APIC.\n");
126  }
127  pkt->makeAtomicResponse();
128  return pioDelay;
129 }
130 
131 void
132 X86ISA::I82094AA::writeReg(uint8_t offset, uint32_t value)
133 {
134  if (offset == 0x0) {
135  id = bits(value, 31, 24);
136  } else if (offset == 0x1) {
137  // The IOAPICVER register is read only.
138  } else if (offset == 0x2) {
139  arbId = bits(value, 31, 24);
140  } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) {
141  int index = (offset - 0x10) / 2;
142  if (offset % 2) {
143  redirTable[index].topDW = value;
144  redirTable[index].topReserved = 0;
145  } else {
146  redirTable[index].bottomDW = value;
147  redirTable[index].bottomReserved = 0;
148  }
149  } else {
150  warn("Access to undefined I/O APIC register %#x.\n", offset);
151  }
153  "Wrote %#x to I/O APIC register %#x .\n", value, offset);
154 }
155 
156 uint32_t
158 {
159  uint32_t result = 0;
160  if (offset == 0x0) {
161  result = id << 24;
162  } else if (offset == 0x1) {
163  result = ((TableSize - 1) << 16) | APICVersion;
164  } else if (offset == 0x2) {
165  result = arbId << 24;
166  } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) {
167  int index = (offset - 0x10) / 2;
168  if (offset % 2) {
169  result = redirTable[index].topDW;
170  } else {
171  result = redirTable[index].bottomDW;
172  }
173  } else {
174  warn("Access to undefined I/O APIC register %#x.\n", offset);
175  }
177  "Read %#x from I/O APIC register %#x.\n", result, offset);
178  return result;
179 }
180 
181 void
183 {
184  DPRINTF(I82094AA, "Received interrupt %d.\n", line);
185  assert(line < TableSize);
186  RedirTableEntry entry = redirTable[line];
187  if (entry.mask) {
188  DPRINTF(I82094AA, "Entry was masked.\n");
189  return;
190  } else {
191  TriggerIntMessage message = 0;
192  message.destination = entry.dest;
193  if (entry.deliveryMode == delivery_mode::ExtInt) {
194  assert(extIntPic);
195  message.vector = extIntPic->getVector();
196  } else {
197  message.vector = entry.vector;
198  }
199  message.deliveryMode = entry.deliveryMode;
200  message.destMode = entry.destMode;
201  message.level = entry.polarity;
202  message.trigger = entry.trigger;
203  std::list<int> apics;
204  int numContexts = sys->threads.size();
205  if (message.destMode == 0) {
206  if (message.deliveryMode == delivery_mode::LowestPriority) {
207  panic("Lowest priority delivery mode from the "
208  "IO APIC aren't supported in physical "
209  "destination mode.\n");
210  }
211  if (message.destination == 0xFF) {
212  for (int i = 0; i < numContexts; i++) {
213  apics.push_back(i);
214  }
215  } else {
216  apics.push_back(message.destination);
217  }
218  } else {
219  for (int i = 0; i < numContexts; i++) {
220  BaseInterrupts *base_int = sys->threads[i]->
221  getCpuPtr()->getInterruptController(0);
222  auto *localApic = dynamic_cast<Interrupts *>(base_int);
223  if ((localApic->readReg(APIC_LOGICAL_DESTINATION) >> 24) &
224  message.destination) {
225  apics.push_back(localApic->getInitialApicId());
226  }
227  }
228  if (message.deliveryMode == delivery_mode::LowestPriority &&
229  apics.size()) {
230  // The manual seems to suggest that the chipset just does
231  // something reasonable for these instead of actually using
232  // state from the local APIC. We'll just rotate an offset
233  // through the set of APICs selected above.
234  uint64_t modOffset = lowestPriorityOffset % apics.size();
235  lowestPriorityOffset++;
236  auto apicIt = apics.begin();
237  while (modOffset--) {
238  apicIt++;
239  assert(apicIt != apics.end());
240  }
241  int selected = *apicIt;
242  apics.clear();
243  apics.push_back(selected);
244  }
245  }
246  for (auto id: apics) {
247  PacketPtr pkt = buildIntTriggerPacket(id, message);
248  intRequestPort.sendMessage(pkt, sys->isTimingMode());
249  }
250  }
251 }
252 
253 void
255 {
256  assert(number < TableSize);
257  if (!pinStates[number])
258  signalInterrupt(number);
259  pinStates[number] = true;
260 }
261 
262 void
264 {
265  assert(number < TableSize);
266  pinStates[number] = false;
267 }
268 
269 void
271 {
272  uint64_t* redirTableArray = (uint64_t*)redirTable;
273  SERIALIZE_SCALAR(regSel);
274  SERIALIZE_SCALAR(initialApicId);
275  SERIALIZE_SCALAR(id);
276  SERIALIZE_SCALAR(arbId);
277  SERIALIZE_SCALAR(lowestPriorityOffset);
278  SERIALIZE_ARRAY(redirTableArray, TableSize);
279  SERIALIZE_ARRAY(pinStates, TableSize);
280 }
281 
282 void
284 {
285  uint64_t redirTableArray[TableSize];
286  UNSERIALIZE_SCALAR(regSel);
287  UNSERIALIZE_SCALAR(initialApicId);
288  UNSERIALIZE_SCALAR(id);
289  UNSERIALIZE_SCALAR(arbId);
290  UNSERIALIZE_SCALAR(lowestPriorityOffset);
291  UNSERIALIZE_ARRAY(redirTableArray, TableSize);
292  UNSERIALIZE_ARRAY(pinStates, TableSize);
293  for (int i = 0; i < TableSize; i++) {
294  redirTable[i] = (RedirTableEntry)redirTableArray[i];
295  }
296 }
297 
298 } // namespace gem5
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:252
gem5::X86ISA::I82094AA::read
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: i82094aa.cc:94
warn
#define warn(...)
Definition: logging.hh:245
system.hh
gem5::X86ISA::APIC_LOGICAL_DESTINATION
@ APIC_LOGICAL_DESTINATION
Definition: apic.hh:47
UNSERIALIZE_SCALAR
#define UNSERIALIZE_SCALAR(scalar)
Definition: serialize.hh:575
gem5::X86ISA::I82094AA::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: i82094aa.cc:71
gem5::BaseInterrupts
Definition: interrupts.hh:41
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::X86ISA::I82094AA::inputs
std::vector< IntSinkPin< I82094AA > * > inputs
Definition: i82094aa.hh:86
intmessage.hh
gem5::X86ISA::offset
offset
Definition: misc.hh:1030
interrupts.hh
gem5::X86ISA::I82094AA::I82094AA
I82094AA(const Params &p)
Definition: i82094aa.cc:45
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
gem5::Packet::makeAtomicResponse
void makeAtomicResponse()
Definition: packet.hh:1043
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::X86ISA::delivery_mode::LowestPriority
@ LowestPriority
Definition: intmessage.hh:61
packet.hh
gem5::PioDevice::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: io_device.cc:59
gem5::PioDevice::Params
PioDeviceParams Params
Definition: io_device.hh:134
gem5::X86ISA::I82094AA::lowerInterruptPin
void lowerInterruptPin(int number)
Definition: i82094aa.cc:263
gem5::X86ISA::I82094AA::regSel
EndBitUnion(RedirTableEntry) protected uint8_t regSel
Definition: i82094aa.hh:66
gem5::X86ISA::I82094AA::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: i82094aa.cc:283
gem5::X86ISA::I82094AA::pinStates
bool pinStates[TableSize]
Definition: i82094aa.hh:84
gem5::Named::name
virtual std::string name() const
Definition: named.hh:47
i82094aa.hh
gem5::X86ISA::I82094AA::writeReg
void writeReg(uint8_t offset, uint32_t value)
Definition: i82094aa.cc:132
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::X86ISA::I82094AA::initialApicId
uint8_t initialApicId
Definition: i82094aa.hh:72
gem5::X86ISA::I82094AA
Definition: i82094aa.hh:49
gem5::X86ISA::Interrupts
Definition: interrupts.hh:77
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::X86ISA::I82094AA::raiseInterruptPin
void raiseInterruptPin(int number)
Definition: i82094aa.cc:254
SERIALIZE_ARRAY
#define SERIALIZE_ARRAY(member, size)
Definition: serialize.hh:610
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
name
const std::string & name()
Definition: trace.cc:49
SERIALIZE_SCALAR
#define SERIALIZE_SCALAR(scalar)
Definition: serialize.hh:568
packet_access.hh
gem5::X86ISA::I82094AA::arbId
uint8_t arbId
Definition: i82094aa.hh:74
gem5::X86ISA::delivery_mode::ExtInt
@ ExtInt
Definition: intmessage.hh:66
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:203
gem5::X86ISA::buildIntTriggerPacket
static PacketPtr buildIntTriggerPacket(int id, TriggerIntMessage message)
Definition: intmessage.hh:85
gem5::X86ISA::I82094AA::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: i82094aa.cc:270
base.hh
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
UNSERIALIZE_ARRAY
#define UNSERIALIZE_ARRAY(member, size)
Definition: serialize.hh:618
gem5::X86ISA::index
Bitfield< 5, 3 > index
Definition: types.hh:98
gem5::X86ISA::I82094AA::write
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: i82094aa.cc:113
gem5::X86ISA::I82094AA::redirTable
RedirTableEntry redirTable[TableSize]
Definition: i82094aa.hh:83
gem5::X86ISA::I82094AA::id
uint8_t id
Definition: i82094aa.hh:73
gem5::IntSinkPin
Definition: intpin.hh:78
gem5::X86ISA::I82094AA::readReg
uint32_t readReg(uint8_t offset)
Definition: i82094aa.cc:157
i8259.hh
gem5::Packet::getLE
T getLE() const
Get the data in the packet byte swapped from little endian to host endian.
Definition: packet_access.hh:78
gem5::X86ISA::p
Bitfield< 0 > p
Definition: pagetable.hh:151
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::Packet::setLE
void setLE(T v)
Set the value in the data pointer to v as little endian.
Definition: packet_access.hh:108
std::list< int >
gem5::Packet::getAddr
Addr getAddr() const
Definition: packet.hh:781
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::BasicPioDevice
Definition: io_device.hh:147
gem5::X86ISA::I82094AA::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: i82094aa.cc:83
gem5::X86ISA::I82094AA::TableSize
static const uint8_t TableSize
Definition: i82094aa.hh:78
gem5::Packet::getSize
unsigned getSize() const
Definition: packet.hh:791
gem5::X86ISA::I82094AA::signalInterrupt
void signalInterrupt(int line)
Definition: i82094aa.cc:182
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::PioDevice::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: io_device.cc:67

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