gem5  v22.0.0.2
i82094aa.cc
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28 
29 #include "dev/x86/i82094aa.hh"
30 
31 #include <list>
32 
33 #include "arch/x86/interrupts.hh"
34 #include "arch/x86/intmessage.hh"
35 #include "cpu/base.hh"
36 #include "debug/I82094AA.hh"
37 #include "dev/x86/i8259.hh"
38 #include "mem/packet.hh"
39 #include "mem/packet_access.hh"
40 #include "sim/system.hh"
41 
42 namespace gem5
43 {
44 
46  : BasicPioDevice(p, 20), lowestPriorityOffset(0),
47  intRequestPort(name() + ".int_request", this, this, p.int_latency)
48 {
49  // This assumes there's only one I/O APIC in the system and since the apic
50  // id is stored in a 8-bit field with 0xff meaning broadcast, the id must
51  // be less than 0xff
52 
53  assert(p.apic_id < 0xff);
54  initialApicId = id = p.apic_id;
55  arbId = id;
56  regSel = 0;
57  RedirTableEntry entry = 0;
58  entry.mask = 1;
59  for (int i = 0; i < TableSize; i++) {
60  redirTable[i] = entry;
61  pinStates[i] = false;
62  }
63 
64  for (int i = 0; i < p.port_inputs_connection_count; i++)
65  inputs.push_back(new IntSinkPin<I82094AA>(
66  csprintf("%s.inputs[%d]", name(), i), i, this));
67 }
68 
69 void
71 {
72  // The io apic must register its address range with its pio port via
73  // the piodevice init() function.
75 
76  // If the request port isn't connected, we can't send interrupts anywhere.
77  panic_if(!intRequestPort.isConnected(),
78  "Int port not connected to anything!");
79 }
80 
81 Port &
82 X86ISA::I82094AA::getPort(const std::string &if_name, PortID idx)
83 {
84  if (if_name == "int_requestor")
85  return intRequestPort;
86  if (if_name == "inputs")
87  return *inputs.at(idx);
88  else
89  return BasicPioDevice::getPort(if_name, idx);
90 }
91 
92 Tick
94 {
95  assert(pkt->getSize() == 4);
96  Addr offset = pkt->getAddr() - pioAddr;
97  switch(offset) {
98  case 0:
99  pkt->setLE<uint32_t>(regSel);
100  break;
101  case 16:
102  pkt->setLE<uint32_t>(readReg(regSel));
103  break;
104  default:
105  panic("Illegal read from I/O APIC.\n");
106  }
107  pkt->makeAtomicResponse();
108  return pioDelay;
109 }
110 
111 Tick
113 {
114  assert(pkt->getSize() == 4);
115  Addr offset = pkt->getAddr() - pioAddr;
116  switch(offset) {
117  case 0:
118  regSel = pkt->getLE<uint32_t>();
119  break;
120  case 16:
121  writeReg(regSel, pkt->getLE<uint32_t>());
122  break;
123  default:
124  panic("Illegal write to I/O APIC.\n");
125  }
126  pkt->makeAtomicResponse();
127  return pioDelay;
128 }
129 
130 void
131 X86ISA::I82094AA::writeReg(uint8_t offset, uint32_t value)
132 {
133  if (offset == 0x0) {
134  id = bits(value, 31, 24);
135  } else if (offset == 0x1) {
136  // The IOAPICVER register is read only.
137  } else if (offset == 0x2) {
138  arbId = bits(value, 31, 24);
139  } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) {
140  int index = (offset - 0x10) / 2;
141  if (offset % 2) {
142  redirTable[index].topDW = value;
143  redirTable[index].topReserved = 0;
144  } else {
145  redirTable[index].bottomDW = value;
146  redirTable[index].bottomReserved = 0;
147  }
148  } else {
149  warn("Access to undefined I/O APIC register %#x.\n", offset);
150  }
152  "Wrote %#x to I/O APIC register %#x .\n", value, offset);
153 }
154 
155 uint32_t
157 {
158  uint32_t result = 0;
159  if (offset == 0x0) {
160  result = id << 24;
161  } else if (offset == 0x1) {
162  result = ((TableSize - 1) << 16) | APICVersion;
163  } else if (offset == 0x2) {
164  result = arbId << 24;
165  } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) {
166  int index = (offset - 0x10) / 2;
167  if (offset % 2) {
168  result = redirTable[index].topDW;
169  } else {
170  result = redirTable[index].bottomDW;
171  }
172  } else {
173  warn("Access to undefined I/O APIC register %#x.\n", offset);
174  }
176  "Read %#x from I/O APIC register %#x.\n", result, offset);
177  return result;
178 }
179 
180 void
182 {
183  DPRINTF(I82094AA, "Received interrupt %d.\n", line);
184  assert(line < TableSize);
185  RedirTableEntry entry = redirTable[line];
186  if (entry.mask) {
187  DPRINTF(I82094AA, "Entry was masked.\n");
188  return;
189  }
190 
191  TriggerIntMessage message = 0;
192 
193  message.destination = entry.dest;
194  message.deliveryMode = entry.deliveryMode;
195  message.destMode = entry.destMode;
196  message.level = entry.polarity;
197  message.trigger = entry.trigger;
198 
199  if (entry.deliveryMode == delivery_mode::ExtInt) {
200  // We need to ask the I8259 for the vector.
202  auto on_completion = [this, message](PacketPtr pkt) {
203  auto msg_copy = message;
204  msg_copy.vector = pkt->getLE<uint8_t>();
205  signalInterrupt(msg_copy);
206  delete pkt;
207  };
208  intRequestPort.sendMessage(pkt, sys->isTimingMode(),
209  on_completion);
210  } else {
211  message.vector = entry.vector;
212  signalInterrupt(message);
213  }
214 }
215 
216 void
217 X86ISA::I82094AA::signalInterrupt(TriggerIntMessage message)
218 {
219  std::list<int> apics;
220  int numContexts = sys->threads.size();
221  if (message.destMode == 0) {
222  if (message.deliveryMode == delivery_mode::LowestPriority) {
223  panic("Lowest priority delivery mode from the "
224  "IO APIC aren't supported in physical "
225  "destination mode.\n");
226  }
227  if (message.destination == 0xFF) {
228  for (int i = 0; i < numContexts; i++) {
229  apics.push_back(i);
230  }
231  } else {
232  apics.push_back(message.destination);
233  }
234  } else {
235  for (int i = 0; i < numContexts; i++) {
236  BaseInterrupts *base_int = sys->threads[i]->
237  getCpuPtr()->getInterruptController(0);
238  auto *localApic = dynamic_cast<Interrupts *>(base_int);
239  if ((localApic->readReg(APIC_LOGICAL_DESTINATION) >> 24) &
240  message.destination) {
241  apics.push_back(localApic->getInitialApicId());
242  }
243  }
244  if (message.deliveryMode == delivery_mode::LowestPriority &&
245  apics.size()) {
246  // The manual seems to suggest that the chipset just does
247  // something reasonable for these instead of actually using
248  // state from the local APIC. We'll just rotate an offset
249  // through the set of APICs selected above.
250  uint64_t modOffset = lowestPriorityOffset % apics.size();
251  lowestPriorityOffset++;
252  auto apicIt = apics.begin();
253  while (modOffset--) {
254  apicIt++;
255  assert(apicIt != apics.end());
256  }
257  int selected = *apicIt;
258  apics.clear();
259  apics.push_back(selected);
260  }
261  }
262  for (auto id: apics) {
263  PacketPtr pkt = buildIntTriggerPacket(id, message);
264  intRequestPort.sendMessage(pkt, sys->isTimingMode());
265  }
266 }
267 
268 void
270 {
271  assert(number < TableSize);
272  if (!pinStates[number])
273  requestInterrupt(number);
274  pinStates[number] = true;
275 }
276 
277 void
279 {
280  assert(number < TableSize);
281  pinStates[number] = false;
282 }
283 
284 void
286 {
287  uint64_t* redirTableArray = (uint64_t*)redirTable;
288  SERIALIZE_SCALAR(regSel);
289  SERIALIZE_SCALAR(initialApicId);
290  SERIALIZE_SCALAR(id);
291  SERIALIZE_SCALAR(arbId);
292  SERIALIZE_SCALAR(lowestPriorityOffset);
293  SERIALIZE_ARRAY(redirTableArray, TableSize);
294  SERIALIZE_ARRAY(pinStates, TableSize);
295 }
296 
297 void
299 {
300  uint64_t redirTableArray[TableSize];
301  UNSERIALIZE_SCALAR(regSel);
302  UNSERIALIZE_SCALAR(initialApicId);
303  UNSERIALIZE_SCALAR(id);
304  UNSERIALIZE_SCALAR(arbId);
305  UNSERIALIZE_SCALAR(lowestPriorityOffset);
306  UNSERIALIZE_ARRAY(redirTableArray, TableSize);
307  UNSERIALIZE_ARRAY(pinStates, TableSize);
308  for (int i = 0; i < TableSize; i++) {
309  redirTable[i] = (RedirTableEntry)redirTableArray[i];
310  }
311 }
312 
313 } // namespace gem5
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:245
gem5::X86ISA::I82094AA::read
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: i82094aa.cc:93
warn
#define warn(...)
Definition: logging.hh:246
system.hh
gem5::X86ISA::APIC_LOGICAL_DESTINATION
@ APIC_LOGICAL_DESTINATION
Definition: apic.hh:47
UNSERIALIZE_SCALAR
#define UNSERIALIZE_SCALAR(scalar)
Definition: serialize.hh:575
gem5::X86ISA::I82094AA::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: i82094aa.cc:70
gem5::BaseInterrupts
Definition: interrupts.hh:41
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::X86ISA::I82094AA::inputs
std::vector< IntSinkPin< I82094AA > * > inputs
Definition: i82094aa.hh:84
intmessage.hh
gem5::X86ISA::offset
offset
Definition: misc.hh:1024
interrupts.hh
gem5::X86ISA::I82094AA::I82094AA
I82094AA(const Params &p)
Definition: i82094aa.cc:45
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
gem5::Packet::makeAtomicResponse
void makeAtomicResponse()
Definition: packet.hh:1056
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::X86ISA::delivery_mode::LowestPriority
@ LowestPriority
Definition: intmessage.hh:61
packet.hh
gem5::PioDevice::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: io_device.cc:59
gem5::PioDevice::Params
PioDeviceParams Params
Definition: io_device.hh:134
gem5::X86ISA::I82094AA::lowerInterruptPin
void lowerInterruptPin(int number)
Definition: i82094aa.cc:278
gem5::X86ISA::I82094AA::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: i82094aa.cc:298
gem5::X86ISA::I82094AA::pinStates
bool pinStates[TableSize]
Definition: i82094aa.hh:82
gem5::Named::name
virtual std::string name() const
Definition: named.hh:47
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
i82094aa.hh
gem5::X86ISA::I82094AA::writeReg
void writeReg(uint8_t offset, uint32_t value)
Definition: i82094aa.cc:131
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:291
gem5::X86ISA::I82094AA::requestInterrupt
void requestInterrupt(int line)
Definition: i82094aa.cc:181
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::X86ISA::I82094AA
Definition: i82094aa.hh:49
gem5::X86ISA::Interrupts
Definition: interrupts.hh:78
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::X86ISA::I82094AA::raiseInterruptPin
void raiseInterruptPin(int number)
Definition: i82094aa.cc:269
gem5::X86ISA::I82094AA::initialApicId
EndBitUnion(RedirTableEntry) protected uint8_t initialApicId
Definition: i82094aa.hh:66
SERIALIZE_ARRAY
#define SERIALIZE_ARRAY(member, size)
Definition: serialize.hh:610
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
name
const std::string & name()
Definition: trace.cc:49
SERIALIZE_SCALAR
#define SERIALIZE_SCALAR(scalar)
Definition: serialize.hh:568
packet_access.hh
gem5::X86ISA::I82094AA::arbId
uint8_t arbId
Definition: i82094aa.hh:72
gem5::X86ISA::delivery_mode::ExtInt
@ ExtInt
Definition: intmessage.hh:66
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:204
gem5::X86ISA::buildIntTriggerPacket
static PacketPtr buildIntTriggerPacket(int id, TriggerIntMessage message)
Definition: intmessage.hh:85
gem5::X86ISA::I82094AA::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: i82094aa.cc:285
base.hh
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
UNSERIALIZE_ARRAY
#define UNSERIALIZE_ARRAY(member, size)
Definition: serialize.hh:618
gem5::X86ISA::index
Bitfield< 5, 3 > index
Definition: types.hh:98
gem5::X86ISA::I82094AA::write
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: i82094aa.cc:112
gem5::X86ISA::I82094AA::redirTable
RedirTableEntry redirTable[TableSize]
Definition: i82094aa.hh:81
gem5::X86ISA::I82094AA::id
uint8_t id
Definition: i82094aa.hh:71
gem5::IntSinkPin
Definition: intpin.hh:78
gem5::X86ISA::I82094AA::readReg
uint32_t readReg(uint8_t offset)
Definition: i82094aa.cc:156
i8259.hh
gem5::X86ISA::buildIntAcknowledgePacket
static PacketPtr buildIntAcknowledgePacket()
Definition: intmessage.hh:92
gem5::Packet::getLE
T getLE() const
Get the data in the packet byte swapped from little endian to host endian.
Definition: packet_access.hh:78
gem5::X86ISA::p
Bitfield< 0 > p
Definition: pagetable.hh:151
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::X86ISA::I82094AA::signalInterrupt
void signalInterrupt(TriggerIntMessage message)
Definition: i82094aa.cc:217
gem5::Packet::setLE
void setLE(T v)
Set the value in the data pointer to v as little endian.
Definition: packet_access.hh:108
std::list< int >
gem5::Packet::getAddr
Addr getAddr() const
Definition: packet.hh:790
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::BasicPioDevice
Definition: io_device.hh:147
gem5::X86ISA::I82094AA::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: i82094aa.cc:82
gem5::X86ISA::I82094AA::TableSize
static const uint8_t TableSize
Definition: i82094aa.hh:76
gem5::Packet::getSize
unsigned getSize() const
Definition: packet.hh:800
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::PioDevice::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: io_device.cc:67

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