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pl111.hh
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1/*
2 * Copyright (c) 2010-2012, 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38
43#ifndef __DEV_ARM_PL111_HH__
44#define __DEV_ARM_PL111_HH__
45
46#include <fstream>
47#include <memory>
48
49#include "base/bmpwriter.hh"
50#include "base/framebuffer.hh"
51#include "base/output.hh"
53#include "params/Pl111.hh"
54#include "sim/serialize.hh"
55
56namespace gem5
57{
58
59class VncInput;
60
61class Pl111: public AmbaDmaDevice
62{
63 protected:
64 static const uint64_t AMBA_ID = 0xb105f00d00141111ULL;
66 static const int LcdTiming0 = 0x000;
67 static const int LcdTiming1 = 0x004;
68 static const int LcdTiming2 = 0x008;
69 static const int LcdTiming3 = 0x00C;
70 static const int LcdUpBase = 0x010;
71 static const int LcdLpBase = 0x014;
72 static const int LcdControl = 0x018;
73 static const int LcdImsc = 0x01C;
74 static const int LcdRis = 0x020;
75 static const int LcdMis = 0x024;
76 static const int LcdIcr = 0x028;
77 static const int LcdUpCurr = 0x02C;
78 static const int LcdLpCurr = 0x030;
79 static const int LcdPalette = 0x200;
80 static const int CrsrImage = 0x800;
81 static const int ClcdCrsrCtrl = 0xC00;
82 static const int ClcdCrsrConfig = 0xC04;
83 static const int ClcdCrsrPalette0 = 0xC08;
84 static const int ClcdCrsrPalette1 = 0xC0C;
85 static const int ClcdCrsrXY = 0xC10;
86 static const int ClcdCrsrClip = 0xC14;
87 static const int ClcdCrsrImsc = 0xC20;
88 static const int ClcdCrsrIcr = 0xC24;
89 static const int ClcdCrsrRis = 0xC28;
90 static const int ClcdCrsrMis = 0xC2C;
91
92 static const int LcdPaletteSize = 128;
93 static const int CrsrImageSize = 256;
94
95 static const int LcdMaxWidth = 1024; // pixels per line
96 static const int LcdMaxHeight = 768; // lines per panel
97
98 static const int dmaSize = 8; // 64 bits
99 static const int maxOutstandingDma = 16; // 16 deep FIFO of 64 bits
100
101 static const int buffer_size = LcdMaxWidth * LcdMaxHeight * sizeof(uint32_t);
102
114
115 BitUnion8(InterruptReg)
116 Bitfield<1> underflow;
117 Bitfield<2> baseaddr;
118 Bitfield<3> vcomp;
119 Bitfield<4> ahbmaster;
120 EndBitUnion(InterruptReg)
121
122 BitUnion32(TimingReg0)
123 Bitfield<7,2> ppl;
124 Bitfield<15,8> hsw;
125 Bitfield<23,16> hfp;
126 Bitfield<31,24> hbp;
127 EndBitUnion(TimingReg0)
128
129 BitUnion32(TimingReg1)
130 Bitfield<9,0> lpp;
131 Bitfield<15,10> vsw;
132 Bitfield<23,16> vfp;
133 Bitfield<31,24> vbp;
134 EndBitUnion(TimingReg1)
135
136 BitUnion32(TimingReg2)
137 Bitfield<4,0> pcdlo;
138 Bitfield<5> clksel;
139 Bitfield<10,6> acb;
140 Bitfield<11> avs;
141 Bitfield<12> ihs;
142 Bitfield<13> ipc;
143 Bitfield<14> ioe;
144 Bitfield<25,16> cpl;
145 Bitfield<26> bcd;
146 Bitfield<31,27> pcdhi;
147 EndBitUnion(TimingReg2)
148
149 BitUnion32(TimingReg3)
150 Bitfield<6,0> led;
151 Bitfield<16> lee;
152 EndBitUnion(TimingReg3)
153
154 BitUnion32(ControlReg)
155 Bitfield<0> lcden;
156 Bitfield<3,1> lcdbpp;
157 Bitfield<4> lcdbw;
158 Bitfield<5> lcdtft;
159 Bitfield<6> lcdmono8;
160 Bitfield<7> lcddual;
161 Bitfield<8> bgr;
162 Bitfield<9> bebo;
163 Bitfield<10> bepo;
164 Bitfield<11> lcdpwr;
165 Bitfield<13,12> lcdvcomp;
166 Bitfield<16> watermark;
167 EndBitUnion(ControlReg)
168
175 class DmaDoneEvent : public Event
176 {
177 private:
178 Pl111 &obj;
179
180 public:
181 DmaDoneEvent(Pl111 *_obj)
182 : Event(), obj(*_obj) {}
183
184 void process() {
185 obj.dmaDoneEventFree.push_back(this);
186 obj.dmaDone();
187 }
188
189 const std::string name() const {
190 return obj.name() + ".DmaDoneEvent";
191 }
192 };
193
195 TimingReg0 lcdTiming0;
196
198 TimingReg1 lcdTiming1;
199
201 TimingReg2 lcdTiming2;
202
204 TimingReg3 lcdTiming3;
205
207 uint32_t lcdUpbase;
208
210 uint32_t lcdLpbase;
211
213 ControlReg lcdControl;
214
216 InterruptReg lcdImsc;
217
219 InterruptReg lcdRis;
220
222 InterruptReg lcdMis;
223
227
231
233 uint32_t clcdCrsrCtrl;
234
237
241
243 uint32_t clcdCrsrXY;
244
246 uint32_t clcdCrsrClip;
247
249 InterruptReg clcdCrsrImsc;
250
252 InterruptReg clcdCrsrIcr;
253
255 InterruptReg clcdCrsrRis;
256
258 InterruptReg clcdCrsrMis;
259
262
265
268
271
274
276 uint16_t width;
277
279 uint16_t height;
280
283
285 uint8_t *dmaBuffer;
286
289
292
295
298
300 uint32_t waterMark;
301
304
306
308 void updateVideoParams();
309
311 void readFramebuffer();
312
315
317 void generateInterrupt();
318
320 void fillFifo();
321
323 void startDma();
324
326 void dmaDone();
327
330
333
352
359
361
362 public:
363 using Params = Pl111Params;
364 Pl111(const Params &p);
365 ~Pl111();
366
367 Tick read(PacketPtr pkt) override;
368 Tick write(PacketPtr pkt) override;
369
370 void serialize(CheckpointOut &cp) const override;
371 void unserialize(CheckpointIn &cp) override;
372
378 AddrRangeList getAddrRanges() const override;
379};
380
381} // namespace gem5
382
383#endif
This is a base class for AMBA devices that have to respond to Device and Implementer ID calls.
#define BitUnion32(name)
Definition bitunion.hh:495
Internal gem5 representation of a frame buffer.
virtual std::string name() const
Definition named.hh:47
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition packet.hh:295
Configurable RGB pixel converter.
Definition pixel.hh:92
void dmaDone()
DMA done event.
Definition pl111.cc:473
Bitfield< 13, 12 > lcdvcomp
Definition pl111.hh:165
Bitfield< 3 > vcomp
Definition pl111.hh:118
Bitfield< 4 > lcdbw
Definition pl111.hh:157
static const int LcdLpCurr
Definition pl111.hh:78
static const int ClcdCrsrCtrl
Definition pl111.hh:81
Addr curAddr
Frame buffer current address.
Definition pl111.hh:297
Bitfield< 31, 24 > vbp
Definition pl111.hh:133
Bitfield< 3, 1 > lcdbpp
Definition pl111.hh:156
EventFunctionWrapper readEvent
DMA framebuffer read event.
Definition pl111.hh:329
static const int ClcdCrsrXY
Definition pl111.hh:85
uint32_t clcdCrsrClip
Cursor clip position register.
Definition pl111.hh:246
Bitfield< 31, 27 > pcdhi
Definition pl111.hh:146
Bitfield< 5 > lcdtft
Definition pl111.hh:158
Bitfield< 7 > lcddual
Definition pl111.hh:160
Addr startAddr
Frame buffer base address.
Definition pl111.hh:291
ControlReg lcdControl
Control register.
Definition pl111.hh:213
static const int LcdMaxWidth
Definition pl111.hh:95
Bitfield< 10 > bepo
Definition pl111.hh:163
Bitfield< 4 > ahbmaster
Definition pl111.hh:119
Bitfield< 2 > baseaddr
Definition pl111.hh:117
Bitfield< 8 > bgr
Definition pl111.hh:161
uint32_t clcdCrsrXY
Cursor XY position register.
Definition pl111.hh:243
static const int LcdTiming3
Definition pl111.hh:69
Bitfield< 6 > lcdmono8
Definition pl111.hh:159
uint32_t clcdCrsrPalette1
Definition pl111.hh:240
AddrRangeList getAddrRanges() const override
Determine the address ranges that this device responds to.
Definition pl111.cc:740
Pl111(const Params &p)
Definition pl111.cc:59
InterruptReg clcdCrsrMis
Cursor masked interrupt status register - const.
Definition pl111.hh:258
uint32_t clcdCrsrPalette0
Cursor palette registers.
Definition pl111.hh:239
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition pl111.cc:524
EndBitUnion(InterruptReg) BitUnion32(TimingReg0) Bitfield< 7
FrameBuffer fb
Definition pl111.hh:264
static const int LcdControl
Definition pl111.hh:72
Bitfield< 31, 24 > hbp
Definition pl111.hh:126
TimingReg2 lcdTiming2
Clock and signal polarity control register.
Definition pl111.hh:201
TimingReg1 lcdTiming1
Vertical axis panel control register.
Definition pl111.hh:198
Addr maxAddr
Frame buffer max address.
Definition pl111.hh:294
static const int LcdRis
Definition pl111.hh:74
static const int LcdLpBase
Definition pl111.hh:71
static const int LcdMaxHeight
Definition pl111.hh:96
bool enableCapture
Definition pl111.hh:360
Pl111Params Params
Definition pl111.hh:363
static const int LcdPaletteSize
Definition pl111.hh:92
Bitfield< 23, 16 > hfp
Definition pl111.hh:125
uint8_t * dmaBuffer
CLCDC supports up to 1024x768.
Definition pl111.hh:285
static const int ClcdCrsrConfig
Definition pl111.hh:82
InterruptReg clcdCrsrRis
Cursor raw interrupt status register - const.
Definition pl111.hh:255
Bitfield< 23, 16 > vfp
Definition pl111.hh:132
Tick startTime
Start time for frame buffer dma read.
Definition pl111.hh:288
uint32_t lcdUpbase
Upper panel frame base address register.
Definition pl111.hh:207
PixelConverter converter
Definition pl111.hh:263
static const int maxOutstandingDma
Definition pl111.hh:99
InterruptReg lcdImsc
Interrupt mask set/clear register.
Definition pl111.hh:216
Bitfield< 13 > ipc
Definition pl111.hh:142
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition pl111.cc:214
Bitfield< 9 > bebo
Definition pl111.hh:162
uint16_t width
Frame buffer width - pixels per line.
Definition pl111.hh:276
static const int ClcdCrsrMis
Definition pl111.hh:90
uint8_t bytesPerPixel
Bytes per pixel.
Definition pl111.hh:282
std::vector< DmaDoneEvent > dmaDoneEventAll
All pre-allocated DMA done events.
Definition pl111.hh:351
static const int LcdImsc
Definition pl111.hh:73
static const int LcdUpBase
Definition pl111.hh:70
void generateReadEvent()
Generate dma framebuffer read event.
static const int LcdMis
Definition pl111.hh:75
Bitfield< 16 > lee
Definition pl111.hh:151
static const int LcdTiming2
Definition pl111.hh:68
uint16_t height
Frame buffer height - lines per panel.
Definition pl111.hh:279
Bitfield< 11 > lcdpwr
Definition pl111.hh:164
static const int dmaSize
Definition pl111.hh:98
EventFunctionWrapper fillFifoEvent
Fill fifo.
Definition pl111.hh:332
TimingReg3 lcdTiming3
Line end control register.
Definition pl111.hh:204
Bitfield< 5 > clksel
Definition pl111.hh:138
Bitfield< 25, 16 > cpl
Definition pl111.hh:144
std::vector< DmaDoneEvent * > dmaDoneEventFree
Unused DMA done events that are ready to be scheduled.
Definition pl111.hh:354
uint32_t cursorImage[CrsrImageSize]
Cursor image RAM register 256-word wide values defining images overlaid by the hw cursor mechanism.
Definition pl111.hh:230
uint32_t clcdCrsrCtrl
Cursor control register.
Definition pl111.hh:233
InterruptReg clcdCrsrImsc
Cursor interrupt mask set/clear register.
Definition pl111.hh:249
Bitfield< 15, 8 > hsw
Definition pl111.hh:124
InterruptReg lcdMis
Masked interrupt status register.
Definition pl111.hh:222
InterruptReg clcdCrsrIcr
Cursor interrupt clear register.
Definition pl111.hh:252
uint32_t lcdPalette[LcdPaletteSize]
256x16-bit color palette registers 256 palette entries organized as 128 locations of two entries per ...
Definition pl111.hh:226
static const int LcdUpCurr
Definition pl111.hh:77
uint32_t lcdLpbase
Lower panel frame base address register.
Definition pl111.hh:210
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition pl111.cc:99
static const int ClcdCrsrRis
Definition pl111.hh:89
static const int CrsrImage
Definition pl111.hh:80
void readFramebuffer()
DMA framebuffer read.
Definition pl111.cc:426
Tick pixelClock
Pixel clock.
Definition pl111.hh:261
static const int ClcdCrsrPalette1
Definition pl111.hh:84
uint32_t clcdCrsrConfig
Cursor configuration register.
Definition pl111.hh:236
static const int LcdTiming0
ARM PL111 register map.
Definition pl111.hh:66
Bitfield< 14 > ioe
Definition pl111.hh:143
VncInput * vnc
VNC server.
Definition pl111.hh:267
Bitfield< 12 > ihs
Definition pl111.hh:141
static const int LcdTiming1
Definition pl111.hh:67
PixelConverter pixelConverter() const
Definition pl111.cc:356
EventFunctionWrapper intEvent
Wrapper to create an event out of the interrupt.
Definition pl111.hh:358
static const int CrsrImageSize
Definition pl111.hh:93
Bitfield< 10, 6 > acb
Definition pl111.hh:139
uint32_t waterMark
DMA FIFO watermark.
Definition pl111.hh:300
static const int LcdPalette
Definition pl111.hh:79
static const int buffer_size
Definition pl111.hh:101
uint32_t dmaPendingNum
Number of pending dma reads.
Definition pl111.hh:303
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition pl111.cc:614
void generateInterrupt()
Function to generate interrupt.
Definition pl111.cc:727
void startDma()
start the dmas off after power is enabled
Definition pl111.cc:418
Bitfield< 16 > watermark
Definition pl111.hh:166
static const int ClcdCrsrIcr
Definition pl111.hh:88
BmpWriter bmp
Helper to write out bitmaps.
Definition pl111.hh:270
void fillFifo()
fillFIFO event
Definition pl111.cc:449
static const int ClcdCrsrImsc
Definition pl111.hh:87
EndBitUnion(ControlReg) class DmaDoneEvent TimingReg0 lcdTiming0
Event wrapper for dmaDone()
Definition pl111.hh:167
OutputStream * pic
Picture of what the current frame buffer looks like.
Definition pl111.hh:273
InterruptReg lcdRis
Raw interrupt status register - const.
Definition pl111.hh:219
Bitfield< 15, 10 > vsw
Definition pl111.hh:131
static const int LcdIcr
Definition pl111.hh:76
Bitfield< 26 > bcd
Definition pl111.hh:145
static const uint64_t AMBA_ID
Definition pl111.hh:64
static const int ClcdCrsrPalette0
Definition pl111.hh:83
static const int ClcdCrsrClip
Definition pl111.hh:86
Bitfield< 11 > avs
Definition pl111.hh:140
void updateVideoParams()
Send updated parameters to the vnc server.
Definition pl111.cc:398
BitUnion8(InterruptReg) Bitfield< 1 > underflow
STL vector class.
Definition stl.hh:37
#define EndBitUnion(name)
This closes off the class and union started by the above macro.
Definition bitunion.hh:428
Bitfield< 0 > p
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
std::ostream CheckpointOut
Definition serialize.hh:66
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147
uint64_t Tick
Tick count type.
Definition types.hh:58
const std::string & name()
Definition trace.cc:48

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