gem5  v21.1.0.2
pl111.hh
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37 
38 
43 #ifndef __DEV_ARM_PL111_HH__
44 #define __DEV_ARM_PL111_HH__
45 
46 #include <fstream>
47 #include <memory>
48 
49 #include "base/bmpwriter.hh"
50 #include "base/framebuffer.hh"
51 #include "base/output.hh"
52 #include "dev/arm/amba_device.hh"
53 #include "params/Pl111.hh"
54 #include "sim/serialize.hh"
55 
56 namespace gem5
57 {
58 
59 class VncInput;
60 
61 class Pl111: public AmbaDmaDevice
62 {
63  protected:
64  static const uint64_t AMBA_ID = 0xb105f00d00141111ULL;
66  static const int LcdTiming0 = 0x000;
67  static const int LcdTiming1 = 0x004;
68  static const int LcdTiming2 = 0x008;
69  static const int LcdTiming3 = 0x00C;
70  static const int LcdUpBase = 0x010;
71  static const int LcdLpBase = 0x014;
72  static const int LcdControl = 0x018;
73  static const int LcdImsc = 0x01C;
74  static const int LcdRis = 0x020;
75  static const int LcdMis = 0x024;
76  static const int LcdIcr = 0x028;
77  static const int LcdUpCurr = 0x02C;
78  static const int LcdLpCurr = 0x030;
79  static const int LcdPalette = 0x200;
80  static const int CrsrImage = 0x800;
81  static const int ClcdCrsrCtrl = 0xC00;
82  static const int ClcdCrsrConfig = 0xC04;
83  static const int ClcdCrsrPalette0 = 0xC08;
84  static const int ClcdCrsrPalette1 = 0xC0C;
85  static const int ClcdCrsrXY = 0xC10;
86  static const int ClcdCrsrClip = 0xC14;
87  static const int ClcdCrsrImsc = 0xC20;
88  static const int ClcdCrsrIcr = 0xC24;
89  static const int ClcdCrsrRis = 0xC28;
90  static const int ClcdCrsrMis = 0xC2C;
91 
92  static const int LcdPaletteSize = 128;
93  static const int CrsrImageSize = 256;
94 
95  static const int LcdMaxWidth = 1024; // pixels per line
96  static const int LcdMaxHeight = 768; // lines per panel
97 
98  static const int dmaSize = 8; // 64 bits
99  static const int maxOutstandingDma = 16; // 16 deep FIFO of 64 bits
100 
101  static const int buffer_size = LcdMaxWidth * LcdMaxHeight * sizeof(uint32_t);
102 
103  enum LcdMode
104  {
105  bpp1 = 0,
113  };
114 
115  BitUnion8(InterruptReg)
116  Bitfield<1> underflow;
117  Bitfield<2> baseaddr;
118  Bitfield<3> vcomp;
119  Bitfield<4> ahbmaster;
120  EndBitUnion(InterruptReg)
121 
122  BitUnion32(TimingReg0)
123  Bitfield<7,2> ppl;
124  Bitfield<15,8> hsw;
125  Bitfield<23,16> hfp;
126  Bitfield<31,24> hbp;
127  EndBitUnion(TimingReg0)
128 
129  BitUnion32(TimingReg1)
130  Bitfield<9,0> lpp;
131  Bitfield<15,10> vsw;
132  Bitfield<23,16> vfp;
133  Bitfield<31,24> vbp;
134  EndBitUnion(TimingReg1)
135 
136  BitUnion32(TimingReg2)
137  Bitfield<4,0> pcdlo;
138  Bitfield<5> clksel;
139  Bitfield<10,6> acb;
140  Bitfield<11> avs;
141  Bitfield<12> ihs;
142  Bitfield<13> ipc;
143  Bitfield<14> ioe;
144  Bitfield<25,16> cpl;
145  Bitfield<26> bcd;
146  Bitfield<31,27> pcdhi;
147  EndBitUnion(TimingReg2)
148 
149  BitUnion32(TimingReg3)
150  Bitfield<6,0> led;
151  Bitfield<16> lee;
152  EndBitUnion(TimingReg3)
153 
154  BitUnion32(ControlReg)
155  Bitfield<0> lcden;
156  Bitfield<3,1> lcdbpp;
157  Bitfield<4> lcdbw;
158  Bitfield<5> lcdtft;
159  Bitfield<6> lcdmono8;
160  Bitfield<7> lcddual;
161  Bitfield<8> bgr;
162  Bitfield<9> bebo;
163  Bitfield<10> bepo;
164  Bitfield<11> lcdpwr;
165  Bitfield<13,12> lcdvcomp;
166  Bitfield<16> watermark;
167  EndBitUnion(ControlReg)
168 
175  class DmaDoneEvent : public Event
176  {
177  private:
178  Pl111 &obj;
179 
180  public:
181  DmaDoneEvent(Pl111 *_obj)
182  : Event(), obj(*_obj) {}
183 
184  void process() {
185  obj.dmaDoneEventFree.push_back(this);
186  obj.dmaDone();
187  }
188 
189  const std::string name() const {
190  return obj.name() + ".DmaDoneEvent";
191  }
192  };
193 
195  TimingReg0 lcdTiming0;
196 
198  TimingReg1 lcdTiming1;
199 
201  TimingReg2 lcdTiming2;
202 
204  TimingReg3 lcdTiming3;
205 
207  uint32_t lcdUpbase;
208 
210  uint32_t lcdLpbase;
211 
213  ControlReg lcdControl;
214 
216  InterruptReg lcdImsc;
217 
219  InterruptReg lcdRis;
220 
222  InterruptReg lcdMis;
223 
227 
231 
233  uint32_t clcdCrsrCtrl;
234 
236  uint32_t clcdCrsrConfig;
237 
241 
243  uint32_t clcdCrsrXY;
244 
246  uint32_t clcdCrsrClip;
247 
249  InterruptReg clcdCrsrImsc;
250 
252  InterruptReg clcdCrsrIcr;
253 
255  InterruptReg clcdCrsrRis;
256 
258  InterruptReg clcdCrsrMis;
259 
262 
265 
268 
271 
274 
276  uint16_t width;
277 
279  uint16_t height;
280 
282  uint8_t bytesPerPixel;
283 
285  uint8_t *dmaBuffer;
286 
289 
292 
295 
298 
300  uint32_t waterMark;
301 
303  uint32_t dmaPendingNum;
304 
306 
308  void updateVideoParams();
309 
311  void readFramebuffer();
312 
314  void generateReadEvent();
315 
317  void generateInterrupt();
318 
320  void fillFifo();
321 
323  void startDma();
324 
326  void dmaDone();
327 
330 
333 
352 
359 
361 
362  public:
363  using Params = Pl111Params;
364  Pl111(const Params &p);
365  ~Pl111();
366 
367  Tick read(PacketPtr pkt) override;
368  Tick write(PacketPtr pkt) override;
369 
370  void serialize(CheckpointOut &cp) const override;
371  void unserialize(CheckpointIn &cp) override;
372 
378  AddrRangeList getAddrRanges() const override;
379 };
380 
381 } // namespace gem5
382 
383 #endif
gem5::Pl111::fillFifo
void fillFifo()
fillFIFO event
Definition: pl111.cc:449
gem5::Pl111::lpp
lpp
Definition: pl111.hh:130
gem5::Pl111::LcdMis
static const int LcdMis
Definition: pl111.hh:75
gem5::Pl111::lcdTiming2
TimingReg2 lcdTiming2
Clock and signal polarity control register.
Definition: pl111.hh:201
gem5::Pl111::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: pl111.cc:614
gem5::Pl111::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: pl111.cc:524
gem5::Pl111::write
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: pl111.cc:214
gem5::Pl111::ClcdCrsrMis
static const int ClcdCrsrMis
Definition: pl111.hh:90
gem5::Pl111::vnc
VncInput * vnc
VNC server.
Definition: pl111.hh:267
gem5::Pl111::bytesPerPixel
uint8_t bytesPerPixel
Bytes per pixel.
Definition: pl111.hh:282
gem5::Pl111::generateReadEvent
void generateReadEvent()
Generate dma framebuffer read event.
gem5::Pl111::ClcdCrsrConfig
static const int ClcdCrsrConfig
Definition: pl111.hh:82
gem5::Pl111::vfp
Bitfield< 23, 16 > vfp
Definition: pl111.hh:132
gem5::FrameBuffer
Internal gem5 representation of a frame buffer.
Definition: framebuffer.hh:68
gem5::Pl111::bpp4
@ bpp4
Definition: pl111.hh:107
serialize.hh
gem5::Pl111::clcdCrsrClip
uint32_t clcdCrsrClip
Cursor clip position register.
Definition: pl111.hh:246
gem5::Pl111::maxOutstandingDma
static const int maxOutstandingDma
Definition: pl111.hh:99
gem5::Pl111::ahbmaster
Bitfield< 4 > ahbmaster
Definition: pl111.hh:119
gem5::Pl111::fillFifoEvent
EventFunctionWrapper fillFifoEvent
Fill fifo.
Definition: pl111.hh:332
gem5::Pl111::bmp
BmpWriter bmp
Helper to write out bitmaps.
Definition: pl111.hh:270
gem5::Pl111::bebo
Bitfield< 9 > bebo
Definition: pl111.hh:162
gem5::Pl111::clcdCrsrPalette0
uint32_t clcdCrsrPalette0
Cursor palette registers.
Definition: pl111.hh:239
gem5::Pl111::LcdMode
LcdMode
Definition: pl111.hh:103
gem5::Pl111::LcdImsc
static const int LcdImsc
Definition: pl111.hh:73
gem5::Pl111::lcdbw
Bitfield< 4 > lcdbw
Definition: pl111.hh:157
gem5::Pl111::getAddrRanges
AddrRangeList getAddrRanges() const override
Determine the address ranges that this device responds to.
Definition: pl111.cc:740
gem5::Pl111::lcddual
Bitfield< 7 > lcddual
Definition: pl111.hh:160
gem5::Pl111::curAddr
Addr curAddr
Frame buffer current address.
Definition: pl111.hh:297
gem5::Pl111::bpp16m565
@ bpp16m565
Definition: pl111.hh:111
amba_device.hh
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::Pl111::lcdPalette
uint32_t lcdPalette[LcdPaletteSize]
256x16-bit color palette registers 256 palette entries organized as 128 locations of two entries per ...
Definition: pl111.hh:226
gem5::Pl111::width
uint16_t width
Frame buffer width - pixels per line.
Definition: pl111.hh:276
gem5::Pl111::bpp24
@ bpp24
Definition: pl111.hh:110
gem5::Pl111::LcdIcr
static const int LcdIcr
Definition: pl111.hh:76
gem5::Pl111::lcdvcomp
Bitfield< 13, 12 > lcdvcomp
Definition: pl111.hh:165
gem5::Pl111::LcdTiming1
static const int LcdTiming1
Definition: pl111.hh:67
gem5::Pl111::lcdUpbase
uint32_t lcdUpbase
Upper panel frame base address register.
Definition: pl111.hh:207
gem5::Pl111::clksel
Bitfield< 5 > clksel
Definition: pl111.hh:138
gem5::Pl111::clcdCrsrIcr
InterruptReg clcdCrsrIcr
Cursor interrupt clear register.
Definition: pl111.hh:252
gem5::Pl111::bcd
Bitfield< 26 > bcd
Definition: pl111.hh:145
gem5::Pl111::startTime
Tick startTime
Start time for frame buffer dma read.
Definition: pl111.hh:288
std::vector< DmaDoneEvent >
gem5::Pl111::cursorImage
uint32_t cursorImage[CrsrImageSize]
Cursor image RAM register 256-word wide values defining images overlaid by the hw cursor mechanism.
Definition: pl111.hh:230
gem5::Pl111::lcdpwr
Bitfield< 11 > lcdpwr
Definition: pl111.hh:164
BitUnion32
#define BitUnion32(name)
Definition: bitunion.hh:496
gem5::Pl111::lee
Bitfield< 16 > lee
Definition: pl111.hh:151
gem5::Pl111::bpp8
@ bpp8
Definition: pl111.hh:108
gem5::Pl111::lcdtft
Bitfield< 5 > lcdtft
Definition: pl111.hh:158
gem5::Pl111::buffer_size
static const int buffer_size
Definition: pl111.hh:101
gem5::Pl111::ClcdCrsrPalette0
static const int ClcdCrsrPalette0
Definition: pl111.hh:83
gem5::BmpWriter
Definition: bmpwriter.hh:54
gem5::Pl111::ClcdCrsrRis
static const int ClcdCrsrRis
Definition: pl111.hh:89
output.hh
gem5::Pl111::LcdUpCurr
static const int LcdUpCurr
Definition: pl111.hh:77
gem5::Pl111::CrsrImageSize
static const int CrsrImageSize
Definition: pl111.hh:93
gem5::Pl111::pcdhi
Bitfield< 31, 27 > pcdhi
Definition: pl111.hh:146
gem5::Pl111::avs
Bitfield< 11 > avs
Definition: pl111.hh:140
gem5::Pl111::dmaDoneEventAll
std::vector< DmaDoneEvent > dmaDoneEventAll
All pre-allocated DMA done events.
Definition: pl111.hh:351
gem5::Pl111::fb
FrameBuffer fb
Definition: pl111.hh:264
gem5::Pl111::lcdRis
InterruptReg lcdRis
Raw interrupt status register - const.
Definition: pl111.hh:219
gem5::Pl111::clcdCrsrPalette1
uint32_t clcdCrsrPalette1
Definition: pl111.hh:240
gem5::Pl111::ClcdCrsrIcr
static const int ClcdCrsrIcr
Definition: pl111.hh:88
gem5::Pl111::bepo
Bitfield< 10 > bepo
Definition: pl111.hh:163
gem5::Pl111::LcdPalette
static const int LcdPalette
Definition: pl111.hh:79
gem5::Pl111::clcdCrsrRis
InterruptReg clcdCrsrRis
Cursor raw interrupt status register - const.
Definition: pl111.hh:255
gem5::Pl111::LcdLpBase
static const int LcdLpBase
Definition: pl111.hh:71
gem5::Pl111::ClcdCrsrCtrl
static const int ClcdCrsrCtrl
Definition: pl111.hh:81
gem5::Pl111::pcdlo
pcdlo
Definition: pl111.hh:137
gem5::Pl111::LcdTiming2
static const int LcdTiming2
Definition: pl111.hh:68
gem5::Pl111::led
led
Definition: pl111.hh:150
gem5::Pl111::height
uint16_t height
Frame buffer height - lines per panel.
Definition: pl111.hh:279
gem5::Pl111::lcdTiming0
EndBitUnion(ControlReg) class DmaDoneEvent TimingReg0 lcdTiming0
Event wrapper for dmaDone()
Definition: pl111.hh:167
gem5::Named::name
virtual std::string name() const
Definition: named.hh:47
gem5::Pl111::BitUnion8
BitUnion8(InterruptReg) Bitfield< 1 > underflow
gem5::Pl111::vcomp
Bitfield< 3 > vcomp
Definition: pl111.hh:118
gem5::Event
Definition: eventq.hh:251
gem5::Pl111::acb
Bitfield< 10, 6 > acb
Definition: pl111.hh:139
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::Pl111::bpp12
@ bpp12
Definition: pl111.hh:112
gem5::Pl111::pic
OutputStream * pic
Picture of what the current frame buffer looks like.
Definition: pl111.hh:273
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::Pl111::dmaPendingNum
uint32_t dmaPendingNum
Number of pending dma reads.
Definition: pl111.hh:303
gem5::Pl111::dmaDone
void dmaDone()
DMA done event.
Definition: pl111.cc:473
gem5::Pl111::AMBA_ID
static const uint64_t AMBA_ID
Definition: pl111.hh:64
gem5::Pl111::ioe
Bitfield< 14 > ioe
Definition: pl111.hh:143
gem5::Pl111::baseaddr
Bitfield< 2 > baseaddr
Definition: pl111.hh:117
gem5::Pl111::clcdCrsrConfig
uint32_t clcdCrsrConfig
Cursor configuration register.
Definition: pl111.hh:236
gem5::Pl111::waterMark
uint32_t waterMark
DMA FIFO watermark.
Definition: pl111.hh:300
gem5::Pl111::bpp16
@ bpp16
Definition: pl111.hh:109
gem5::Pl111::LcdMaxWidth
static const int LcdMaxWidth
Definition: pl111.hh:95
gem5::Pl111::lcdbpp
Bitfield< 3, 1 > lcdbpp
Definition: pl111.hh:156
gem5::Pl111::dmaDoneEventFree
std::vector< DmaDoneEvent * > dmaDoneEventFree
Unused DMA done events that are ready to be scheduled.
Definition: pl111.hh:354
gem5::Pl111::readEvent
EventFunctionWrapper readEvent
DMA framebuffer read event.
Definition: pl111.hh:329
gem5::Pl111::lcdmono8
Bitfield< 6 > lcdmono8
Definition: pl111.hh:159
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::Pl111::LcdTiming3
static const int LcdTiming3
Definition: pl111.hh:69
gem5::Pl111::pixelConverter
PixelConverter pixelConverter() const
Definition: pl111.cc:356
framebuffer.hh
gem5::PixelConverter
Configurable RGB pixel converter.
Definition: pixel.hh:91
gem5::Pl111::ipc
Bitfield< 13 > ipc
Definition: pl111.hh:142
gem5::Pl111::lcdTiming1
TimingReg1 lcdTiming1
Vertical axis panel control register.
Definition: pl111.hh:198
gem5::Pl111::bpp1
@ bpp1
Definition: pl111.hh:105
gem5::Pl111::clcdCrsrCtrl
uint32_t clcdCrsrCtrl
Cursor control register.
Definition: pl111.hh:233
gem5::Pl111::lcdControl
ControlReg lcdControl
Control register.
Definition: pl111.hh:213
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
gem5::Pl111
Definition: pl111.hh:61
gem5::Pl111::LcdPaletteSize
static const int LcdPaletteSize
Definition: pl111.hh:92
gem5::Pl111::clcdCrsrXY
uint32_t clcdCrsrXY
Cursor XY position register.
Definition: pl111.hh:243
gem5::Pl111::LcdMaxHeight
static const int LcdMaxHeight
Definition: pl111.hh:96
gem5::AmbaDmaDevice
Definition: amba_device.hh:99
gem5::Pl111::Pl111
Pl111(const Params &p)
Definition: pl111.cc:59
gem5::Pl111::lcdLpbase
uint32_t lcdLpbase
Lower panel frame base address register.
Definition: pl111.hh:210
gem5::Pl111::pixelClock
Tick pixelClock
Pixel clock.
Definition: pl111.hh:261
gem5::Pl111::watermark
Bitfield< 16 > watermark
Definition: pl111.hh:166
gem5::Pl111::read
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: pl111.cc:99
gem5::Pl111::maxAddr
Addr maxAddr
Frame buffer max address.
Definition: pl111.hh:294
gem5::Pl111::dmaSize
static const int dmaSize
Definition: pl111.hh:98
gem5::Pl111::readFramebuffer
void readFramebuffer()
DMA framebuffer read.
Definition: pl111.cc:426
gem5::Pl111::startDma
void startDma()
start the dmas off after power is enabled
Definition: pl111.cc:418
gem5::Pl111::vbp
Bitfield< 31, 24 > vbp
Definition: pl111.hh:133
bmpwriter.hh
gem5::Pl111::enableCapture
bool enableCapture
Definition: pl111.hh:360
gem5::Pl111::LcdTiming0
static const int LcdTiming0
ARM PL111 register map.
Definition: pl111.hh:66
gem5::Pl111::ClcdCrsrPalette1
static const int ClcdCrsrPalette1
Definition: pl111.hh:84
gem5::Pl111::lcdImsc
InterruptReg lcdImsc
Interrupt mask set/clear register.
Definition: pl111.hh:216
gem5::Pl111::startAddr
Addr startAddr
Frame buffer base address.
Definition: pl111.hh:291
gem5::VncInput
Definition: vncinput.hh:89
gem5::Pl111::lcdMis
InterruptReg lcdMis
Masked interrupt status register.
Definition: pl111.hh:222
gem5::Pl111::dmaBuffer
uint8_t * dmaBuffer
CLCDC supports up to 1024x768.
Definition: pl111.hh:285
gem5::Pl111::clcdCrsrImsc
InterruptReg clcdCrsrImsc
Cursor interrupt mask set/clear register.
Definition: pl111.hh:249
gem5::Pl111::hfp
Bitfield< 23, 16 > hfp
Definition: pl111.hh:125
gem5::Pl111::updateVideoParams
void updateVideoParams()
Send updated parameters to the vnc server.
Definition: pl111.cc:398
gem5::Pl111::clcdCrsrMis
InterruptReg clcdCrsrMis
Cursor masked interrupt status register - const.
Definition: pl111.hh:258
gem5::Pl111::cpl
Bitfield< 25, 16 > cpl
Definition: pl111.hh:144
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::Pl111::converter
PixelConverter converter
Definition: pl111.hh:263
gem5::Pl111::ClcdCrsrClip
static const int ClcdCrsrClip
Definition: pl111.hh:86
gem5::Pl111::vsw
Bitfield< 15, 10 > vsw
Definition: pl111.hh:131
std::list< AddrRange >
gem5::Pl111::LcdRis
static const int LcdRis
Definition: pl111.hh:74
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::Pl111::ihs
Bitfield< 12 > ihs
Definition: pl111.hh:141
gem5::Pl111::~Pl111
~Pl111()
Definition: pl111.cc:92
gem5::Pl111::hbp
Bitfield< 31, 24 > hbp
Definition: pl111.hh:126
gem5::Pl111::bpp2
@ bpp2
Definition: pl111.hh:106
gem5::Pl111::ClcdCrsrImsc
static const int ClcdCrsrImsc
Definition: pl111.hh:87
gem5::OutputStream
Definition: output.hh:56
gem5::Pl111::ClcdCrsrXY
static const int ClcdCrsrXY
Definition: pl111.hh:85
gem5::Pl111::intEvent
EventFunctionWrapper intEvent
Wrapper to create an event out of the interrupt.
Definition: pl111.hh:358
gem5::Pl111::EndBitUnion
EndBitUnion(InterruptReg) BitUnion32(TimingReg0) Bitfield< 7
gem5::Pl111::LcdControl
static const int LcdControl
Definition: pl111.hh:72
gem5::Pl111::hsw
Bitfield< 15, 8 > hsw
Definition: pl111.hh:124
gem5::Pl111::lcdTiming3
TimingReg3 lcdTiming3
Line end control register.
Definition: pl111.hh:204
gem5::Pl111::LcdLpCurr
static const int LcdLpCurr
Definition: pl111.hh:78
gem5::Pl111::bgr
Bitfield< 8 > bgr
Definition: pl111.hh:161
gem5::Pl111::ppl
ppl
Definition: pl111.hh:123
gem5::AmbaDmaDevice::Params
AmbaDmaDeviceParams Params
Definition: amba_device.hh:109
gem5::Pl111::generateInterrupt
void generateInterrupt()
Function to generate interrupt.
Definition: pl111.cc:727
gem5::Pl111::CrsrImage
static const int CrsrImage
Definition: pl111.hh:80
gem5::Pl111::LcdUpBase
static const int LcdUpBase
Definition: pl111.hh:70

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