gem5  v22.0.0.2
vecregs.hh
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29 
30 #ifndef __ARCH_POWER_VECREGS_HH__
31 #define __ARCH_POWER_VECREGS_HH__
32 
34 #include "arch/generic/vec_reg.hh"
35 
36 namespace gem5
37 {
38 
39 namespace PowerISA
40 {
41 
42 // Not applicable to Power
45 
46 } // namespace PowerISA
47 } // namespace gem5
48 
49 #endif // __ARCH_POWER_VECREGS_HH__
vec_pred_reg.hh
vec_reg.hh
gem5::DummyVecPredRegContainer
Dummy type aliases and constants for architectures that do not implement vector predicate registers.
Definition: vec_pred_reg.hh:398
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::DummyVecRegContainer
Dummy type aliases and constants for architectures that do not implement vector registers.
Definition: vec_reg.hh:268

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