gem5  v22.0.0.2
vec_pred_reg.hh
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35 
36 #ifndef __ARCH_GENERIC_VEC_PRED_REG_HH__
37 #define __ARCH_GENERIC_VEC_PRED_REG_HH__
38 
39 #include <array>
40 #include <cassert>
41 #include <cstdint>
42 #include <string>
43 #include <type_traits>
44 #include <vector>
45 
46 #include "base/cprintf.hh"
47 #include "base/types.hh"
49 
50 namespace gem5
51 {
52 
53 template <size_t NumBits, bool Packed>
55 
72 template <typename VecElem, size_t NumElems, bool Packed, bool Const>
74 {
75  protected:
77  static constexpr size_t NUM_BITS = Packed ? NumElems :
78  sizeof(VecElem) * NumElems;
79 
80  public:
82  using Container = typename std::conditional_t<
83  Const,
86 
87  protected:
88  // Alias for this type
92 
93  public:
95 
97  template<bool Condition = !Const>
98  std::enable_if_t<Condition> reset() { container.reset(); }
99 
101  template<bool Condition = !Const>
102  std::enable_if_t<Condition> set() { container.set(); }
103 
104  template<bool Condition = !Const>
105  std::enable_if_t<Condition, MyClass&>
106  operator=(const MyClass& that)
107  {
108  container = that.container;
109  return *this;
110  }
111 
112  const bool&
113  operator[](size_t idx) const
114  {
115  return container[idx * (Packed ? 1 : sizeof(VecElem))];
116  }
117 
118  template<bool Condition = !Const>
119  std::enable_if_t<Condition, bool&>
120  operator[](size_t idx)
121  {
122  return container[idx * (Packed ? 1 : sizeof(VecElem))];
123  }
124 
127  uint8_t
128  getRaw(size_t idx) const
129  {
130  return container.getBits(idx * (Packed ? 1 : sizeof(VecElem)),
131  (Packed ? 1 : sizeof(VecElem)));
132  }
133 
135  template<bool Condition = !Const>
136  std::enable_if_t<Condition>
137  setRaw(size_t idx, uint8_t val)
138  {
139  container.setBits(idx * (Packed ? 1 : sizeof(VecElem)),
140  (Packed ? 1 : sizeof(VecElem)), val);
141  }
142 
144  template<typename VE2, size_t NE2, bool P2, bool C2>
145  bool
147  {
148  return container == that.container;
149  }
150 
152  template<typename VE2, size_t NE2, bool P2, bool C2>
153  bool
155  {
156  return !operator==(that);
157  }
158 
159  friend std::ostream&
160  operator<<(std::ostream& os, const MyClass& p)
161  {
162  // Size must be greater than 0.
163  for (int i = 0; i < NUM_BITS; i++)
164  ccprintf(os, "%s%d", i ? " " : "[", (int)p.container[i]);
165  ccprintf(os, "]");
166  return os;
167  }
168 
173  template <bool MC>
174  bool
176  size_t actual_num_elems) const
177  {
178  assert(actual_num_elems <= NumElems);
179  for (int i = 0; i < actual_num_elems; ++i) {
180  if (mask[i]) {
181  return (*this)[i];
182  }
183  }
184  return false;
185  }
186 
191  template <bool MC>
192  bool
194  size_t actual_num_elems) const
195  {
196  assert(actual_num_elems <= NumElems);
197  for (int i = 0; i < actual_num_elems; ++i) {
198  if (mask[i] && operator[](i)) {
199  return false;
200  }
201  }
202  return true;
203  }
204 
209  template <bool MC>
210  bool
212  size_t actual_num_elems) const
213  {
214  assert(actual_num_elems <= NumElems);
215  for (int i = actual_num_elems - 1; i >= 0; --i) {
216  if (mask[i]) {
217  return operator[](i);
218  }
219  }
220  return false;
221  }
222 };
223 
230 template <size_t NumBits, bool Packed>
232 {
233  static_assert(NumBits > 0,
234  "Size of a predicate register must be > 0");
235 
236  public:
237  static constexpr size_t NUM_BITS = NumBits;
238  using Container = std::array<bool, NumBits>;
239 
240  private:
242  // Alias for this type
244 
245  public:
247  VecPredRegContainer(const VecPredRegContainer &) = default;
248 
249  MyClass&
250  operator=(const MyClass& that)
251  {
252  if (&that == this)
253  return *this;
254  container = that.container;
255  return *this;
256  }
257 
259  MyClass&
261  {
262  assert(that.size() == NUM_BITS);
263  std::copy(that.begin(), that.end(), container.begin());
264  return *this;
265  }
266 
268  void
270  {
271  container.fill(false);
272  }
273 
275  void
276  set()
277  {
278  container.fill(true);
279  }
280 
282  template<size_t N2, bool P2>
283  inline bool
285  {
286  return NumBits == N2 && Packed == P2 && container == that.container;
287  }
288 
290  template<size_t N2, bool P2>
291  bool
293  {
294  return !operator==(that);
295  }
296 
298  bool& operator[](size_t idx) { return container[idx]; }
299 
302  const bool& operator[](size_t idx) const { return container[idx]; }
303 
306  uint8_t
307  getBits(size_t idx, uint8_t nbits) const
308  {
309  assert(nbits > 0 && nbits <= 8 && (idx + nbits - 1) < NumBits);
310  uint8_t v = 0;
311  idx = idx + nbits - 1;
312  for (int i = 0; i < nbits; ++i, --idx) {
313  v <<= 1;
314  v |= container[idx];
315  }
316  return v;
317  }
318 
321  void
322  setBits(size_t idx, uint8_t nbits, uint8_t bval)
323  {
324  assert(nbits > 0 && nbits <= 8 && (idx + nbits - 1) < NumBits);
325  for (int i = 0; i < nbits; ++i, ++idx) {
326  container[idx] = bval & 1;
327  bval >>= 1;
328  }
329  }
330 
331  friend std::ostream&
332  operator<<(std::ostream& os, const MyClass& p)
333  {
334  // Size must be greater than 0.
335  for (int i = 0; i < NumBits; i++)
336  ccprintf(os, "%s%d", i ? " " : "[", (int)p.container[i]);
337  ccprintf(os, "]");
338  return os;
339  }
340 
342 
347  template <typename VecElem>
348  auto
349  as() const
350  {
351  static_assert(NumBits % sizeof(VecElem) == 0,
352  "Container size incompatible with view size.");
353  return VecPredRegT<VecElem,
354  Packed ? NumBits : (NumBits / sizeof(VecElem)),
355  Packed, true>(*this);
356  }
357 
358  template <typename VecElem>
359  auto
360  as()
361  {
362  static_assert(NumBits % sizeof(VecElem) == 0,
363  "Container size incompatible with view size.");
364  return VecPredRegT<VecElem,
365  Packed ? NumBits : (NumBits / sizeof(VecElem)),
366  Packed, false>(*this);
367  }
369 };
370 
371 template <size_t NumBits, bool Packed>
372 struct ParseParam<VecPredRegContainer<NumBits, Packed>>
373 {
374  static bool
375  parse(const std::string &s, VecPredRegContainer<NumBits, Packed> &value)
376  {
377  int i = 0;
378  for (const auto& c: s)
379  value[i++] = (c == '1');
380  return true;
381  }
382 };
383 
384 template <size_t NumBits, bool Packed>
385 struct ShowParam<VecPredRegContainer<NumBits, Packed>>
386 {
387  static void
388  show(std::ostream &os, const VecPredRegContainer<NumBits, Packed> &value)
389  {
390  for (auto b: value.container)
391  ccprintf(os, "%d", b);
392  }
393 };
394 
399 {
401  bool operator == (const DummyVecPredRegContainer &d) const { return true; }
402  bool operator != (const DummyVecPredRegContainer &d) const { return true; }
403  template <typename VecElem>
404  VecElem *as() { return nullptr; }
405 };
406 template <>
408 {
409  static bool
410  parse(const std::string &s, DummyVecPredRegContainer &value)
411  {
412  return false;
413  }
414 };
415 static_assert(sizeof(DummyVecPredRegContainer) == sizeof(RegVal));
416 static inline std::ostream &
417 operator<<(std::ostream &os, const DummyVecPredRegContainer &d)
418 {
419  return os;
420 }
422 
423 } // namespace gem5
424 
425 #endif // __ARCH_GENERIC_VEC_PRED_REG_HH__
gem5::operator<<
std::ostream & operator<<(std::ostream &os, const ArmSemihosting::InPlaceArg &ipa)
Definition: semihosting.cc:1054
gem5::VegaISA::s
Bitfield< 1 > s
Definition: pagetable.hh:64
gem5::VecPredRegContainer::setBits
void setBits(size_t idx, uint8_t nbits, uint8_t bval)
Set a subset of bits starting from a specific element in the container.
Definition: vec_pred_reg.hh:322
gem5::VecPredRegContainer::operator!=
bool operator!=(const VecPredRegContainer< N2, P2 > &that) const
Inequality operator, required to compare thread contexts.
Definition: vec_pred_reg.hh:292
gem5::VecPredRegContainer
Generic predicate register container.
Definition: vec_pred_reg.hh:54
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::ArmISA::VecPredRegContainer
VecPredReg::Container VecPredRegContainer
Definition: vec.hh:68
gem5::VecPredRegT::getRaw
uint8_t getRaw(size_t idx) const
Return an element of the predicate register as it appears in the raw (untyped) internal representatio...
Definition: vec_pred_reg.hh:128
gem5::VecPredRegT::setRaw
std::enable_if_t< Condition > setRaw(size_t idx, uint8_t val)
Write a raw value in an element of the predicate register.
Definition: vec_pred_reg.hh:137
gem5::VecPredRegContainer::container
Container container
Definition: vec_pred_reg.hh:241
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
gem5::VecPredRegT::firstActive
bool firstActive(const VecPredRegT< VecElem, NumElems, Packed, MC > &mask, size_t actual_num_elems) const
Returns true if the first active element of the register is true.
Definition: vec_pred_reg.hh:175
std::vector< uint8_t >
gem5::VecPredRegT::operator[]
const bool & operator[](size_t idx) const
Definition: vec_pred_reg.hh:113
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::DummyVecPredRegContainer::operator!=
bool operator!=(const DummyVecPredRegContainer &d) const
Definition: vec_pred_reg.hh:402
gem5::ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:130
gem5::VecPredRegT::operator!=
bool operator!=(const VecPredRegT< VE2, NE2, P2, C2 > &that) const
Inequality operator, required to compare thread contexts.
Definition: vec_pred_reg.hh:154
gem5::ShowParam
Definition: serialize_handlers.hh:125
gem5::mask
constexpr uint64_t mask(unsigned nbits)
Generate a 64-bit mask of 'nbits' 1s, right justified.
Definition: bitfield.hh:63
gem5::VecPredRegContainer::set
void set()
Sets the predicate register to an all-true value.
Definition: vec_pred_reg.hh:276
gem5::VecPredRegT::operator==
bool operator==(const VecPredRegT< VE2, NE2, P2, C2 > &that) const
Equality operator, required to compare thread contexts.
Definition: vec_pred_reg.hh:146
gem5::VegaISA::c
Bitfield< 2 > c
Definition: pagetable.hh:63
gem5::ArmISA::b
Bitfield< 7 > b
Definition: misc_types.hh:382
gem5::VecPredRegContainer::operator=
MyClass & operator=(const MyClass &that)
Definition: vec_pred_reg.hh:250
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::VecPredRegContainer::as
auto as() const
Create a view of this container.
Definition: vec_pred_reg.hh:349
gem5::VecPredRegT
Predicate register view.
Definition: vec_pred_reg.hh:73
gem5::ArmISA::d
Bitfield< 9 > d
Definition: misc_types.hh:64
gem5::VecPredRegContainer::operator[]
const bool & operator[](size_t idx) const
Returns a const reference to a specific element of the internal container.
Definition: vec_pred_reg.hh:302
gem5::VecPredRegContainer::getBits
uint8_t getBits(size_t idx, uint8_t nbits) const
Returns a subset of bits starting from a specific element in the container.
Definition: vec_pred_reg.hh:307
cprintf.hh
gem5::VecPredRegT::set
std::enable_if_t< Condition > set()
Reset the register to an all-true value.
Definition: vec_pred_reg.hh:102
gem5::VecPredRegT::operator<<
friend std::ostream & operator<<(std::ostream &os, const MyClass &p)
Definition: vec_pred_reg.hh:160
gem5::DummyVecPredRegContainer::as
VecElem * as()
Definition: vec_pred_reg.hh:404
gem5::VecPredRegT::reset
std::enable_if_t< Condition > reset()
Reset the register to an all-false value.
Definition: vec_pred_reg.hh:98
gem5::VecPredRegT::operator[]
std::enable_if_t< Condition, bool & > operator[](size_t idx)
Definition: vec_pred_reg.hh:120
gem5::VecPredRegContainer::operator=
MyClass & operator=(const std::vector< uint8_t > &that)
Required for de-serialization.
Definition: vec_pred_reg.hh:260
gem5::ParseParam< DummyVecPredRegContainer >::parse
static bool parse(const std::string &s, DummyVecPredRegContainer &value)
Definition: vec_pred_reg.hh:410
gem5::VecPredRegT::Container
typename std::conditional_t< Const, const VecPredRegContainer< NUM_BITS, Packed >, VecPredRegContainer< NUM_BITS, Packed > > Container
Container type alias.
Definition: vec_pred_reg.hh:85
gem5::VecPredRegT::lastActive
bool lastActive(const VecPredRegT< VecElem, NumElems, Packed, MC > &mask, size_t actual_num_elems) const
Returns true if the last active element of the register is true.
Definition: vec_pred_reg.hh:211
gem5::VecPredRegContainer::operator[]
bool & operator[](size_t idx)
Returns a reference to a specific element of the internal container.
Definition: vec_pred_reg.hh:298
gem5::VegaISA::v
Bitfield< 0 > v
Definition: pagetable.hh:65
gem5::VecPredRegContainer::VecPredRegContainer
VecPredRegContainer()
Definition: vec_pred_reg.hh:246
serialize_handlers.hh
gem5::ArmISA::VecElem
uint32_t VecElem
Definition: vec.hh:60
types.hh
gem5::X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:803
gem5::VecPredRegContainer::MyClass
VecPredRegContainer< NumBits, Packed > MyClass
Definition: vec_pred_reg.hh:243
gem5::VecPredRegContainer::NUM_BITS
static constexpr size_t NUM_BITS
Definition: vec_pred_reg.hh:237
gem5::DummyVecPredRegContainer::filler
RegVal filler
Definition: vec_pred_reg.hh:400
gem5::VecPredRegT::container
Container & container
Container corresponding to this view.
Definition: vec_pred_reg.hh:91
gem5::VecPredRegT::NUM_BITS
static constexpr size_t NUM_BITS
Size of the register in bits.
Definition: vec_pred_reg.hh:77
gem5::VecPredRegContainer::reset
void reset()
Resets the predicate register to an all-false register.
Definition: vec_pred_reg.hh:269
gem5::DummyVecPredRegContainer
Dummy type aliases and constants for architectures that do not implement vector predicate registers.
Definition: vec_pred_reg.hh:398
gem5::ParseParam< VecPredRegContainer< NumBits, Packed > >::parse
static bool parse(const std::string &s, VecPredRegContainer< NumBits, Packed > &value)
Definition: vec_pred_reg.hh:375
gem5::ParseParam
Definition: serialize_handlers.hh:78
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::VecPredRegContainer::as
auto as()
Definition: vec_pred_reg.hh:360
gem5::VecPredRegContainer< size, T >::Container
std::array< bool, NumBits > Container
Definition: vec_pred_reg.hh:238
gem5::VecPredRegT::VecPredRegT
VecPredRegT(Container &c)
Definition: vec_pred_reg.hh:94
gem5::VecPredRegContainer::operator<<
friend std::ostream & operator<<(std::ostream &os, const MyClass &p)
Definition: vec_pred_reg.hh:332
gem5::VecPredRegContainer::operator==
bool operator==(const VecPredRegContainer< N2, P2 > &that) const
Equality operator, required to compare thread contexts.
Definition: vec_pred_reg.hh:284
gem5::VecPredRegT::noneActive
bool noneActive(const VecPredRegT< VecElem, NumElems, Packed, MC > &mask, size_t actual_num_elems) const
Returns true if there are no active elements in the register.
Definition: vec_pred_reg.hh:193
gem5::ShowParam< VecPredRegContainer< NumBits, Packed > >::show
static void show(std::ostream &os, const VecPredRegContainer< NumBits, Packed > &value)
Definition: vec_pred_reg.hh:388
gem5::DummyVecPredRegContainer::operator==
bool operator==(const DummyVecPredRegContainer &d) const
Definition: vec_pred_reg.hh:401
gem5::VecPredRegT::operator=
std::enable_if_t< Condition, MyClass & > operator=(const MyClass &that)
Definition: vec_pred_reg.hh:106

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