gem5  v21.1.0.2
vec_pred_reg.hh
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35 
36 #ifndef __ARCH_GENERIC_VEC_PRED_REG_HH__
37 #define __ARCH_GENERIC_VEC_PRED_REG_HH__
38 
39 #include <array>
40 #include <cassert>
41 #include <cstdint>
42 #include <string>
43 #include <type_traits>
44 #include <vector>
45 
46 #include "base/cprintf.hh"
48 
49 namespace gem5
50 {
51 
52 template <size_t NumBits, bool Packed>
54 
71 template <typename VecElem, size_t NumElems, bool Packed, bool Const>
73 {
74  protected:
76  static constexpr size_t NUM_BITS = Packed ? NumElems :
77  sizeof(VecElem) * NumElems;
78 
79  public:
81  using Container = typename std::conditional_t<
82  Const,
85 
86  protected:
87  // Alias for this type
91 
92  public:
94 
96  template<bool Condition = !Const>
97  std::enable_if_t<Condition> reset() { container.reset(); }
98 
100  template<bool Condition = !Const>
101  std::enable_if_t<Condition> set() { container.set(); }
102 
103  template<bool Condition = !Const>
104  std::enable_if_t<Condition, MyClass&>
105  operator=(const MyClass& that)
106  {
107  container = that.container;
108  return *this;
109  }
110 
111  const bool&
112  operator[](size_t idx) const
113  {
114  return container[idx * (Packed ? 1 : sizeof(VecElem))];
115  }
116 
117  template<bool Condition = !Const>
118  std::enable_if_t<Condition, bool&>
119  operator[](size_t idx)
120  {
121  return container[idx * (Packed ? 1 : sizeof(VecElem))];
122  }
123 
126  uint8_t
127  getRaw(size_t idx) const
128  {
129  return container.getBits(idx * (Packed ? 1 : sizeof(VecElem)),
130  (Packed ? 1 : sizeof(VecElem)));
131  }
132 
134  template<bool Condition = !Const>
135  std::enable_if_t<Condition>
136  setRaw(size_t idx, uint8_t val)
137  {
138  container.setBits(idx * (Packed ? 1 : sizeof(VecElem)),
139  (Packed ? 1 : sizeof(VecElem)), val);
140  }
141 
143  template<typename VE2, size_t NE2, bool P2, bool C2>
144  bool
146  {
147  return container == that.container;
148  }
149 
151  template<typename VE2, size_t NE2, bool P2, bool C2>
152  bool
154  {
155  return !operator==(that);
156  }
157 
158  friend std::ostream&
159  operator<<(std::ostream& os, const MyClass& p)
160  {
161  // Size must be greater than 0.
162  for (int i = 0; i < NUM_BITS; i++)
163  ccprintf(os, "%s%d", i ? " " : "[", (int)p.container[i]);
164  ccprintf(os, "]");
165  return os;
166  }
167 
172  template <bool MC>
173  bool
175  size_t actual_num_elems) const
176  {
177  assert(actual_num_elems <= NumElems);
178  for (int i = 0; i < actual_num_elems; ++i) {
179  if (mask[i]) {
180  return (*this)[i];
181  }
182  }
183  return false;
184  }
185 
190  template <bool MC>
191  bool
193  size_t actual_num_elems) const
194  {
195  assert(actual_num_elems <= NumElems);
196  for (int i = 0; i < actual_num_elems; ++i) {
197  if (mask[i] && operator[](i)) {
198  return false;
199  }
200  }
201  return true;
202  }
203 
208  template <bool MC>
209  bool
211  size_t actual_num_elems) const
212  {
213  assert(actual_num_elems <= NumElems);
214  for (int i = actual_num_elems - 1; i >= 0; --i) {
215  if (mask[i]) {
216  return operator[](i);
217  }
218  }
219  return false;
220  }
221 };
222 
229 template <size_t NumBits, bool Packed>
231 {
232  static_assert(NumBits > 0,
233  "Size of a predicate register must be > 0");
234 
235  public:
236  static constexpr size_t NUM_BITS = NumBits;
237  using Container = std::array<bool, NumBits>;
238 
239  private:
241  // Alias for this type
243 
244  public:
246  VecPredRegContainer(const VecPredRegContainer &) = default;
247 
248  MyClass&
249  operator=(const MyClass& that)
250  {
251  if (&that == this)
252  return *this;
253  container = that.container;
254  return *this;
255  }
256 
258  MyClass&
260  {
261  assert(that.size() == NUM_BITS);
262  std::copy(that.begin(), that.end(), container.begin());
263  return *this;
264  }
265 
267  void
269  {
270  container.fill(false);
271  }
272 
274  void
275  set()
276  {
277  container.fill(true);
278  }
279 
281  template<size_t N2, bool P2>
282  inline bool
284  {
285  return NumBits == N2 && Packed == P2 && container == that.container;
286  }
287 
289  template<size_t N2, bool P2>
290  bool
292  {
293  return !operator==(that);
294  }
295 
297  bool& operator[](size_t idx) { return container[idx]; }
298 
301  const bool& operator[](size_t idx) const { return container[idx]; }
302 
305  uint8_t
306  getBits(size_t idx, uint8_t nbits) const
307  {
308  assert(nbits > 0 && nbits <= 8 && (idx + nbits - 1) < NumBits);
309  uint8_t v = 0;
310  idx = idx + nbits - 1;
311  for (int i = 0; i < nbits; ++i, --idx) {
312  v <<= 1;
313  v |= container[idx];
314  }
315  return v;
316  }
317 
320  void
321  setBits(size_t idx, uint8_t nbits, uint8_t bval)
322  {
323  assert(nbits > 0 && nbits <= 8 && (idx + nbits - 1) < NumBits);
324  for (int i = 0; i < nbits; ++i, ++idx) {
325  container[idx] = bval & 1;
326  bval >>= 1;
327  }
328  }
329 
330  friend std::ostream&
331  operator<<(std::ostream& os, const MyClass& p)
332  {
333  // Size must be greater than 0.
334  for (int i = 0; i < NumBits; i++)
335  ccprintf(os, "%s%d", i ? " " : "[", (int)p.container[i]);
336  ccprintf(os, "]");
337  return os;
338  }
339 
341 
346  template <typename VecElem>
347  VecPredRegT<VecElem, NumBits / sizeof(VecElem), Packed, true>
348  as() const
349  {
350  static_assert(NumBits % sizeof(VecElem) == 0,
351  "Container size incompatible with view size.");
352  return VecPredRegT<VecElem, NumBits / sizeof(VecElem), Packed, true>(
353  *this);
354  }
355 
356  template <typename VecElem>
357  VecPredRegT<VecElem, NumBits / sizeof(VecElem), Packed, false>
358  as()
359  {
360  static_assert(NumBits % sizeof(VecElem) == 0,
361  "Container size incompatible with view size.");
362  return VecPredRegT<VecElem, NumBits / sizeof(VecElem), Packed, false>(
363  *this);
364  }
366 };
367 
368 template <size_t NumBits, bool Packed>
369 struct ParseParam<VecPredRegContainer<NumBits, Packed>>
370 {
371  static bool
372  parse(const std::string &s, VecPredRegContainer<NumBits, Packed> &value)
373  {
374  int i = 0;
375  for (const auto& c: s)
376  value[i++] = (c == '1');
377  return true;
378  }
379 };
380 
381 template <size_t NumBits, bool Packed>
382 struct ShowParam<VecPredRegContainer<NumBits, Packed>>
383 {
384  static void
385  show(std::ostream &os, const VecPredRegContainer<NumBits, Packed> &value)
386  {
387  for (auto b: value.container)
388  ccprintf(os, "%d", b);
389  }
390 };
391 
397 
398 } // namespace gem5
399 
400 #endif // __ARCH_GENERIC_VEC_PRED_REG_HH__
gem5::VecPredRegContainer::setBits
void setBits(size_t idx, uint8_t nbits, uint8_t bval)
Set a subset of bits starting from a specific element in the container.
Definition: vec_pred_reg.hh:321
gem5::VecPredRegContainer::operator!=
bool operator!=(const VecPredRegContainer< N2, P2 > &that) const
Inequality operator, required to compare thread contexts.
Definition: vec_pred_reg.hh:291
gem5::VecPredRegContainer
Generic predicate register container.
Definition: vec_pred_reg.hh:53
gem5::ArmISA::VecPredRegContainer
VecPredReg::Container VecPredRegContainer
Definition: vec.hh:68
gem5::VecPredRegT::getRaw
uint8_t getRaw(size_t idx) const
Return an element of the predicate register as it appears in the raw (untyped) internal representatio...
Definition: vec_pred_reg.hh:127
gem5::VecPredRegT::setRaw
std::enable_if_t< Condition > setRaw(size_t idx, uint8_t val)
Write a raw value in an element of the predicate register.
Definition: vec_pred_reg.hh:136
gem5::VecPredRegContainer::container
Container container
Definition: vec_pred_reg.hh:240
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::VecPredRegT::firstActive
bool firstActive(const VecPredRegT< VecElem, NumElems, Packed, MC > &mask, size_t actual_num_elems) const
Returns true if the first active element of the register is true.
Definition: vec_pred_reg.hh:174
std::vector< uint8_t >
gem5::VecPredRegT::operator[]
const bool & operator[](size_t idx) const
Definition: vec_pred_reg.hh:112
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::VecPredRegContainer::as
VecPredRegT< VecElem, NumBits/sizeof(VecElem), Packed, false > as()
Definition: vec_pred_reg.hh:358
gem5::ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:130
gem5::VecPredRegT::operator!=
bool operator!=(const VecPredRegT< VE2, NE2, P2, C2 > &that) const
Inequality operator, required to compare thread contexts.
Definition: vec_pred_reg.hh:153
gem5::ShowParam
Definition: serialize_handlers.hh:125
gem5::mask
constexpr uint64_t mask(unsigned nbits)
Generate a 64-bit mask of 'nbits' 1s, right justified.
Definition: bitfield.hh:63
gem5::VecPredRegContainer::set
void set()
Sets the predicate register to an all-true value.
Definition: vec_pred_reg.hh:275
gem5::VecPredRegT::operator==
bool operator==(const VecPredRegT< VE2, NE2, P2, C2 > &that) const
Equality operator, required to compare thread contexts.
Definition: vec_pred_reg.hh:145
gem5::ArmISA::b
Bitfield< 7 > b
Definition: misc_types.hh:381
gem5::VecPredRegContainer::operator=
MyClass & operator=(const MyClass &that)
Definition: vec_pred_reg.hh:249
gem5::VecPredRegT
Predicate register view.
Definition: vec_pred_reg.hh:72
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::VecPredRegContainer::operator[]
const bool & operator[](size_t idx) const
Returns a const reference to a specific element of the internal container.
Definition: vec_pred_reg.hh:301
gem5::ArmISA::v
Bitfield< 28 > v
Definition: misc_types.hh:54
gem5::ArmISA::s
Bitfield< 4 > s
Definition: misc_types.hh:561
gem5::VecPredRegContainer::getBits
uint8_t getBits(size_t idx, uint8_t nbits) const
Returns a subset of bits starting from a specific element in the container.
Definition: vec_pred_reg.hh:306
cprintf.hh
gem5::VecPredRegT::set
std::enable_if_t< Condition > set()
Reset the register to an all-true value.
Definition: vec_pred_reg.hh:101
gem5::VecPredRegT::operator<<
friend std::ostream & operator<<(std::ostream &os, const MyClass &p)
Definition: vec_pred_reg.hh:159
gem5::VecPredRegT::reset
std::enable_if_t< Condition > reset()
Reset the register to an all-false value.
Definition: vec_pred_reg.hh:97
gem5::ArmISA::c
Bitfield< 29 > c
Definition: misc_types.hh:53
gem5::VecPredRegT::operator[]
std::enable_if_t< Condition, bool & > operator[](size_t idx)
Definition: vec_pred_reg.hh:119
gem5::VecPredRegContainer::operator=
MyClass & operator=(const std::vector< uint8_t > &that)
Required for de-serialization.
Definition: vec_pred_reg.hh:259
gem5::VecPredRegT::Container
typename std::conditional_t< Const, const VecPredRegContainer< NUM_BITS, Packed >, VecPredRegContainer< NUM_BITS, Packed > > Container
Container type alias.
Definition: vec_pred_reg.hh:84
gem5::VecPredRegT::lastActive
bool lastActive(const VecPredRegT< VecElem, NumElems, Packed, MC > &mask, size_t actual_num_elems) const
Returns true if the last active element of the register is true.
Definition: vec_pred_reg.hh:210
gem5::VecPredRegContainer::operator[]
bool & operator[](size_t idx)
Returns a reference to a specific element of the internal container.
Definition: vec_pred_reg.hh:297
gem5::VecPredRegContainer::as
VecPredRegT< VecElem, NumBits/sizeof(VecElem), Packed, true > as() const
Create a view of this container.
Definition: vec_pred_reg.hh:348
gem5::VecPredRegContainer::VecPredRegContainer
VecPredRegContainer()
Definition: vec_pred_reg.hh:245
serialize_handlers.hh
gem5::ArmISA::VecElem
uint32_t VecElem
Definition: vec.hh:60
gem5::X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:809
gem5::VecPredRegContainer::MyClass
VecPredRegContainer< NumBits, Packed > MyClass
Definition: vec_pred_reg.hh:242
gem5::VecPredRegContainer::NUM_BITS
static constexpr size_t NUM_BITS
Definition: vec_pred_reg.hh:236
gem5::VecPredRegT::container
Container & container
Container corresponding to this view.
Definition: vec_pred_reg.hh:90
gem5::VecPredRegT::NUM_BITS
static constexpr size_t NUM_BITS
Size of the register in bits.
Definition: vec_pred_reg.hh:76
gem5::VecPredRegContainer::reset
void reset()
Resets the predicate register to an all-false register.
Definition: vec_pred_reg.hh:268
gem5::ParseParam< VecPredRegContainer< NumBits, Packed > >::parse
static bool parse(const std::string &s, VecPredRegContainer< NumBits, Packed > &value)
Definition: vec_pred_reg.hh:372
gem5::ParseParam
Definition: serialize_handlers.hh:78
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::VecPredRegContainer::Container
std::array< bool, NumBits > Container
Definition: vec_pred_reg.hh:237
gem5::VecPredRegT::VecPredRegT
VecPredRegT(Container &c)
Definition: vec_pred_reg.hh:93
gem5::VecPredRegContainer::operator<<
friend std::ostream & operator<<(std::ostream &os, const MyClass &p)
Definition: vec_pred_reg.hh:331
gem5::VecPredRegContainer::operator==
bool operator==(const VecPredRegContainer< N2, P2 > &that) const
Equality operator, required to compare thread contexts.
Definition: vec_pred_reg.hh:283
gem5::VecPredRegT::noneActive
bool noneActive(const VecPredRegT< VecElem, NumElems, Packed, MC > &mask, size_t actual_num_elems) const
Returns true if there are no active elements in the register.
Definition: vec_pred_reg.hh:192
gem5::ShowParam< VecPredRegContainer< NumBits, Packed > >::show
static void show(std::ostream &os, const VecPredRegContainer< NumBits, Packed > &value)
Definition: vec_pred_reg.hh:385
gem5::VecPredRegT::operator=
std::enable_if_t< Condition, MyClass & > operator=(const MyClass &that)
Definition: vec_pred_reg.hh:105

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