gem5  v21.1.0.2
vec_reg.hh
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37 
96 #ifndef __ARCH_GENERIC_VEC_REG_HH__
97 #define __ARCH_GENERIC_VEC_REG_HH__
98 
99 #include <array>
100 #include <cstdint>
101 #include <iostream>
102 #include <string>
103 
104 #include "base/cprintf.hh"
105 #include "base/logging.hh"
106 #include "sim/serialize_handlers.hh"
107 
108 namespace gem5
109 {
110 
111 constexpr unsigned MaxVecRegLenInBytes = 4096;
112 
120 template <size_t SIZE>
122 {
123  private:
124  static_assert(SIZE > 0,
125  "Cannot create Vector Register Container of zero size");
126  static_assert(SIZE <= MaxVecRegLenInBytes,
127  "Vector Register size limit exceeded");
128  public:
129  static constexpr inline size_t size() { return SIZE; };
130  using Container = std::array<uint8_t, SIZE>;
131  private:
132  // 16-byte aligned to support 128bit element view
133  alignas(16) Container container;
134 
135  public:
137  VecRegContainer(const VecRegContainer &) = default;
138 
140  void zero() { memset(container.data(), 0, SIZE); }
141 
147  {
148  if (&that != this)
149  std::memcpy(container.data(), that.container.data(), SIZE);
150  return *this;
151  }
157  template<size_t S2>
158  inline bool
159  operator==(const VecRegContainer<S2>& that) const
160  {
161  return SIZE == S2 &&
162  !memcmp(container.data(), that.container.data(), SIZE);
163  }
167  template<size_t S2>
168  bool
169  operator!=(const VecRegContainer<S2>& that) const
170  {
171  return !operator==(that);
172  }
173 
185  template <typename VecElem>
186  VecElem *
187  as()
188  {
189  static_assert(SIZE % sizeof(VecElem) == 0,
190  "VecElem does not evenly divide the register size");
191  return (VecElem *)container.data();
192  }
193 
194  template <typename VecElem>
195  const VecElem *
196  as() const
197  {
198  static_assert(SIZE % sizeof(VecElem) == 0,
199  "VecElem does not evenly divide the register size");
200  return (VecElem *)container.data();
201  }
202 
203  friend std::ostream&
204  operator<<(std::ostream& os, const VecRegContainer<SIZE>& v)
205  {
206  // When printing for human consumption, break into 4 byte chunks.
207  ccprintf(os, "[");
208  size_t count = 0;
209  for (auto& b: v.container) {
210  if (count && (count % 4) == 0)
211  os << "_";
212  ccprintf(os, "%02x", b);
213  count++;
214  }
215  ccprintf(os, "]");
216  return os;
217  }
218 
224 };
225 
230 template <size_t Sz>
232 {
233  static bool
234  parse(const std::string &str, VecRegContainer<Sz> &value)
235  {
236  fatal_if(str.size() > 2 * Sz,
237  "Vector register value overflow at unserialize");
238 
239  for (int i = 0; i < Sz; i++) {
240  uint8_t b = 0;
241  if (2 * i < value.size())
242  b = stoul(str.substr(i * 2, 2), nullptr, 16);
243  value.template as<uint8_t>()[i] = b;
244  }
245  return true;
246  }
247 };
248 
249 template <size_t Sz>
251 {
252  static void
253  show(std::ostream &os, const VecRegContainer<Sz> &value)
254  {
255  for (auto& b: value.container)
256  ccprintf(os, "%02x", b);
257  }
258 };
266 using DummyVecElem = uint32_t;
267 constexpr unsigned DummyNumVecElemPerVecReg = 2;
268 using DummyVecRegContainer =
272 } // namespace gem5
273 
274 #endif /* __ARCH_GENERIC_VEC_REG_HH__ */
gem5::DummyVecElem
uint32_t DummyVecElem
Dummy type aliases and constants for architectures that do not implement vector registers.
Definition: vec_reg.hh:266
gem5::VecRegContainer::size
static constexpr size_t size()
Definition: vec_reg.hh:129
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::VecRegContainer::operator<<
friend std::ostream & operator<<(std::ostream &os, const VecRegContainer< SIZE > &v)
Definition: vec_reg.hh:204
gem5::ParseParam< VecRegContainer< Sz > >::parse
static bool parse(const std::string &str, VecRegContainer< Sz > &value)
Definition: vec_reg.hh:234
gem5::ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:130
gem5::ShowParam
Definition: serialize_handlers.hh:125
gem5::VecRegContainer
Vector Register Abstraction This generic class is the model in a particularization of MVC,...
Definition: vec_reg.hh:121
gem5::ArmISA::b
Bitfield< 7 > b
Definition: misc_types.hh:381
gem5::VecRegContainer::as
VecElem * as()
View interposers.
Definition: vec_reg.hh:187
gem5::X86ISA::count
count
Definition: misc.hh:709
gem5::ArmISA::v
Bitfield< 28 > v
Definition: misc_types.hh:54
gem5::MaxVecRegLenInBytes
constexpr unsigned MaxVecRegLenInBytes
Definition: vec_reg.hh:111
cprintf.hh
gem5::VecRegContainer::container
Container container
Definition: vec_reg.hh:133
gem5::ShowParam< VecRegContainer< Sz > >::show
static void show(std::ostream &os, const VecRegContainer< Sz > &value)
Definition: vec_reg.hh:253
gem5::HtmFailureFaultCause::SIZE
@ SIZE
serialize_handlers.hh
gem5::ArmISA::VecElem
uint32_t VecElem
Definition: vec.hh:60
gem5::VecRegContainer< sizeof(DataType) *NumVecElemPerVecReg >::Container
std::array< uint8_t, SIZE > Container
Definition: vec_reg.hh:130
gem5::X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:809
gem5::VecRegContainer::operator!=
bool operator!=(const VecRegContainer< S2 > &that) const
Inequality operator.
Definition: vec_reg.hh:169
gem5::VecRegContainer::zero
void zero()
Zero the container.
Definition: vec_reg.hh:140
logging.hh
gem5::VecRegContainer::as
const VecElem * as() const
Definition: vec_reg.hh:196
gem5::VecRegContainer::VecRegContainer
VecRegContainer()
Definition: vec_reg.hh:136
gem5::DummyNumVecElemPerVecReg
constexpr unsigned DummyNumVecElemPerVecReg
Definition: vec_reg.hh:267
gem5::ParseParam
Definition: serialize_handlers.hh:78
fatal_if
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
Definition: logging.hh:225
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::VecRegContainer::operator=
VecRegContainer< SIZE > & operator=(const VecRegContainer< SIZE > &that)
Assignment operators.
Definition: vec_reg.hh:146
gem5::VecRegContainer::operator==
bool operator==(const VecRegContainer< S2 > &that) const
Equality operator.
Definition: vec_reg.hh:159

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