gem5  v22.0.0.2
vec_reg.hh
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37 
97 #ifndef __ARCH_GENERIC_VEC_REG_HH__
98 #define __ARCH_GENERIC_VEC_REG_HH__
99 
100 #include <array>
101 #include <cstdint>
102 #include <iostream>
103 #include <string>
104 
105 #include "base/cprintf.hh"
106 #include "base/logging.hh"
107 #include "base/types.hh"
108 #include "sim/serialize_handlers.hh"
109 
110 namespace gem5
111 {
112 
113 constexpr unsigned MaxVecRegLenInBytes = 4096;
114 
122 template <size_t SIZE>
124 {
125  private:
126  static_assert(SIZE > 0,
127  "Cannot create Vector Register Container of zero size");
128  static_assert(SIZE <= MaxVecRegLenInBytes,
129  "Vector Register size limit exceeded");
130  public:
131  static constexpr inline size_t size() { return SIZE; };
132  using Container = std::array<uint8_t, SIZE>;
133  private:
134  // 16-byte aligned to support 128bit element view
135  alignas(16) Container container;
136 
137  public:
139  VecRegContainer(const VecRegContainer &) = default;
140 
142  void zero() { memset(container.data(), 0, SIZE); }
143 
149  {
150  if (&that != this)
151  std::memcpy(container.data(), that.container.data(), SIZE);
152  return *this;
153  }
159  template<size_t S2>
160  inline bool
161  operator==(const VecRegContainer<S2>& that) const
162  {
163  return SIZE == S2 &&
164  !memcmp(container.data(), that.container.data(), SIZE);
165  }
169  template<size_t S2>
170  bool
171  operator!=(const VecRegContainer<S2>& that) const
172  {
173  return !operator==(that);
174  }
175 
187  template <typename VecElem>
188  VecElem *
189  as()
190  {
191  static_assert(SIZE % sizeof(VecElem) == 0,
192  "VecElem does not evenly divide the register size");
193  return (VecElem *)container.data();
194  }
195 
196  template <typename VecElem>
197  const VecElem *
198  as() const
199  {
200  static_assert(SIZE % sizeof(VecElem) == 0,
201  "VecElem does not evenly divide the register size");
202  return (VecElem *)container.data();
203  }
204 
205  friend std::ostream&
206  operator<<(std::ostream& os, const VecRegContainer<SIZE>& v)
207  {
208  // When printing for human consumption, break into 4 byte chunks.
209  ccprintf(os, "[");
210  size_t count = 0;
211  for (auto& b: v.container) {
212  if (count && (count % 4) == 0)
213  os << "_";
214  ccprintf(os, "%02x", b);
215  count++;
216  }
217  ccprintf(os, "]");
218  return os;
219  }
220 
226 };
227 
232 template <size_t Sz>
234 {
235  static bool
236  parse(const std::string &str, VecRegContainer<Sz> &value)
237  {
238  fatal_if(str.size() > 2 * Sz,
239  "Vector register value overflow at unserialize");
240 
241  for (int i = 0; i < Sz; i++) {
242  uint8_t b = 0;
243  if (2 * i < str.size())
244  b = stoul(str.substr(i * 2, 2), nullptr, 16);
245  value.template as<uint8_t>()[i] = b;
246  }
247  return true;
248  }
249 };
250 
251 template <size_t Sz>
253 {
254  static void
255  show(std::ostream &os, const VecRegContainer<Sz> &value)
256  {
257  for (auto& b: value.container)
258  ccprintf(os, "%02x", b);
259  }
260 };
269 {
271  bool operator == (const DummyVecRegContainer &d) const { return true; }
272  bool operator != (const DummyVecRegContainer &d) const { return true; }
273  template <typename VecElem>
274  VecElem *as() { return nullptr; }
275 };
276 template <>
278 {
279  static bool
280  parse(const std::string &s, DummyVecRegContainer &value)
281  {
282  return false;
283  }
284 };
285 static_assert(sizeof(DummyVecRegContainer) == sizeof(RegVal));
286 static inline std::ostream &
287 operator<<(std::ostream &os, const DummyVecRegContainer &d)
288 {
289  return os;
290 }
293 } // namespace gem5
294 
295 #endif /* __ARCH_GENERIC_VEC_REG_HH__ */
gem5::operator<<
std::ostream & operator<<(std::ostream &os, const ArmSemihosting::InPlaceArg &ipa)
Definition: semihosting.cc:1054
gem5::VegaISA::s
Bitfield< 1 > s
Definition: pagetable.hh:64
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::ParseParam< DummyVecRegContainer >::parse
static bool parse(const std::string &s, DummyVecRegContainer &value)
Definition: vec_reg.hh:280
gem5::VecRegContainer::size
static constexpr size_t size()
Definition: vec_reg.hh:131
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::VecRegContainer::operator<<
friend std::ostream & operator<<(std::ostream &os, const VecRegContainer< SIZE > &v)
Definition: vec_reg.hh:206
gem5::ParseParam< VecRegContainer< Sz > >::parse
static bool parse(const std::string &str, VecRegContainer< Sz > &value)
Definition: vec_reg.hh:236
gem5::ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:130
gem5::ShowParam
Definition: serialize_handlers.hh:125
gem5::VecRegContainer
Vector Register Abstraction This generic class is the model in a particularization of MVC,...
Definition: vec_reg.hh:123
gem5::ArmISA::b
Bitfield< 7 > b
Definition: misc_types.hh:382
gem5::VecRegContainer::as
VecElem * as()
View interposers.
Definition: vec_reg.hh:189
gem5::X86ISA::count
count
Definition: misc.hh:703
gem5::ArmISA::d
Bitfield< 9 > d
Definition: misc_types.hh:64
gem5::MaxVecRegLenInBytes
constexpr unsigned MaxVecRegLenInBytes
Definition: vec_reg.hh:113
cprintf.hh
gem5::VecRegContainer::container
Container container
Definition: vec_reg.hh:135
gem5::ShowParam< VecRegContainer< Sz > >::show
static void show(std::ostream &os, const VecRegContainer< Sz > &value)
Definition: vec_reg.hh:255
gem5::VegaISA::v
Bitfield< 0 > v
Definition: pagetable.hh:65
gem5::HtmFailureFaultCause::SIZE
@ SIZE
serialize_handlers.hh
gem5::ArmISA::VecElem
uint32_t VecElem
Definition: vec.hh:60
gem5::VecRegContainer< sizeof(DataType) *NumVecElemPerVecReg >::Container
std::array< uint8_t, SIZE > Container
Definition: vec_reg.hh:132
types.hh
gem5::X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:803
gem5::DummyVecRegContainer::as
VecElem * as()
Definition: vec_reg.hh:274
gem5::VecRegContainer::operator!=
bool operator!=(const VecRegContainer< S2 > &that) const
Inequality operator.
Definition: vec_reg.hh:171
gem5::VecRegContainer::zero
void zero()
Zero the container.
Definition: vec_reg.hh:142
logging.hh
gem5::VecRegContainer::as
const VecElem * as() const
Definition: vec_reg.hh:198
gem5::VecRegContainer::VecRegContainer
VecRegContainer()
Definition: vec_reg.hh:138
gem5::DummyVecRegContainer::filler
RegVal filler
Definition: vec_reg.hh:270
gem5::ParseParam
Definition: serialize_handlers.hh:78
fatal_if
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
Definition: logging.hh:226
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::DummyVecRegContainer::operator==
bool operator==(const DummyVecRegContainer &d) const
Definition: vec_reg.hh:271
gem5::VecRegContainer::operator=
VecRegContainer< SIZE > & operator=(const VecRegContainer< SIZE > &that)
Assignment operators.
Definition: vec_reg.hh:148
gem5::VecRegContainer::operator==
bool operator==(const VecRegContainer< S2 > &that) const
Equality operator.
Definition: vec_reg.hh:161
gem5::DummyVecRegContainer
Dummy type aliases and constants for architectures that do not implement vector registers.
Definition: vec_reg.hh:268
gem5::DummyVecRegContainer::operator!=
bool operator!=(const DummyVecRegContainer &d) const
Definition: vec_reg.hh:272

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