gpu_translation_state.hh

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#ifndef __ARCH_AMDGPU_COMMON_GPU_TRANSLATION_STATE_HH__
#define __ARCH_AMDGPU_COMMON_GPU_TRANSLATION_STATE_HH__
 
#include "arch/generic/mmu.hh"
 
namespace gem5
{
 
class ResponsePort;
 
struct GpuTranslationState : public Packet::SenderState
{
    // TLB mode, read or write
    BaseMMU::Mode tlbMode;
    // SE mode thread context associated with this req
    ThreadContext *tc;
    // FS mode related fields
    int deviceId;
    int pasId; // Process Address Space ID
 
    /*
    * TLB entry to be populated and passed back and filled in
    * previous TLBs.  Equivalent to the data cache concept of
    * "data return."
    */
    Serializable *tlbEntry;
    // Is this a TLB prefetch request?
    bool isPrefetch;
    // When was the req for this translation issued
    uint64_t issueTime;
    // Remember where this came from
    std::vector<ResponsePort*>ports;
 
    // keep track of #uncoalesced reqs per packet per TLB level;
    // reqCnt per level >= reqCnt higher level
    std::vector<int> reqCnt;
    // TLB level this packet hit in; 0 if it hit in the page table
    int hitLevel;
    Packet::SenderState *saved;
 
    GpuTranslationState(BaseMMU::Mode tlb_mode, ThreadContext *_tc,
                        bool _prefetch=false,
                        Packet::SenderState *_saved=nullptr)
        : tlbMode(tlb_mode), tc(_tc), deviceId(0), pasId(0), tlbEntry(nullptr),
          isPrefetch(_prefetch), issueTime(0), hitLevel(0), saved(_saved)
    { }
 
    GpuTranslationState(BaseMMU::Mode tlb_mode,
                       bool _prefetch=false,
                       Packet::SenderState *_saved=nullptr)
        : tlbMode(tlb_mode), tc(nullptr), deviceId(0), pasId(0),
          tlbEntry(nullptr), isPrefetch(_prefetch), issueTime(0), hitLevel(0),
          saved(_saved)
    { }
};
 
} // namespace gem5
 
#endif // __ARCH_AMDGPU_COMMON_GPU_TRANSLATION_STATE_HH__