gem5  v22.0.0.2
gpu_translation_state.hh
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31 
32 #ifndef __ARCH_AMDGPU_COMMON_GPU_TRANSLATION_STATE_HH__
33 #define __ARCH_AMDGPU_COMMON_GPU_TRANSLATION_STATE_HH__
34 
35 #include "arch/generic/mmu.hh"
36 
37 namespace gem5
38 {
39 
40 class ResponsePort;
41 
59 {
60  // TLB mode, read or write
62  // SE mode thread context associated with this req
64  // FS mode related fields
65  int deviceId;
66  int pasId; // Process Address Space ID
67 
68  /*
69  * TLB entry to be populated and passed back and filled in
70  * previous TLBs. Equivalent to the data cache concept of
71  * "data return."
72  */
74  // Is this a TLB prefetch request?
75  bool isPrefetch;
76  // When was the req for this translation issued
77  uint64_t issueTime;
78  // Remember where this came from
80 
81  // keep track of #uncoalesced reqs per packet per TLB level;
82  // reqCnt per level >= reqCnt higher level
84  // TLB level this packet hit in; 0 if it hit in the page table
85  int hitLevel;
87 
89  bool _prefetch=false,
90  Packet::SenderState *_saved=nullptr)
91  : tlbMode(tlb_mode), tc(_tc), deviceId(0), pasId(0), tlbEntry(nullptr),
92  isPrefetch(_prefetch), issueTime(0), hitLevel(0), saved(_saved)
93  { }
94 
96  bool _prefetch=false,
97  Packet::SenderState *_saved=nullptr)
98  : tlbMode(tlb_mode), tc(nullptr), deviceId(0), pasId(0),
99  tlbEntry(nullptr), isPrefetch(_prefetch), issueTime(0), hitLevel(0),
100  saved(_saved)
101  { }
102 };
103 
104 } // namespace gem5
105 
106 #endif // __ARCH_AMDGPU_COMMON_GPU_TRANSLATION_STATE_HH__
gem5::GpuTranslationState::deviceId
int deviceId
Definition: gpu_translation_state.hh:65
gem5::GpuTranslationState::pasId
int pasId
Definition: gpu_translation_state.hh:66
gem5::GpuTranslationState::GpuTranslationState
GpuTranslationState(BaseMMU::Mode tlb_mode, ThreadContext *_tc, bool _prefetch=false, Packet::SenderState *_saved=nullptr)
Definition: gpu_translation_state.hh:88
gem5::GpuTranslationState
GPU TranslationState: this currently is a somewhat bastardization of the usage of SenderState,...
Definition: gpu_translation_state.hh:58
gem5::GpuTranslationState::ports
std::vector< ResponsePort * > ports
Definition: gpu_translation_state.hh:79
gem5::BaseMMU::Mode
Mode
Definition: mmu.hh:56
std::vector
STL vector class.
Definition: stl.hh:37
gem5::Serializable
Basic support for object serialization.
Definition: serialize.hh:169
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::GpuTranslationState::issueTime
uint64_t issueTime
Definition: gpu_translation_state.hh:77
mmu.hh
gem5::GpuTranslationState::tlbEntry
Serializable * tlbEntry
Definition: gpu_translation_state.hh:73
gem5::GpuTranslationState::hitLevel
int hitLevel
Definition: gpu_translation_state.hh:85
gem5::Packet::SenderState
A virtual base opaque structure used to hold state associated with the packet (e.g....
Definition: packet.hh:465
gem5::GpuTranslationState::reqCnt
std::vector< int > reqCnt
Definition: gpu_translation_state.hh:83
gem5::GpuTranslationState::saved
Packet::SenderState * saved
Definition: gpu_translation_state.hh:86
gem5::ResponsePort
A ResponsePort is a specialization of a port.
Definition: port.hh:268
gem5::GpuTranslationState::tlbMode
BaseMMU::Mode tlbMode
Definition: gpu_translation_state.hh:61
gem5::GpuTranslationState::isPrefetch
bool isPrefetch
Definition: gpu_translation_state.hh:75
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::GpuTranslationState::GpuTranslationState
GpuTranslationState(BaseMMU::Mode tlb_mode, bool _prefetch=false, Packet::SenderState *_saved=nullptr)
Definition: gpu_translation_state.hh:95
gem5::GpuTranslationState::tc
ThreadContext * tc
Definition: gpu_translation_state.hh:63

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