gem5  v22.0.0.2
Classes | Namespaces | Variables
vec_reg.hh File Reference
#include <array>
#include <cstdint>
#include <iostream>
#include <string>
#include "base/cprintf.hh"
#include "base/logging.hh"
#include "base/types.hh"
#include "sim/serialize_handlers.hh"

Go to the source code of this file.


class  gem5::VecRegContainer< SIZE >
 Vector Register Abstraction This generic class is the model in a particularization of MVC, to vector registers. More...
struct  gem5::ParseParam< VecRegContainer< Sz > >
 Calls required for serialization/deserialization. More...
struct  gem5::ShowParam< VecRegContainer< Sz > >
struct  gem5::DummyVecRegContainer
 Dummy type aliases and constants for architectures that do not implement vector registers. More...
struct  gem5::ParseParam< DummyVecRegContainer >


 Reference material can be found at the JEDEC website: UFS standard UFS HCI specification


static std::ostream & gem5::operator<< (std::ostream &os, const DummyVecRegContainer &d)
static std::ostream & gem5::operator<< (std::ostream &os, const DummyVecRegContainer &d)


constexpr unsigned gem5::MaxVecRegLenInBytes = 4096

Detailed Description

Vector Registers layout specification.

This register type is to be used to model the SIMD registers. It takes into account the possibility that different architectural names may overlap (like for ARMv8 AArch32 for example).

The design is having a basic vector register container that holds the bytes, unaware of anything else. This is implemented by VecRegContainer. As the (maximum) length of the physical vector register is a compile-time constant, it is defined as a template parameter.

This file also describe one view of the container that has semantic information about the bytes, the VecRegT. A VecRegT is a view of a VecRegContainer (by reference). The VecRegT has a type (VecElem) to which bytes are casted, and the amount of such elements that the vector contains (NumElems). The size of a view, calculated as sizeof(VecElem) * NumElems must match the size of the underlying container. As VecRegT has some degree of type information it has vector semantics, and defines the index operator ([]) to get references to particular bytes understood as a VecElem.

The intended usage is requesting views to the VecRegContainer via the member 'as' for VecRegT.

// We declare 512 bits vectors using Vec512 = VecRegContainer<64>; ... // We implement the physical vector register file Vec512 physicalVecRegFile[NUM_VREGS]; ... // Usage example, for a macro op: VecFloat8Add(ExecContext* xd) { // Request source vector register to the execution context. Vec512 vsrc1raw; xc->getRegOperand(this, 0, &vsrc1raw); // View it as a vector of floats (we could just specify the first // template parametre, the second has a default value that works, and the // last one is derived by the constness of vsrc1raw). VecRegT<float, 8, true>& vsrc1 = vsrc1raw->as<float, 8>();

// Second source and view Vec512 vsrc2raw; xc->getRegOperand(this, 1, &vsrc2raw); VecRegT<float, 8, true>& vsrc2 = vsrc2raw->as<float, 8>();

// Destination and view Vec512 vdstraw; VecRegT<float, 8, false>& vdst = vdstraw->as<float, 8>();

for (auto i = 0; i < 8; i++) { // This asignment sets the bits in the underlying Vec512: vdstraw vdst[i] = vsrc1[i] + vsrc2[i]; } xc->setWriteRegOperand(this, 0, vdstraw); }

Definition in file vec_reg.hh.

Generated on Thu Jul 28 2022 13:32:44 for gem5 by doxygen 1.8.17