vector.hh File Reference

#include <cstdint>
#include <string>
#include <vector>
#include "arch/generic/vec_pred_reg.hh"
#include "arch/generic/vec_reg.hh"
#include "arch/riscv/types.hh"
#include "base/bitunion.hh"
#include "cpu/reg_class.hh"
#include "debug/VecRegs.hh"

Go to the source code of this file.

Namespaces
namespace	gem5
	Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
namespace	gem5::RiscvISA

Typedefs
using	gem5::RiscvISA::VecRegContainer = gem5::VecRegContainer<MaxVecLenInBytes>
using	gem5::RiscvISA::vreg_t = VecRegContainer

Functions
	gem5::RiscvISA::BitUnion64 (VTYPE) Bitfield< 63 > vill

Variables
const int	gem5::RiscvISA::NumVecStandardRegs = 32
const int	gem5::RiscvISA::NumVecInternalRegs = 8
const int	gem5::RiscvISA::NumVecRegs = NumVecStandardRegs + NumVecInternalRegs
const std::vector< std::string >	gem5::RiscvISA::VecRegNames
const int	gem5::RiscvISA::VecMemInternalReg0 = NumVecStandardRegs
static TypedRegClassOps< RiscvISA::VecRegContainer >	gem5::RiscvISA::vecRegClassOps
constexpr RegClass	gem5::RiscvISA::vecRegClass
Bitfield< 7, 0 >	gem5::RiscvISA::vtype8
Bitfield< 7 >	gem5::RiscvISA::vma
Bitfield< 6 >	gem5::RiscvISA::vta
Bitfield< 5, 3 >	gem5::RiscvISA::vsew
Bitfield< 2, 0 >	gem5::RiscvISA::vlmul