gem5  v22.0.0.2
reg_abi.cc
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27 
28 #include "arch/riscv/reg_abi.hh"
29 
30 namespace gem5
31 {
32 
33 namespace RiscvISA
34 {
35 
36 const std::vector<int> RegABI64::ArgumentRegs = {10, 11, 12, 13, 14, 15, 16};
37 
38 } // namespace RiscvISA
39 } // namespace gem5
reg_abi.hh
gem5::RiscvISA::RegABI64::ArgumentRegs
static const std::vector< int > ArgumentRegs
Definition: reg_abi.hh:44
std::vector< int >
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37

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