gem5
v24.0.0.0
Loading...
Searching...
No Matches
arch
riscv
reg_abi.cc
Go to the documentation of this file.
1
/*
2
* Copyright 2020 Google Inc.
3
*
4
* Redistribution and use in source and binary forms, with or without
5
* modification, are permitted provided that the following conditions are
6
* met: redistributions of source code must retain the above copyright
7
* notice, this list of conditions and the following disclaimer;
8
* redistributions in binary form must reproduce the above copyright
9
* notice, this list of conditions and the following disclaimer in the
10
* documentation and/or other materials provided with the distribution;
11
* neither the name of the copyright holders nor the names of its
12
* contributors may be used to endorse or promote products derived from
13
* this software without specific prior written permission.
14
*
15
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26
*/
27
28
#include "
arch/riscv/reg_abi.hh
"
29
#include "
arch/riscv/regs/int.hh
"
30
31
namespace
gem5
32
{
33
34
namespace
RiscvISA
35
{
36
37
const
std::vector<RegId>
RegABI64::ArgumentRegs
= {
38
int_reg::A0
,
int_reg::A1
,
int_reg::A2
,
int_reg::A3
,
39
int_reg::A4
,
int_reg::A5
,
int_reg::A6
40
};
41
42
const
std::vector<RegId>
RegABI32::ArgumentRegs
= {
43
int_reg::A0
,
int_reg::A1
,
int_reg::A2
,
int_reg::A3
,
44
int_reg::A4
,
int_reg::A5
,
int_reg::A6
45
};
46
47
48
}
// namespace RiscvISA
49
}
// namespace gem5
std::vector
STL vector class.
Definition
stl.hh:37
gem5::RiscvISA::int_reg::A1
constexpr RegId A1
Definition
int.hh:102
gem5::RiscvISA::int_reg::A3
constexpr RegId A3
Definition
int.hh:104
gem5::RiscvISA::int_reg::A0
constexpr RegId A0
Definition
int.hh:101
gem5::RiscvISA::int_reg::A2
constexpr RegId A2
Definition
int.hh:103
gem5::RiscvISA::int_reg::A6
constexpr RegId A6
Definition
int.hh:107
gem5::RiscvISA::int_reg::A4
constexpr RegId A4
Definition
int.hh:105
gem5::RiscvISA::int_reg::A5
constexpr RegId A5
Definition
int.hh:106
gem5
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition
binary32.hh:36
reg_abi.hh
int.hh
gem5::RiscvISA::RegABI32::ArgumentRegs
static const std::vector< RegId > ArgumentRegs
Definition
reg_abi.hh:49
gem5::RiscvISA::RegABI64::ArgumentRegs
static const std::vector< RegId > ArgumentRegs
Definition
reg_abi.hh:44
Generated on Tue Jun 18 2024 16:23:57 for gem5 by
doxygen
1.11.0