gem5
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arch
riscv
reg_abi.cc
Go to the documentation of this file.
1
/*
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* Copyright 2020 Google Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "
arch/riscv/reg_abi.hh
"
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#include "
arch/riscv/regs/int.hh
"
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namespace
gem5
32
{
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34
namespace
RiscvISA
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{
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const
std::vector<RegId>
RegABI64::ArgumentRegs
= {
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int_reg::A0
,
int_reg::A1
,
int_reg::A2
,
int_reg::A3
,
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int_reg::A4
,
int_reg::A5
,
int_reg::A6
40
};
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const
std::vector<RegId>
RegABI32::ArgumentRegs
= {
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int_reg::A0
,
int_reg::A1
,
int_reg::A2
,
int_reg::A3
,
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int_reg::A4
,
int_reg::A5
,
int_reg::A6
45
};
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}
// namespace RiscvISA
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}
// namespace gem5
std::vector
STL vector class.
Definition
stl.hh:37
gem5::RiscvISA::int_reg::A1
constexpr RegId A1
Definition
int.hh:102
gem5::RiscvISA::int_reg::A3
constexpr RegId A3
Definition
int.hh:104
gem5::RiscvISA::int_reg::A0
constexpr RegId A0
Definition
int.hh:101
gem5::RiscvISA::int_reg::A2
constexpr RegId A2
Definition
int.hh:103
gem5::RiscvISA::int_reg::A6
constexpr RegId A6
Definition
int.hh:107
gem5::RiscvISA::int_reg::A4
constexpr RegId A4
Definition
int.hh:105
gem5::RiscvISA::int_reg::A5
constexpr RegId A5
Definition
int.hh:106
gem5
Copyright (c) 2024 Arm Limited All rights reserved.
Definition
binary32.hh:36
reg_abi.hh
int.hh
gem5::RiscvISA::RegABI32::ArgumentRegs
static const std::vector< RegId > ArgumentRegs
Definition
reg_abi.hh:49
gem5::RiscvISA::RegABI64::ArgumentRegs
static const std::vector< RegId > ArgumentRegs
Definition
reg_abi.hh:44
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