gem5  v21.2.0.0
reg_abi.hh
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27 
28 #ifndef __ARCH_RISCV_REG_ABI_HH__
29 #define __ARCH_RISCV_REG_ABI_HH__
30 
31 #include <vector>
32 
33 #include "sim/syscall_abi.hh"
34 
35 namespace gem5
36 {
37 
38 namespace RiscvISA
39 {
40 
41 //FIXME RISCV needs to handle 64 bit arguments in its 32 bit ISA.
43 {
45 };
46 
47 } // namespace RiscvISA
48 } // namespace gem5
49 
50 #endif // __ARCH_RISCV_REG_ABI_HH__
gem5::RiscvISA::RegABI64::ArgumentRegs
static const std::vector< int > ArgumentRegs
Definition: reg_abi.hh:44
gem5::GenericSyscallABI64
Definition: syscall_abi.hh:47
std::vector< int >
syscall_abi.hh
gem5::RiscvISA::RegABI64
Definition: reg_abi.hh:42
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60

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