gem5 v24.0.0.0
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gem5::RiscvISA::int_reg Namespace Reference

Enumerations

enum  : RegIndex {
  _ZeroIdx , _RaIdx , _SpIdx , _GpIdx ,
  _TpIdx , _T0Idx , _T1Idx , _T2Idx ,
  _S0Idx , _S1Idx , _A0Idx , _A1Idx ,
  _A2Idx , _A3Idx , _A4Idx , _A5Idx ,
  _A6Idx , _A7Idx , _S2Idx , _S3Idx ,
  _S4Idx , _S5Idx , _S6Idx , _S7Idx ,
  _S8Idx , _S9Idx , _S10Idx , _S11Idx ,
  _T3Idx , _T4Idx , _T5Idx , _T6Idx ,
  NumArchRegs , _Ureg0Idx = NumArchRegs , NumRegs
}
 

Variables

constexpr RegId Zero = intRegClass[_ZeroIdx]
 
constexpr RegId Ra = intRegClass[_RaIdx]
 
constexpr RegId Sp = intRegClass[_SpIdx]
 
constexpr RegId Gp = intRegClass[_GpIdx]
 
constexpr RegId Tp = intRegClass[_TpIdx]
 
constexpr RegId T0 = intRegClass[_T0Idx]
 
constexpr RegId T1 = intRegClass[_T1Idx]
 
constexpr RegId T2 = intRegClass[_T2Idx]
 
constexpr RegId S0 = intRegClass[_S0Idx]
 
constexpr RegId S1 = intRegClass[_S1Idx]
 
constexpr RegId A0 = intRegClass[_A0Idx]
 
constexpr RegId A1 = intRegClass[_A1Idx]
 
constexpr RegId A2 = intRegClass[_A2Idx]
 
constexpr RegId A3 = intRegClass[_A3Idx]
 
constexpr RegId A4 = intRegClass[_A4Idx]
 
constexpr RegId A5 = intRegClass[_A5Idx]
 
constexpr RegId A6 = intRegClass[_A6Idx]
 
constexpr RegId A7 = intRegClass[_A7Idx]
 
constexpr RegId S2 = intRegClass[_S2Idx]
 
constexpr RegId S3 = intRegClass[_S3Idx]
 
constexpr RegId S4 = intRegClass[_S4Idx]
 
constexpr RegId S5 = intRegClass[_S5Idx]
 
constexpr RegId S6 = intRegClass[_S6Idx]
 
constexpr RegId S7 = intRegClass[_S7Idx]
 
constexpr RegId S8 = intRegClass[_S8Idx]
 
constexpr RegId S9 = intRegClass[_S9Idx]
 
constexpr RegId S10 = intRegClass[_S10Idx]
 
constexpr RegId S11 = intRegClass[_S11Idx]
 
constexpr RegId T3 = intRegClass[_T3Idx]
 
constexpr RegId T4 = intRegClass[_T4Idx]
 
constexpr RegId T5 = intRegClass[_T5Idx]
 
constexpr RegId T6 = intRegClass[_T6Idx]
 
constexpr RegId Ureg0 = intRegClass[_Ureg0Idx]
 
const std::vector< std::string > RegNames
 

Enumeration Type Documentation

◆ anonymous enum

anonymous enum : RegIndex
Enumerator
_ZeroIdx 
_RaIdx 
_SpIdx 
_GpIdx 
_TpIdx 
_T0Idx 
_T1Idx 
_T2Idx 
_S0Idx 
_S1Idx 
_A0Idx 
_A1Idx 
_A2Idx 
_A3Idx 
_A4Idx 
_A5Idx 
_A6Idx 
_A7Idx 
_S2Idx 
_S3Idx 
_S4Idx 
_S5Idx 
_S6Idx 
_S7Idx 
_S8Idx 
_S9Idx 
_S10Idx 
_S11Idx 
_T3Idx 
_T4Idx 
_T5Idx 
_T6Idx 
NumArchRegs 
_Ureg0Idx 
NumRegs 

Definition at line 64 of file int.hh.

Variable Documentation

◆ A0

RegId gem5::RiscvISA::int_reg::A0 = intRegClass[_A0Idx]

Definition at line 101 of file int.hh.

Referenced by gem5::RiscvSemihosting::call32(), and gem5::RiscvSemihosting::call64().

◆ A1

RegId gem5::RiscvISA::int_reg::A1 = intRegClass[_A1Idx]

◆ A2

RegId gem5::RiscvISA::int_reg::A2 = intRegClass[_A2Idx]

Definition at line 103 of file int.hh.

◆ A3

RegId gem5::RiscvISA::int_reg::A3 = intRegClass[_A3Idx]

Definition at line 104 of file int.hh.

◆ A4

RegId gem5::RiscvISA::int_reg::A4 = intRegClass[_A4Idx]

Definition at line 105 of file int.hh.

◆ A5

RegId gem5::RiscvISA::int_reg::A5 = intRegClass[_A5Idx]

Definition at line 106 of file int.hh.

◆ A6

RegId gem5::RiscvISA::int_reg::A6 = intRegClass[_A6Idx]

Definition at line 107 of file int.hh.

◆ A7

RegId gem5::RiscvISA::int_reg::A7 = intRegClass[_A7Idx]

Definition at line 108 of file int.hh.

◆ Gp

RegId gem5::RiscvISA::int_reg::Gp = intRegClass[_GpIdx]

Definition at line 94 of file int.hh.

◆ Ra

RegId gem5::RiscvISA::int_reg::Ra = intRegClass[_RaIdx]

Definition at line 92 of file int.hh.

◆ RegNames

const std::vector<std::string> gem5::RiscvISA::int_reg::RegNames
Initial value:
= {
"zero", "ra", "sp", "gp",
"tp", "t0", "t1", "t2",
"s0", "s1", "a0", "a1",
"a2", "a3", "a4", "a5",
"a6", "a7", "s2", "s3",
"s4", "s5", "s6", "s7",
"s8", "s9", "s10", "s11",
"t3", "t4", "t5", "t6"
}

Definition at line 125 of file int.hh.

Referenced by gem5::RiscvISA::registerName().

◆ S0

RegId gem5::RiscvISA::int_reg::S0 = intRegClass[_S0Idx]

Definition at line 99 of file int.hh.

◆ S1

RegId gem5::RiscvISA::int_reg::S1 = intRegClass[_S1Idx]

Definition at line 100 of file int.hh.

◆ S10

RegId gem5::RiscvISA::int_reg::S10 = intRegClass[_S10Idx]

Definition at line 117 of file int.hh.

◆ S11

RegId gem5::RiscvISA::int_reg::S11 = intRegClass[_S11Idx]

Definition at line 118 of file int.hh.

◆ S2

RegId gem5::RiscvISA::int_reg::S2 = intRegClass[_S2Idx]

Definition at line 109 of file int.hh.

◆ S3

RegId gem5::RiscvISA::int_reg::S3 = intRegClass[_S3Idx]

Definition at line 110 of file int.hh.

◆ S4

RegId gem5::RiscvISA::int_reg::S4 = intRegClass[_S4Idx]

Definition at line 111 of file int.hh.

◆ S5

RegId gem5::RiscvISA::int_reg::S5 = intRegClass[_S5Idx]

Definition at line 112 of file int.hh.

◆ S6

RegId gem5::RiscvISA::int_reg::S6 = intRegClass[_S6Idx]

Definition at line 113 of file int.hh.

◆ S7

RegId gem5::RiscvISA::int_reg::S7 = intRegClass[_S7Idx]

Definition at line 114 of file int.hh.

◆ S8

RegId gem5::RiscvISA::int_reg::S8 = intRegClass[_S8Idx]

Definition at line 115 of file int.hh.

◆ S9

RegId gem5::RiscvISA::int_reg::S9 = intRegClass[_S9Idx]

Definition at line 116 of file int.hh.

◆ Sp

RegId gem5::RiscvISA::int_reg::Sp = intRegClass[_SpIdx]

Definition at line 93 of file int.hh.

◆ T0

RegId gem5::RiscvISA::int_reg::T0 = intRegClass[_T0Idx]

Definition at line 96 of file int.hh.

◆ T1

RegId gem5::RiscvISA::int_reg::T1 = intRegClass[_T1Idx]

Definition at line 97 of file int.hh.

◆ T2

RegId gem5::RiscvISA::int_reg::T2 = intRegClass[_T2Idx]

Definition at line 98 of file int.hh.

◆ T3

RegId gem5::RiscvISA::int_reg::T3 = intRegClass[_T3Idx]

Definition at line 119 of file int.hh.

◆ T4

RegId gem5::RiscvISA::int_reg::T4 = intRegClass[_T4Idx]

Definition at line 120 of file int.hh.

◆ T5

RegId gem5::RiscvISA::int_reg::T5 = intRegClass[_T5Idx]

Definition at line 121 of file int.hh.

◆ T6

RegId gem5::RiscvISA::int_reg::T6 = intRegClass[_T6Idx]

Definition at line 122 of file int.hh.

◆ Tp

RegId gem5::RiscvISA::int_reg::Tp = intRegClass[_TpIdx]

Definition at line 95 of file int.hh.

◆ Ureg0

RegId gem5::RiscvISA::int_reg::Ureg0 = intRegClass[_Ureg0Idx]

Definition at line 123 of file int.hh.

◆ Zero

RegId gem5::RiscvISA::int_reg::Zero = intRegClass[_ZeroIdx]
inlineconstexpr

Definition at line 91 of file int.hh.


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