gem5 v24.0.0.0
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Enumerations | |
enum | : RegIndex { _ZeroIdx , _RaIdx , _SpIdx , _GpIdx , _TpIdx , _T0Idx , _T1Idx , _T2Idx , _S0Idx , _S1Idx , _A0Idx , _A1Idx , _A2Idx , _A3Idx , _A4Idx , _A5Idx , _A6Idx , _A7Idx , _S2Idx , _S3Idx , _S4Idx , _S5Idx , _S6Idx , _S7Idx , _S8Idx , _S9Idx , _S10Idx , _S11Idx , _T3Idx , _T4Idx , _T5Idx , _T6Idx , NumArchRegs , _Ureg0Idx = NumArchRegs , NumRegs } |
anonymous enum : RegIndex |
RegId gem5::RiscvISA::int_reg::A0 = intRegClass[_A0Idx] |
Definition at line 101 of file int.hh.
Referenced by gem5::RiscvSemihosting::call32(), and gem5::RiscvSemihosting::call64().
RegId gem5::RiscvISA::int_reg::A1 = intRegClass[_A1Idx] |
Definition at line 102 of file int.hh.
Referenced by gem5::RiscvISA::FsLinux::initState(), and gem5::RiscvISA::BootloaderKernelWorkload::loadDtb().
RegId gem5::RiscvISA::int_reg::A2 = intRegClass[_A2Idx] |
RegId gem5::RiscvISA::int_reg::A3 = intRegClass[_A3Idx] |
RegId gem5::RiscvISA::int_reg::A4 = intRegClass[_A4Idx] |
RegId gem5::RiscvISA::int_reg::A5 = intRegClass[_A5Idx] |
RegId gem5::RiscvISA::int_reg::A6 = intRegClass[_A6Idx] |
RegId gem5::RiscvISA::int_reg::A7 = intRegClass[_A7Idx] |
RegId gem5::RiscvISA::int_reg::Gp = intRegClass[_GpIdx] |
RegId gem5::RiscvISA::int_reg::Ra = intRegClass[_RaIdx] |
const std::vector<std::string> gem5::RiscvISA::int_reg::RegNames |
Definition at line 125 of file int.hh.
Referenced by gem5::RiscvISA::registerName().
RegId gem5::RiscvISA::int_reg::S0 = intRegClass[_S0Idx] |
RegId gem5::RiscvISA::int_reg::S1 = intRegClass[_S1Idx] |
RegId gem5::RiscvISA::int_reg::S10 = intRegClass[_S10Idx] |
RegId gem5::RiscvISA::int_reg::S11 = intRegClass[_S11Idx] |
RegId gem5::RiscvISA::int_reg::S2 = intRegClass[_S2Idx] |
RegId gem5::RiscvISA::int_reg::S3 = intRegClass[_S3Idx] |
RegId gem5::RiscvISA::int_reg::S4 = intRegClass[_S4Idx] |
RegId gem5::RiscvISA::int_reg::S5 = intRegClass[_S5Idx] |
RegId gem5::RiscvISA::int_reg::S6 = intRegClass[_S6Idx] |
RegId gem5::RiscvISA::int_reg::S7 = intRegClass[_S7Idx] |
RegId gem5::RiscvISA::int_reg::S8 = intRegClass[_S8Idx] |
RegId gem5::RiscvISA::int_reg::S9 = intRegClass[_S9Idx] |
RegId gem5::RiscvISA::int_reg::Sp = intRegClass[_SpIdx] |
RegId gem5::RiscvISA::int_reg::T0 = intRegClass[_T0Idx] |
RegId gem5::RiscvISA::int_reg::T1 = intRegClass[_T1Idx] |
RegId gem5::RiscvISA::int_reg::T2 = intRegClass[_T2Idx] |
RegId gem5::RiscvISA::int_reg::T3 = intRegClass[_T3Idx] |
RegId gem5::RiscvISA::int_reg::T4 = intRegClass[_T4Idx] |
RegId gem5::RiscvISA::int_reg::T5 = intRegClass[_T5Idx] |
RegId gem5::RiscvISA::int_reg::T6 = intRegClass[_T6Idx] |
RegId gem5::RiscvISA::int_reg::Tp = intRegClass[_TpIdx] |
RegId gem5::RiscvISA::int_reg::Ureg0 = intRegClass[_Ureg0Idx] |
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inlineconstexpr |