gem5  v21.1.0.2
serial_link.hh
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41 
48 #ifndef __MEM_SERIAL_LINK_HH__
49 #define __MEM_SERIAL_LINK_HH__
50 
51 #include <deque>
52 
53 #include "base/types.hh"
54 #include "mem/port.hh"
55 #include "params/SerialLink.hh"
56 #include "sim/clocked_object.hh"
57 
58 namespace gem5
59 {
60 
68 class SerialLink : public ClockedObject
69 {
70  protected:
71 
77  {
78 
79  public:
80 
81  const Tick tick;
82  const PacketPtr pkt;
83 
84  DeferredPacket(PacketPtr _pkt, Tick _tick) : tick(_tick), pkt(_pkt)
85  { }
86  };
87 
88  // Forward declaration to allow the CPU-side port to have a pointer
89  class SerialLinkRequestPort;
90 
98  {
99 
100  private:
101 
104 
109 
111  const Cycles delay;
112 
115 
123 
125  unsigned int outstandingResponses;
126 
128  bool retryReq;
129 
131  unsigned int respQueueLimit;
132 
138  bool respQueueFull() const;
139 
145  void trySendTiming();
146 
149 
150  public:
151 
163  SerialLinkResponsePort(const std::string& _name, SerialLink&
164  _serial_link, SerialLinkRequestPort& _mem_side_port,
165  Cycles _delay, int _resp_limit, const
166  std::vector<AddrRange>& _ranges);
167 
175  void schedTimingResp(PacketPtr pkt, Tick when);
176 
182  void retryStalledReq();
183 
184  protected:
185 
188  bool recvTimingReq(PacketPtr pkt);
189 
192  void recvRespRetry();
193 
197 
200  void recvFunctional(PacketPtr pkt);
201 
205  };
206 
207 
214  {
215 
216  private:
217 
220 
226 
228  const Cycles delay;
229 
237 
239  const unsigned int reqQueueLimit;
240 
246  void trySendTiming();
247 
250 
251  public:
252 
263  SerialLinkRequestPort(const std::string& _name, SerialLink&
264  _serial_link, SerialLinkResponsePort& _cpu_side_port,
265  Cycles _delay, int _req_limit);
266 
272  bool reqQueueFull() const;
273 
281  void schedTimingReq(PacketPtr pkt, Tick when);
282 
292 
293  protected:
294 
297  bool recvTimingResp(PacketPtr pkt);
298 
301  void recvReqRetry();
302  };
303 
306 
309 
311  unsigned num_lanes;
312 
314  uint64_t link_speed;
315 
316  public:
317 
318  Port &getPort(const std::string &if_name,
319  PortID idx=InvalidPortID);
320 
321  virtual void init();
322 
323  typedef SerialLinkParams Params;
324 
325  SerialLink(const SerialLinkParams &p);
326 };
327 
328 } // namespace gem5
329 
330 #endif //__MEM_SERIAL_LINK_HH__
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:252
std::vector
STL vector class.
Definition: stl.hh:37
gem5::InvalidPortID
const PortID InvalidPortID
Definition: types.hh:253
gem5::RequestPort
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition: port.hh:77
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
port.hh
gem5::ClockedObject
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
Definition: clocked_object.hh:234
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
gem5::ResponsePort
A ResponsePort is a specialization of a port.
Definition: port.hh:268
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
types.hh
clocked_object.hh
std::deque
STL deque class.
Definition: stl.hh:44
std::list< AddrRange >
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::Named::_name
const std::string _name
Definition: named.hh:41

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