gem5  v21.1.0.2
simple_cache.hh
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28 
29 #ifndef __LEARNING_GEM5_SIMPLE_CACHE_SIMPLE_CACHE_HH__
30 #define __LEARNING_GEM5_SIMPLE_CACHE_SIMPLE_CACHE_HH__
31 
32 #include <unordered_map>
33 
34 #include "base/statistics.hh"
35 #include "mem/port.hh"
36 #include "params/SimpleCache.hh"
37 #include "sim/clocked_object.hh"
38 
39 namespace gem5
40 {
41 
49 class SimpleCache : public ClockedObject
50 {
51  private:
52 
57  class CPUSidePort : public ResponsePort
58  {
59  private:
61  int id;
62 
65 
67  bool needRetry;
68 
71 
72  public:
76  CPUSidePort(const std::string& name, int id, SimpleCache *owner) :
78  blockedPacket(nullptr)
79  { }
80 
88  void sendPacket(PacketPtr pkt);
89 
97  AddrRangeList getAddrRanges() const override;
98 
103  void trySendRetry();
104 
105  protected:
110  Tick recvAtomic(PacketPtr pkt) override
111  { panic("recvAtomic unimpl."); }
112 
119  void recvFunctional(PacketPtr pkt) override;
120 
129  bool recvTimingReq(PacketPtr pkt) override;
130 
136  void recvRespRetry() override;
137  };
138 
143  class MemSidePort : public RequestPort
144  {
145  private:
148 
151 
152  public:
156  MemSidePort(const std::string& name, SimpleCache *owner) :
158  { }
159 
167  void sendPacket(PacketPtr pkt);
168 
169  protected:
173  bool recvTimingResp(PacketPtr pkt) override;
174 
180  void recvReqRetry() override;
181 
189  void recvRangeChange() override;
190  };
191 
201  bool handleRequest(PacketPtr pkt, int port_id);
202 
211  bool handleResponse(PacketPtr pkt);
212 
221  void sendResponse(PacketPtr pkt);
222 
229  void handleFunctional(PacketPtr pkt);
230 
235  void accessTiming(PacketPtr pkt);
236 
243  bool accessFunctional(PacketPtr pkt);
244 
251  void insert(PacketPtr pkt);
252 
260 
264  void sendRangeChange() const;
265 
268 
270  const unsigned blockSize;
271 
273  const unsigned capacity;
274 
277 
280 
282  bool blocked;
283 
287 
290 
293 
295  std::unordered_map<Addr, uint8_t*> cacheStore;
296 
298  protected:
300  {
306  } stats;
307 
308  public:
309 
312  SimpleCache(const SimpleCacheParams &params);
313 
324  Port &getPort(const std::string &if_name,
325  PortID idx=InvalidPortID) override;
326 
327 };
328 
329 } // namespace gem5
330 
331 #endif // __LEARNING_GEM5_SIMPLE_CACHE_SIMPLE_CACHE_HH__
gem5::statistics::Scalar
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:1927
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:252
gem5::SimpleCache::handleRequest
bool handleRequest(PacketPtr pkt, int port_id)
Handle the request from the CPU side.
Definition: simple_cache.cc:194
gem5::SimpleCache::SimpleCacheStats::missLatency
statistics::Histogram missLatency
Definition: simple_cache.hh:304
gem5::Port::name
const std::string name() const
Return port name (for DPRINTF).
Definition: port.hh:111
gem5::SimpleCache::CPUSidePort::recvFunctional
void recvFunctional(PacketPtr pkt) override
Receive a functional request packet from the request port.
Definition: simple_cache.cc:106
gem5::SimpleCache::waitingPortId
int waitingPortId
The port to send the response when we recieve it back.
Definition: simple_cache.hh:289
gem5::SimpleCache::MemSidePort::blockedPacket
PacketPtr blockedPacket
If we tried to send a packet and it was blocked, store it here.
Definition: simple_cache.hh:150
gem5::SimpleCache
A very simple cache object.
Definition: simple_cache.hh:49
gem5::SimpleCache::CPUSidePort::recvAtomic
Tick recvAtomic(PacketPtr pkt) override
Receive an atomic request packet from the request port.
Definition: simple_cache.hh:110
gem5::SimpleCache::sendRangeChange
void sendRangeChange() const
Tell the CPU side to ask for our memory ranges.
Definition: simple_cache.cc:421
gem5::SimpleCache::MemSidePort::recvTimingResp
bool recvTimingResp(PacketPtr pkt) override
Receive a timing response from the response port.
Definition: simple_cache.cc:167
gem5::SimpleCache::CPUSidePort::recvRespRetry
void recvRespRetry() override
Called by the request port if sendTimingResp was called on this response port (causing recvTimingResp...
Definition: simple_cache.cc:136
gem5::statistics::Formula
A formula for statistics that is calculated when printed.
Definition: statistics.hh:2536
std::vector
STL vector class.
Definition: stl.hh:37
gem5::SimpleCache::accessFunctional
bool accessFunctional(PacketPtr pkt)
This is where we actually update / read from the cache.
Definition: simple_cache.cc:342
gem5::InvalidPortID
const PortID InvalidPortID
Definition: types.hh:253
gem5::SimpleCache::sendResponse
void sendResponse(PacketPtr pkt)
Send the packet to the CPU side.
Definition: simple_cache.cc:249
gem5::SimpleCache::handleResponse
bool handleResponse(PacketPtr pkt)
Handle the respone from the memory side.
Definition: simple_cache.cc:219
gem5::RequestPort
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition: port.hh:77
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::SimpleCache::SimpleCacheStats::hitRatio
statistics::Formula hitRatio
Definition: simple_cache.hh:305
gem5::SimpleCache::SimpleCacheStats::hits
statistics::Scalar hits
Definition: simple_cache.hh:302
gem5::SimpleCache::MemSidePort
Port on the memory-side that receives responses.
Definition: simple_cache.hh:143
gem5::SimpleCache::blockSize
const unsigned blockSize
The block size for the cache.
Definition: simple_cache.hh:270
gem5::statistics::Histogram
A simple histogram stat.
Definition: statistics.hh:2123
gem5::SimpleCache::CPUSidePort::CPUSidePort
CPUSidePort(const std::string &name, int id, SimpleCache *owner)
Constructor.
Definition: simple_cache.hh:76
gem5::SimpleCache::memPort
MemSidePort memPort
Instantiation of the memory-side port.
Definition: simple_cache.hh:279
gem5::SimpleCache::CPUSidePort::id
int id
Since this is a vector port, need to know what number this one is.
Definition: simple_cache.hh:61
gem5::SimpleCache::CPUSidePort::needRetry
bool needRetry
True if the port needs to send a retry req.
Definition: simple_cache.hh:67
gem5::SimpleCache::SimpleCacheStats::misses
statistics::Scalar misses
Definition: simple_cache.hh:303
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
gem5::SimpleCache::CPUSidePort::trySendRetry
void trySendRetry()
Send a retry to the peer port only if it is needed.
Definition: simple_cache.cc:95
gem5::SimpleCache::stats
gem5::SimpleCache::SimpleCacheStats stats
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
statistics.hh
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::SimpleCache::cpuPorts
std::vector< CPUSidePort > cpuPorts
Instantiation of the CPU-side port.
Definition: simple_cache.hh:276
gem5::SimpleCache::originalPacket
PacketPtr originalPacket
Packet that we are currently handling.
Definition: simple_cache.hh:286
port.hh
gem5::SimpleCache::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: simple_cache.cc:57
gem5::SimpleCache::MemSidePort::MemSidePort
MemSidePort(const std::string &name, SimpleCache *owner)
Constructor.
Definition: simple_cache.hh:156
gem5::SimpleCache::CPUSidePort::blockedPacket
PacketPtr blockedPacket
If we tried to send a packet and it was blocked, store it here.
Definition: simple_cache.hh:70
gem5::ClockedObject
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
Definition: clocked_object.hh:234
gem5::SimpleCache::handleFunctional
void handleFunctional(PacketPtr pkt)
Handle a packet functionally.
Definition: simple_cache.cc:274
gem5::SimpleCache::CPUSidePort::recvTimingReq
bool recvTimingReq(PacketPtr pkt) override
Receive a timing request from the request port.
Definition: simple_cache.cc:113
gem5::SimpleCache::CPUSidePort::getAddrRanges
AddrRangeList getAddrRanges() const override
Get a list of the non-overlapping address ranges the owner is responsible for.
Definition: simple_cache.cc:89
gem5::ResponsePort
A ResponsePort is a specialization of a port.
Definition: port.hh:268
gem5::SimpleCache::CPUSidePort
Port on the CPU-side that receives requests.
Definition: simple_cache.hh:57
gem5::SimpleCache::capacity
const unsigned capacity
Number of blocks in the cache (size of cache / block size)
Definition: simple_cache.hh:273
gem5::SimpleCache::missTime
Tick missTime
For tracking the miss latency.
Definition: simple_cache.hh:292
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::SimpleCache::SimpleCache
SimpleCache(const SimpleCacheParams &params)
constructor
Definition: simple_cache.cc:39
gem5::SimpleCache::SimpleCacheStats::SimpleCacheStats
SimpleCacheStats(statistics::Group *parent)
Definition: simple_cache.cc:428
clocked_object.hh
gem5::SimpleCache::MemSidePort::recvReqRetry
void recvReqRetry() override
Called by the response port if sendTimingReq was called on this request port (causing recvTimingReq t...
Definition: simple_cache.cc:174
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::SimpleCache::MemSidePort::sendPacket
void sendPacket(PacketPtr pkt)
Send a packet across this port.
Definition: simple_cache.cc:154
gem5::SimpleCache::latency
const Cycles latency
Latency to check the cache. Number of cycles for both hit and miss.
Definition: simple_cache.hh:267
gem5::SimpleCache::CPUSidePort::sendPacket
void sendPacket(PacketPtr pkt)
Send a packet across this port.
Definition: simple_cache.cc:74
gem5::SimpleCache::MemSidePort::recvRangeChange
void recvRangeChange() override
Called to receive an address range change from the peer response port.
Definition: simple_cache.cc:188
gem5::SimpleCache::cacheStore
std::unordered_map< Addr, uint8_t * > cacheStore
An incredibly simple cache storage. Maps block addresses to data.
Definition: simple_cache.hh:295
std::list< AddrRange >
gem5::SimpleCache::SimpleCacheStats
Cache statistics.
Definition: simple_cache.hh:299
gem5::SimpleCache::MemSidePort::owner
SimpleCache * owner
The object that owns this object (SimpleCache)
Definition: simple_cache.hh:147
gem5::SimpleCache::getAddrRanges
AddrRangeList getAddrRanges() const
Return the address ranges this cache is responsible for.
Definition: simple_cache.cc:413
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::SimpleCache::CPUSidePort::owner
SimpleCache * owner
The object that owns this object (SimpleCache)
Definition: simple_cache.hh:64
gem5::SimpleCache::accessTiming
void accessTiming(PacketPtr pkt)
Access the cache for a timing access.
Definition: simple_cache.cc:284
gem5::SimpleCache::insert
void insert(PacketPtr pkt)
Insert a block into the cache.
Definition: simple_cache.cc:362
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::SimpleCache::blocked
bool blocked
True if this cache is currently blocked waiting for a response.
Definition: simple_cache.hh:282

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